[LegalizeTypes] Add ROTL/ROTR to ScalarizeVectorResult.

[foad]

Summary

We can scalarize these just like any other binary operation.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47303 caused by D77152.

[foad]

The test case attached to the bug is huge, and I haven't had much luck reducing it yet, so I don't know how to add a test for this.

[RKSimon]

LGTM, ideally a reduced test case needs to be added - via bugpoint/whatever.

[spatel]

I thought a non-native vector type would trigger this, but this might be a different bug?

$ cat rot.ll 
define <2 x i16> @var_funnnel_v2i16(<2 x i16> %x, <2 x i16> %amt) nounwind {
  %res = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %x, <2 x i16> %x, <2 x i16> %amt)
  ret <2 x i16> %res
}

declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
$ llc -o - rot.ll -mtriple=aarch64 
	.text
	.file	"rot.ll"
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: ./llc -o - rot.ll -mtriple=aarch64 
1.	Running pass 'Function Pass Manager' on module 'rot.ll'.
2.	Running pass 'AArch64 Instruction Selection' on function '@var_funnnel_v2i16'
0  llc                      0x0000000107f0bcd5 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 37
1  llc                      0x0000000107f0aa68 llvm::sys::RunSignalHandlers() + 248
2  llc                      0x0000000107f0c2ec SignalHandler(int) + 268
3  libsystem_platform.dylib 0x00007fff6a6725fd _sigtramp + 29
4  libsystem_platform.dylib 0x0000000000000010 _sigtramp + 18446603338731018800
5  llc                      0x0000000107c8f9f3 llvm::DAGTypeLegalizer::ReplaceValueWith(llvm::SDValue, llvm::SDValue) + 67
6  llc                      0x0000000107c66090 llvm::DAGTypeLegalizer::PromoteIntegerResult(llvm::SDNode*, unsigned int) + 784
7  llc                      0x0000000107c8ef38 llvm::DAGTypeLegalizer::run() + 2808

[ro]

I've just completed a sparcv9-sun-solaris2.11 2-stage RelWithDebInfo build with your patch applied: worked fine. Thanks a lot for the quick fix.

[foad]

In D86601#2238500, @spatel wrote:

I thought a non-native vector type would trigger this, but this might be a different bug?

$ cat rot.ll 
define <2 x i16> @var_funnnel_v2i16(<2 x i16> %x, <2 x i16> %amt) nounwind {
  %res = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %x, <2 x i16> %x, <2 x i16> %amt)
  ret <2 x i16> %res
}

declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
$ llc -o - rot.ll -mtriple=aarch64 
	.text
	.file	"rot.ll"
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: ./llc -o - rot.ll -mtriple=aarch64 
1.	Running pass 'Function Pass Manager' on module 'rot.ll'.
2.	Running pass 'AArch64 Instruction Selection' on function '@var_funnnel_v2i16'
0  llc                      0x0000000107f0bcd5 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 37
1  llc                      0x0000000107f0aa68 llvm::sys::RunSignalHandlers() + 248
2  llc                      0x0000000107f0c2ec SignalHandler(int) + 268
3  libsystem_platform.dylib 0x00007fff6a6725fd _sigtramp + 29
4  libsystem_platform.dylib 0x0000000000000010 _sigtramp + 18446603338731018800
5  llc                      0x0000000107c8f9f3 llvm::DAGTypeLegalizer::ReplaceValueWith(llvm::SDValue, llvm::SDValue) + 67
6  llc                      0x0000000107c66090 llvm::DAGTypeLegalizer::PromoteIntegerResult(llvm::SDNode*, unsigned int) + 784
7  llc                      0x0000000107c8ef38 llvm::DAGTypeLegalizer::run() + 2808

This looks like a different bug to me. DAGTypeLegalizer::PromoteIntRes_Rotate doesn't cope with TargetLowering::expandROT failing. I don't know how this is supposed to work.

[foad]

In D86601#2238283, @RKSimon wrote:

LGTM, ideally a reduced test case needs to be added - via bugpoint/whatever.

I tried reducing the .ll from the bug report with llvm-reduce. I got it down from 19 MB to 8 MB ...

[spatel]

In D86601#2238536, @foad wrote:

In D86601#2238500, @spatel wrote:

I thought a non-native vector type would trigger this, but this might be a different bug?

$ cat rot.ll 
define <2 x i16> @var_funnnel_v2i16(<2 x i16> %x, <2 x i16> %amt) nounwind {
  %res = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %x, <2 x i16> %x, <2 x i16> %amt)
  ret <2 x i16> %res
}

declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
$ llc -o - rot.ll -mtriple=aarch64 
	.text
	.file	"rot.ll"
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: ./llc -o - rot.ll -mtriple=aarch64 
1.	Running pass 'Function Pass Manager' on module 'rot.ll'.
2.	Running pass 'AArch64 Instruction Selection' on function '@var_funnnel_v2i16'
0  llc                      0x0000000107f0bcd5 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 37
1  llc                      0x0000000107f0aa68 llvm::sys::RunSignalHandlers() + 248
2  llc                      0x0000000107f0c2ec SignalHandler(int) + 268
3  libsystem_platform.dylib 0x00007fff6a6725fd _sigtramp + 29
4  libsystem_platform.dylib 0x0000000000000010 _sigtramp + 18446603338731018800
5  llc                      0x0000000107c8f9f3 llvm::DAGTypeLegalizer::ReplaceValueWith(llvm::SDValue, llvm::SDValue) + 67
6  llc                      0x0000000107c66090 llvm::DAGTypeLegalizer::PromoteIntegerResult(llvm::SDNode*, unsigned int) + 784
7  llc                      0x0000000107c8ef38 llvm::DAGTypeLegalizer::run() + 2808

This looks like a different bug to me. DAGTypeLegalizer::PromoteIntRes_Rotate doesn't cope with TargetLowering::expandROT failing. I don't know how this is supposed to work.

Filed as:
https://llvm.org/PR47320

[RKSimon]

@foad I managed to reduce the test case to this:

llc -mtriple=sparcv9--

define i32 @PR47303() {
bb:
  %i = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> undef, <4 x i64> undef, <4 x i64> <i64 57, i64 27, i64 12, i64 33>)
  %i1 = add <4 x i64> %i, zeroinitializer
  %i2 = add <4 x i64> %i1, zeroinitializer
  %i3 = extractelement <4 x i64> %i2, i32 0
  %i4 = add i64 0, %i3
  %i5 = xor i64 0, %i4
  %i6 = trunc i64 %i5 to i32
  %i7 = mul i32 %i6, 797982799
  ret i32 %i7
}
declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
   case ISD::SREM:
   case ISD::SUB:
   case ISD::UDIV:
   case ISD::UREM:
   case ISD::XOR:
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
+  case ISD::ROTL:
+  case ISD::ROTR:
     R = ScalarizeVecRes_BinOp(N);
     break;
   case ISD::FMA:
   case ISD::FSHL:
   case ISD::FSHR:
     R = ScalarizeVecRes_TernaryOp(N);
     break;