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[AArch64] Optimize instruction selection for certain vector shuffles

Authored by miyuki on Aug 19 2020, 9:41 AM.



This patch adds code to recognize vector shuffles which can be
represented as VDUP (splat) of a vector lane with of a different
(wider) type than the original vector lane type.

For example:

shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>

is essentially:

shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 0, i32 0>

Such patterns are generated by the SelectionDAG machinery in some cases
(see DAGCombiner::visitBITCAST in DAGCombiner.cpp, the "Remove double
bitcasts from shuffles" part).

Diff Detail

Event Timeline

miyuki created this revision.Aug 19 2020, 9:41 AM
miyuki requested review of this revision.Aug 19 2020, 9:41 AM

Looks nice. Perhaps add a few more negative tests for the various different "return false"'s


You can make this an else and drop the continue.


Would this be nullptr or BlockElts.end()?


BlockElts.size() -> NumEltsPerBlock, as it's used more consistently.

miyuki updated this revision to Diff 286848.Aug 20 2020, 10:05 AM
  1. Addressed review comments
  2. Added a cast back to the original type
miyuki marked 3 inline comments as done.Aug 20 2020, 10:07 AM

Thanks. One last question about this new bit of code.


I'm not sure I see when will this happen. Aren't we returning a node that isn't of type VT? I think that would cause problems. It looks like the output from constructDup should be of type VT, unless I'm missing something.

miyuki updated this revision to Diff 288049.Aug 26 2020, 11:13 AM

Cast to the correct type

miyuki marked an inline comment as done.Aug 26 2020, 11:13 AM
dmgreen accepted this revision.Aug 27 2020, 12:14 AM

Thanks. LGTM

This revision is now accepted and ready to land.Aug 27 2020, 12:14 AM
This revision was landed with ongoing or failed builds.Aug 27 2020, 3:07 AM
This revision was automatically updated to reflect the committed changes.