VFRCZ* are AMD XOP instructions.
That instruction set is only supported by bdver[1-4] cpu models.
These instructions are unrelated to the instructions grouped by the WriteFRnd sched class.
On bdver[1-3], they have latency of 10, as per agner's tables,
and as per my llvm-exegesis measurements for bdver2.
Which is different from what WriteFRnd specifies (5).
Now, the test coverage is saddening. We currently don't have any
dedicated sched models for any of these 4 cpu's, so the test coverage decreases.
I'm not sure this can be improved, until the said sched model is ready for integration...