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andreadb (Andrea Di Biagio)
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May 9 2013, 11:10 AM (401 w, 3 d)

Recent Activity

Sat, Jan 16

andreadb added a comment to D86644: [llvm-mca] Initial implementation of output serialization using JSON.

I really like this JSON format. Thanks a lot!

Sat, Jan 16, 5:11 AM · Restricted Project

Dec 18 2020

andreadb requested changes to D86644: [llvm-mca] Initial implementation of output serialization using JSON.

The json output is better now.
However there are things about the implementation that must be fixed/changed (see my comments below).

Dec 18 2020, 6:03 AM · Restricted Project
andreadb added inline comments to D86644: [llvm-mca] Initial implementation of output serialization using JSON.
Dec 18 2020, 5:31 AM · Restricted Project

Nov 25 2020

andreadb accepted D92026: [TableGen][SchedModels] Get rid of hasVariant. NFC.

Thanks for checking.

Nov 25 2020, 2:57 AM · Restricted Project

Nov 24 2020

andreadb added a comment to D92026: [TableGen][SchedModels] Get rid of hasVariant. NFC.

When you say that " Subtarget files are unchanged by the patch", does it mean that you have checked all the targets or just ARM?

I checked ARM, AArch64 and X86. Does any other have scheduling enabled?

Nov 24 2020, 9:01 AM · Restricted Project
andreadb added a comment to D92026: [TableGen][SchedModels] Get rid of hasVariant. NFC.

I've only skimmed through the code, but it looks like a nice improvement.

Nov 24 2020, 7:33 AM · Restricted Project
andreadb accepted D91704: [llvm-mca] Fix processing thumb instruction set.

LGTM

Nov 24 2020, 7:16 AM · Restricted Project
andreadb added a comment to D91704: [llvm-mca] Fix processing thumb instruction set.

A couple of minor nits. Otherwise the llvm-mca change looks good.
Thanks.

Nov 24 2020, 1:51 AM · Restricted Project

Nov 23 2020

andreadb added a comment to D91704: [llvm-mca] Fix processing thumb instruction set.

Thanks for the updated patch.

Nov 23 2020, 4:17 AM · Restricted Project

Nov 18 2020

andreadb added a comment to D91410: [llvm][clang][mlir] Add checks for the return values from Target::createXXX to prevent protential null deref.

LGTM for llvm-mca.

Nov 18 2020, 4:36 PM · Restricted Project, Restricted Project, Restricted Project
andreadb added inline comments to D91704: [llvm-mca] Fix processing thumb instruction set.
Nov 18 2020, 4:34 PM · Restricted Project

Oct 31 2020

andreadb committed rG0e20666db3ac: [MCA][LSUnit] Correctly update the internal group flags on store barrier… (authored by andreadb).
[MCA][LSUnit] Correctly update the internal group flags on store barrier…
Oct 31 2020, 5:01 AM

Oct 26 2020

andreadb added a comment to D90150: [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate.

Much better. Thanks a lot :)

Oct 26 2020, 7:46 AM · Restricted Project
andreadb added a comment to D90150: [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate.

The new predicate looks good. I only have a couple of nits (see below).

Oct 26 2020, 7:08 AM · Restricted Project

Oct 23 2020

andreadb added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

I'm happy with that explanation, and would be happy with this patch going ahead. The mir test above seems to show it failing before and working now.

Oct 23 2020, 10:41 AM · Restricted Project
andreadb accepted D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .
Oct 23 2020, 10:25 AM · Restricted Project
andreadb added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

So, it doesn't look like the lowering is doing anything odd with the operand sequence. It should be fine.
At this point, the only explanation is that the original predicate was never really executed for that write variant. So it was never tested. I don't see other alternatives honestly.

Oct 23 2020, 10:17 AM · Restricted Project
andreadb added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

(paranoia level).
Are we sure that the lowering of MachineInstr to MCInst is preserving the operand sequence? Can it be that the immediate is at position 4 for the MCInst only?
I have no idea how an ldrbt looks like as a MachineInstr. The original check should have triggered an assertion too for MachineInstr then...

I was not aware that was a thing that could happen!

I'm unsure if anything would ever generate an ldrbt with negative postinc reg and shift from codegen, so it might be difficult to test. And may never have been tested in the past.

Oct 23 2020, 9:51 AM · Restricted Project
andreadb added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

Should it always have been checking operand 4 then? I think that makes sense

IMO, it was incorrectly checking for operand 3. I've got an assertion when switched to MC pred

Oct 23 2020, 8:56 AM · Restricted Project
andreadb added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

Should it always have been checking operand 4 then? I think that makes sense

(More of a commit message might make it more obvious why changes are being made ;) )

Oct 23 2020, 8:47 AM · Restricted Project
andreadb added a comment to D90045: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate.

Nice!
The predicates look good to me.

Oct 23 2020, 8:23 AM · Restricted Project
andreadb added inline comments to D90045: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate.
Oct 23 2020, 7:32 AM · Restricted Project
andreadb added a comment to D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate.

The new predicate looks good to me.

Oct 23 2020, 7:22 AM · Restricted Project
andreadb added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

Could you please add more context to the diff? I don't remember how IsLdstsoScaledPredX2 was defined.

Oct 23 2020, 7:18 AM · Restricted Project
andreadb accepted D90017: [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC.

LGTM.

Oct 23 2020, 3:07 AM · Restricted Project

Oct 22 2020

andreadb added a comment to D89939: [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate.

Nice patch!
The new predicate looks good.

Oct 22 2020, 2:37 AM · Restricted Project

Oct 21 2020

andreadb added a comment to D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.

Addressed

Oct 21 2020, 9:48 AM · Restricted Project
andreadb added inline comments to D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.
Oct 21 2020, 9:30 AM · Restricted Project
andreadb added a comment to D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.

Hi Eugene,

Oct 21 2020, 7:47 AM · Restricted Project

Oct 19 2020

andreadb added inline comments to D89460: [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate.
Oct 19 2020, 3:02 AM · Restricted Project

Oct 17 2020

andreadb added a comment to D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.

I have been thinking a bit more about this patch.
D89553 is surprisingly less complicated than I have originally thought it was. It definitely touches more files. However the majority of the changes are very mechanical (mostly boilerplate required for the new MCSchedPredicate to work). It is also a non-controversial change, since it doesn't modify the layout of MCInst.
Bonus point: by changing the signature of resolveVariantSchedClass() we potentially enable future developments in the area of MCSchedPredicate (and mca). Basically that change would make it possible for users to declare new predicates on MCinstrDesc (which is definitely not a bad thing!).

Oct 17 2020, 4:10 AM · Restricted Project
andreadb accepted D89553: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate (alternative approach).

The patch is mostly a mechanical change (i.e. a lot of boilerplate to introduce a new scheduling predicate).

Oct 17 2020, 2:58 AM · Restricted Project

Oct 16 2020

andreadb added a comment to D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.

For the record, this is how your patch would look like if you decided to add a new predicate.


I am just trying to be helpful by showing how the alternative approach would look like (in case, if people decide that it is not a good idea to add an extra field to MCInst).

Oct 16 2020, 5:36 AM · Restricted Project
andreadb added inline comments to D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.
Oct 16 2020, 1:46 AM · Restricted Project

Oct 15 2020

andreadb added a comment to D86644: [llvm-mca] Initial implementation of output serialization using JSON.

Hey Wolfgang,
are you still looking at this patch? Do you have any updates?

Oct 15 2020, 3:27 PM · Restricted Project
andreadb added inline comments to D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.
Oct 15 2020, 3:23 PM · Restricted Project

Sep 2 2020

andreadb accepted D87033: [APInt] New member function setBitVal.

Looks good to me.

Sep 2 2020, 12:22 PM · Restricted Project

Aug 28 2020

andreadb added a comment to D86644: [llvm-mca] Initial implementation of output serialization using JSON.

Can it simply be autogenerated, without omitting details?

It would have to be auto-generated based on the readable output, then, using some sort of (python) script that creates the structure independently, or did you have something else in mind?
Aug 28 2020, 8:47 AM · Restricted Project

Aug 26 2020

andreadb added a reviewer for D86644: [llvm-mca] Initial implementation of output serialization using JSON: RKSimon.
Aug 26 2020, 12:32 PM · Restricted Project
andreadb added a comment to D86644: [llvm-mca] Initial implementation of output serialization using JSON.

Thanks Wolfgang for working on this.

Aug 26 2020, 12:26 PM · Restricted Project

Aug 25 2020

andreadb added inline comments to D86390: [llvm-mca][NFC] Refactor instruction printing.
Aug 25 2020, 1:38 AM · Restricted Project
andreadb accepted D86390: [llvm-mca][NFC] Refactor instruction printing.

Looks good to me module a few nits (see below).

Aug 25 2020, 1:06 AM · Restricted Project

Aug 21 2020

andreadb accepted D86177: [llvm-mca][NFC] Separate calculation of display data from its display in the summary and instruction info views.

LGTM

Aug 21 2020, 8:59 AM · Restricted Project

Aug 20 2020

andreadb added a comment to D86177: [llvm-mca][NFC] Separate calculation of display data from its display in the summary and instruction info views.

Nice!

Thank you Andrea!

I agree with Roman in that we should not guarantee stability of data and/or structure.
Also, changes to the output structure should always be advertised (for example, by adding a line in the release notes), so that people are always aware of it.

I must confess I am not very informed about the issues regarding stability. Doesn't data stability depend on the scheduling model? I don't see how llvm-mca could guarantee it if that changes.

Aug 20 2020, 1:25 AM · Restricted Project

Aug 19 2020

andreadb added a comment to D86177: [llvm-mca][NFC] Separate calculation of display data from its display in the summary and instruction info views.

Thanks Wolfgang! I always wanted to add a structured output to llvm-mca.
Thanks for working on this.

Aug 19 2020, 2:04 AM · Restricted Project

Aug 12 2020

andreadb added a comment to D85165: [X86][MC][Target] Initial backend support a tune CPU to support -mtune.

Cheers. Now I have a better understanding of why you wanted to check latencies.

Aug 12 2020, 12:31 PM · Restricted Project
andreadb added a comment to D85165: [X86][MC][Target] Initial backend support a tune CPU to support -mtune.

@andreadb @RKSimon or @efriedma do any of you have suggestions for simple scheduler tests for this? I was hoping I could use -print-schedule like we used to but that no longer exists.

Aug 12 2020, 11:12 AM · Restricted Project

May 19 2020

andreadb committed rG0980c9c6f155: [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). (authored by andreadb).
[X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975).
May 19 2020, 10:23 AM
andreadb closed D80201: [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). NFC.
May 19 2020, 10:22 AM · Restricted Project
andreadb updated the diff for D80201: [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). NFC.

Addressed review comments.

May 19 2020, 8:07 AM · Restricted Project
andreadb updated the diff for D80201: [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). NFC.

Patch updated. This time with context.

May 19 2020, 3:45 AM · Restricted Project
andreadb created D80201: [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). NFC.
May 19 2020, 3:45 AM · Restricted Project

May 10 2020

andreadb committed rG47b95d7cf462: [MCA][InstrBuilder] Correctly mark reserved resources in… (authored by andreadb).
[MCA][InstrBuilder] Correctly mark reserved resources in…
May 10 2020, 11:42 AM

May 5 2020

andreadb committed rG5bb5fa3c0a29: Forgot to add a -mtriple to a test. NFC (authored by andreadb).
Forgot to add a -mtriple to a test. NFC
May 5 2020, 3:12 AM
andreadb committed rG5578ec32f9c4: [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as… (authored by andreadb).
[MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as…
May 5 2020, 2:39 AM
andreadb closed D79351: [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as depedent (PR45793)..
May 5 2020, 2:39 AM · Restricted Project

May 4 2020

andreadb updated the diff for D79351: [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as depedent (PR45793)..

Addressed review comments.

May 4 2020, 3:38 PM · Restricted Project
andreadb added a comment to D79351: [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as depedent (PR45793)..

I'm totally cool with this change; however, it's been a while since I've taken a look at this part of MCA. I'll let other's chime in as well, but +1 from me.

May 4 2020, 1:26 PM · Restricted Project
andreadb updated the diff for D79351: [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as depedent (PR45793)..

Patch updated. This time with full context.

May 4 2020, 12:53 PM · Restricted Project
andreadb created D79351: [MCA] Fixed a bug where loads and stores were sometimes incorrectly marked as depedent (PR45793)..
May 4 2020, 12:21 PM · Restricted Project

Mar 30 2020

andreadb accepted D77073: [llvm-mca] Cleanup unnecessary includes from headers.

LGTM

Mar 30 2020, 1:37 PM · Restricted Project

Mar 24 2020

andreadb added a comment to D76580: [X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form.

Rebase after MCInstPrinter::PrintBranchImmAsAddress is added to the parent patch.

llvm-mc -filetype=asm and llvm-mca are unaffected now.

Mar 24 2020, 1:28 PM · Restricted Project
andreadb added inline comments to D76580: [X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form.
Mar 24 2020, 11:16 AM · Restricted Project

Mar 8 2020

andreadb added a comment to D75214: [MCA][WIP] Modelling CPU front-ent: Fetch stage/Instruction Byte Buffer unit/Decoder stage (PR42202).

we still need to keep into account that processors may implement loop caches.

I agree this may be useful, but i currently don't believe that to be a blocker here.

Mar 8 2020, 5:18 AM · Restricted Project

Feb 27 2020

andreadb accepted D74976: [CostModel][X86] Improve extract/insert element costs (PR43605).

Looks good to me.

Feb 27 2020, 6:57 AM · Restricted Project
andreadb added a comment to D75214: [MCA][WIP] Modelling CPU front-ent: Fetch stage/Instruction Byte Buffer unit/Decoder stage (PR42202).

Hi Roman,

Feb 27 2020, 4:30 AM · Restricted Project

Feb 7 2020

andreadb added a comment to D74155: [X86CmovConversion] Make heuristic for optimized cmov depth more conservative (PR44539).

Okay. Then this needs tests.
There's a lot of bugs referenced in https://bugs.llvm.org/show_bug.cgi?id=44539,
at least one of those should be affected, right?

Feb 7 2020, 4:42 AM · Restricted Project

Feb 6 2020

andreadb added a comment to D74155: [X86CmovConversion] Make heuristic for optimized cmov depth more conservative (PR44539).

Forgot to say that this should also be backported to the release branch.

Feb 6 2020, 12:43 PM · Restricted Project
andreadb accepted D74155: [X86CmovConversion] Make heuristic for optimized cmov depth more conservative (PR44539).

LGTM (modulo Roman comment). It fixes the regression in libgav1. So I am happy.

Feb 6 2020, 12:43 PM · Restricted Project

Feb 5 2020

andreadb accepted D74000: [X86] Improve the gather scheduler models for SkylakeClient and SkylakeServer.

LGTM too.

Feb 5 2020, 10:15 AM · Restricted Project
andreadb added a comment to D74000: [X86] Improve the gather scheduler models for SkylakeClient and SkylakeServer.

I've added avx512 gather instructions to llvm-mca resource tests. I wanted to pre-commit them, but since some of them have 0 uops in the existing data, llvm-mca gave an error.

What I can do in the short term is to remove the check for MayLoad and MayStore in mca (I have a patch ready for it). That check is too conservative, since we were already test if an instruction consumes processor resources in general. That is enough to fix the issue that you saw with zero uOP gathers.

Feb 5 2020, 7:03 AM · Restricted Project
andreadb committed rGaaaeac616692: [MCA] Remove verification check on MayLoad and MayStore. NFCI (authored by andreadb).
[MCA] Remove verification check on MayLoad and MayStore. NFCI
Feb 5 2020, 5:53 AM
andreadb added a comment to D74000: [X86] Improve the gather scheduler models for SkylakeClient and SkylakeServer.

I've added avx512 gather instructions to llvm-mca resource tests. I wanted to pre-commit them, but since some of them have 0 uops in the existing data, llvm-mca gave an error.

Feb 5 2020, 4:19 AM · Restricted Project

Feb 3 2020

andreadb accepted D73844: [X86] Update the haswell and broadwell scheduler information for gather instructions.

Here is the idea: why don't we just add new writes for gather instructions (ideally a new write per each type of gather)?. I think that we shall consider this alternative (maybe in a follow up patch? I don't particularly mind..). Not sure if other people agree with this.

Adding gather (and broadcast) schedule classes is on my backlog - as long as the InstRW entries are correct, I'll replace them when I get aroung to doing it. So, staying with InstRW for this patch is fine by me.

Feb 3 2020, 6:25 AM · Restricted Project
andreadb added a comment to D73844: [X86] Update the haswell and broadwell scheduler information for gather instructions.

The change looks pretty mechanical, and I trust that the new numbers are correct.

Feb 3 2020, 4:01 AM · Restricted Project

Jan 16 2020

andreadb added inline comments to D72480: [Matrix] Add info about number of operations to remarks..
Jan 16 2020, 6:38 AM · Restricted Project
andreadb added inline comments to D72480: [Matrix] Add info about number of operations to remarks..
Jan 16 2020, 6:25 AM · Restricted Project

Jan 9 2020

andreadb accepted D72385: Clarify how llvm-mca detects att vs intel syntax..

LGTM

Jan 9 2020, 6:56 AM · Restricted Project

Oct 29 2019

andreadb committed rG67720e7bf7df: Revert "[NFC] Replace a linked list in LiveDebugVariables pass with a DenseMap" (authored by andreadb).
Revert "[NFC] Replace a linked list in LiveDebugVariables pass with a DenseMap"
Oct 29 2019, 5:20 AM
andreadb added a reverting change for rG8af5ada09319: [NFC] Replace a linked list in LiveDebugVariables pass with a DenseMap: rG67720e7bf7df: Revert "[NFC] Replace a linked list in LiveDebugVariables pass with a DenseMap".
Oct 29 2019, 5:20 AM

Oct 14 2019

andreadb committed rGb744abb4f6a9: [X86][BtVer2] Improved latency and throughput of float/vector loads and stores. (authored by andreadb).
[X86][BtVer2] Improved latency and throughput of float/vector loads and stores.
Oct 14 2019, 4:14 AM
andreadb closed D68871: [X86][BtVer2] Improved latency and throughput of float/vector loads and stores..
Oct 14 2019, 4:14 AM · Restricted Project

Oct 11 2019

andreadb added a comment to D68871: [X86][BtVer2] Improved latency and throughput of float/vector loads and stores..

Posted the output from llvm-exegesis for all the affected instructions.

Oct 11 2019, 8:14 AM · Restricted Project
andreadb created D68871: [X86][BtVer2] Improved latency and throughput of float/vector loads and stores..
Oct 11 2019, 8:14 AM · Restricted Project
andreadb added a comment to D67950: [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel.

I am not convinced that this patch is correct. Isn’t the problem that your model was wrongly marked as complete?

Oct 11 2019, 3:31 AM · Restricted Project
andreadb added a comment to D67950: [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel.

I am not convinced that this patch is correct. Isn’t the problem that your model was wrongly marked as complete?

Oct 11 2019, 2:46 AM · Restricted Project

Oct 10 2019

andreadb accepted D68714: [MCA] Show aggregate over Average Wait times for the whole snippet (PR43219).

LGTM

Oct 10 2019, 7:16 AM · Restricted Project
andreadb added inline comments to D68714: [MCA] Show aggregate over Average Wait times for the whole snippet (PR43219).
Oct 10 2019, 4:14 AM · Restricted Project

Oct 9 2019

andreadb added inline comments to D68714: [MCA] Show aggregate over Average Wait times for the whole snippet (PR43219).
Oct 9 2019, 12:44 PM · Restricted Project
andreadb added a comment to D68714: [MCA] Show aggregate over Average Wait times for the whole snippet (PR43219).

Thanks Roman.

Oct 9 2019, 10:56 AM · Restricted Project

Oct 8 2019

andreadb committed rG8d6651f7b11e: [MCA][LSUnit] Track loads and stores until retirement. (authored by andreadb).
[MCA][LSUnit] Track loads and stores until retirement.
Oct 8 2019, 3:46 AM
andreadb closed D68266: [MCA][LSUnit] Track loads and stores until retirement..
Oct 8 2019, 3:46 AM · Restricted Project

Oct 4 2019

andreadb added a comment to D68266: [MCA][LSUnit] Track loads and stores until retirement..

Thanks Roman,

Oct 4 2019, 3:52 AM · Restricted Project

Oct 1 2019

andreadb created D68266: [MCA][LSUnit] Track loads and stores until retirement..
Oct 1 2019, 5:08 AM · Restricted Project

Sep 30 2019

andreadb committed rG2730df2e164b: [MCA] Use references to LSUnitBase in class Scheduler and add helper methods to… (authored by andreadb).
[MCA] Use references to LSUnitBase in class Scheduler and add helper methods to…
Sep 30 2019, 10:24 AM
andreadb accepted D68190: [llvm-mca] Add a -mattr flag.

LGTM

Sep 30 2019, 8:47 AM · Restricted Project

Sep 22 2019

andreadb added inline comments to D67875: [X86] X86DAGToDAGISel::matchBEXTRFromAndImm(): if can't use BEXTR, fallback to BZHI (PR43381).
Sep 22 2019, 1:36 PM · Restricted Project

Sep 19 2019

andreadb committed rGe0900f285bb5: [MCA] Improved cost computation for loop carried dependencies in the bottleneck… (authored by andreadb).
[MCA] Improved cost computation for loop carried dependencies in the bottleneck…
Sep 19 2019, 9:05 AM

Sep 6 2019

andreadb accepted D67192: [X86] Use MOVSX instead of CBW to extend i8 to AX for i8 sdiv..

Looks good to me.
Thanks for the changes in FixupBWInsts. Personally I was already happy with the previous version patch. But this one is looks even better.

Sep 6 2019, 3:51 AM · Restricted Project

Sep 2 2019

andreadb committed rG528f68144b7e: [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions. (authored by andreadb).
[X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.
Sep 2 2019, 5:34 AM