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Differential D11833

s/NDEBUG/LLVM_NDEBUG/ in most places
Needs RevisionPublic

Authored by • tstellarAMD on Aug 7 2015, 8:27 AM.

Details

Reviewers
echristo
beanz
dexonsmith
Summary

The goal of this change is to remove the dependency on NDEBUG in
headers, so that library users can freely choose whether or not to
define this value when building their applications.

Diff Detail

Event Timeline

• tstellarAMD updated this revision to Diff 31512.Aug 7 2015, 8:27 AM
• tstellarAMD retitled this revision from to s/NDEBUG/LLVM_NDEBUG/ in most places.
• tstellarAMD updated this object.
• tstellarAMD added reviewers: echristo, chandlerc, beanz.
• tstellarAMD added a subscriber: llvm-commits.
Herald added subscribers: qcolombet, MatzeB. · View Herald TranscriptAug 7 2015, 8:27 AM
• tstellarAMD added a comment.Sep 10 2015, 8:31 AM

Ping.

chandlerc removed a reviewer: chandlerc.Apr 6 2016, 10:58 PM
philip.pfaffe added a subscriber: philip.pfaffe.Jul 1 2016, 11:33 AM
rogerjarrett added a subscriber: rogerjarrett.Nov 12 2019, 1:20 PM
Herald added subscribers: asbirlea, jsji, tpr and 17 others. · View Herald TranscriptNov 12 2019, 1:20 PM
rogerjarrett added a comment.Nov 12 2019, 1:28 PM

+1 on Goal In particular the use of NDEBUG in external interface header files causes significant pain when using the header files in a build environment that uses NDEBUG

What steps are needed to move this change forward?

Herald added a subscriber: • wuzish. · View Herald TranscriptNov 12 2019, 1:28 PM
mehdi_amini added a comment.Nov 13 2019, 12:58 PM
In D11833#1742834, @rogerjarrett wrote:

+1 on Goal In particular the use of NDEBUG in external interface header files causes significant pain when using the header files in a build environment that uses NDEBUG

What steps are needed to move this change forward?

Is this still a problem? Aren't all the header checks guarded by LLVM_ENABLE_ABI_BREAKING_CHECKS now?

rogerjarrett added a comment.Nov 13 2019, 1:34 PM

Issue appears to still be present
For example: In llvm/include/llvm/Transforms/Scalar/LoopPassManager.h

https://llvm.org/doxygen/LoopPassManager_8h_source.html

line 207
...
#ifndef NDEBUG

for (Loop *NewL : NewChildLoops)
  assert(NewL->getParentLoop() == CurrentL && "All of the new loops must "
                                              "be immediate children of "
                                              "the current loop!");

#endif
...

Running the command: find . -iname '*.h' | xargs grep '^#' -- | grep -vE '^.*:.*(LLVM_|cplusplus|endif|else|include|define )' | grep NDEBUG | wc -l

returns
150 instances of NDEBUG in .h files the 9.0.0 code base.

Best,
--Roger

mehdi_amini added a comment.Nov 13 2019, 1:48 PM

OK but these NDEBUG aren't necessarily harmful, are they?

IIRC we added LLVM_ENABLE_ABI_BREAKING_CHECKS to cover the cases because previous using NDEBUG in the client was *required* to match the settings at the time LLVM was built.

dexonsmith added a comment.Nov 13 2019, 1:53 PM
In D11833#1744718, @mehdi_amini wrote:

OK but these NDEBUG aren't necessarily harmful, are they?

IIRC we added LLVM_ENABLE_ABI_BREAKING_CHECKS to cover the cases because previous using NDEBUG in the client was *required* to match the settings at the time LLVM was built.

Agree with Mehdi, we should only be using LLVM_ENABLE_ABI_BREAKING_CHECKS when it's actually an ABI-breaking check.

arsenm removed a subscriber: arsenm.Nov 13 2019, 6:29 PM
Meinersbur added a subscriber: Meinersbur.Nov 14 2019, 8:39 AM

s/NDEBUG/LLVM_NDEBUG/ will not apply to the use of NDEBUG in assert.h. Most uses of NDEBUG are hidden in the assert macro.

In the aforementioned use of NDEBUG:

#ifndef NDEBUG
for (Loop *NewL : NewChildLoops)
  assert(NewL->getParentLoop() == CurrentL && "All of the new loops must "
                                              "be immediate children of "
                                              "the current loop!");
#endif

it is used only to avoid the overhead of iteration when the assert macro expands to nothing.

Consequences:

  1. Even with LLVM_NDEBUG defined, plain assert's will still be evaluated.
  2. To have complete asserts build, LLVM_NDEBUG and NDEBUG must be defined at the same time.
  3. NDEBUG and assert are linked by the C/C++ language. To unlink, we must also introduce llvm_assert (or ban assert in headers).
dexonsmith requested changes to this revision.Nov 14 2019, 11:44 AM

Stepping back to look at the goals:

The goal of this change is to remove the dependency on NDEBUG in
headers, so that library users can freely choose whether or not to
define this value when building their applications.

This seems like the same goal that introducing LLVM_ENABLE_ABI_BREAKING_CHECKS had. Is this patch a change in direction for how to achieve the goal? Or is there a subtlety here, and it's achieving something additional that LLVM_ENABLE_ABI_BREAKING_CHECKS does not? I think it at least deserves an llvm-dev discussion before proceeding (I just took a look through the archives and don't see one, apologies if I missed it).

Note that there are some nice benefits to the existing LLVM_ENABLE_ABI_BREAKING_CHECKS model:

  • A developer that needs a stable ABI can configure LLVM_ENABLE_ABI_BREAKING_CHECKS (either on or off) to achieve that.
  • If not specified explicitly, LLVM_ENABLE_ABI_BREAKING_CHECKS is controlled by whether it's an "asserts" build. This gives the right behaviour for most developers most of the time.
  • The common case of assertions that are not ABI-breaking don't need special treatment.
    • Always controlled by whether it's an "asserts" build.
    • Uses the syntax that people expect.

I think the llvm-dev discussion would need to establish (a) why this isn't working (but the new thing would work) and/or (b) what additional benefits splitting off LLVM_NDEBUG and llvm_assert would solve. It's also not clear what's supposed to happen for other LLVM sub-projects, like Clang. Should they grow clang_assert or use llvm_assert? (BTW, it would probably be nice to also introduce an llvm_abi_breaking_assert or something to simplify the existing model, whether or not this change moves forward.)

I also think changes like this should be documented in the coding standards; I'm requesting changes on that basis.

This revision now requires changes to proceed.Nov 14 2019, 11:44 AM
rogerjarrett added a comment.Nov 14 2019, 3:04 PM

Yes I agree the example case I provided is not an LLVM_ENABLE_ABI_BREAKING_CHECKS modification

I agree with dexonsmith on these points

  1. That LLVM_ENABLE_ABI_BREAKING_CHECKS addresses the issue
  1. The use LLVM_ENABLE_ABI_BREAKING_CHECKS should be better documented in the llvm-project coding standards

2a. And the use or non-use llvm_assert(),assert(), NDEBUG,.. should also be documented

  1. That we need to think through how this model should apply to subprojects: clang, lld, mlir,...

How can I help enable this discussion of 1 and 2?

Rhetorical question: What is the definition of when LLVM_ENABLE_ABI_BREAKING_CHECKS should be used ?

Candidate answer: Any change to the class/template/... that changes the size of class or template

Correct usage example from: llvm/include/llvm/Analysis/LoopInfo.h
...
template <class BlockT, class LoopT> class LoopBase {

LoopT *ParentLoop;
// Loops contained entirely within this one.
std::vector<LoopT *> SubLoops;

// The list of blocks in this loop. First entry is the header node.
std::vector<BlockT *> Blocks;

SmallPtrSet<const BlockT *, 8> DenseBlockSet;

#if LLVM_ENABLE_ABI_BREAKING_CHECKS

/// Indicator that this loop is no longer a valid loop.
bool IsInvalid = false;

#endif
...

header example that appears to need LLVM_ENABLE_ABI_BREAKING_CHECKS

File: llvm/include/llvm/CodeGen/LiveIntervalUnion.h

Line 101 in llvm-project 9.0.0
...
// Print union, using TRI to translate register names

void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;

#ifndef NDEBUG

// Verify the live intervals in this union and add them to the visited set.
void verify(LiveVirtRegBitSet& VisitedVRegs);

#endif
...

How do I confirm that the use of NDEBUG in a header file is correct?

kovdan01 mentioned this in D120714: [CodeGen] Place SDNode debug ID declaration under appropriate #if.Mar 11 2022, 7:12 AM

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Diff 31512

Makefile.rules

Show First 20 Lines • Show All 377 Lines • ▼ Show 20 Linesifeq ($(ENABLE_COVERAGE),1)
CXX.Flags += -ftest-coverage -fprofile-arcs CXX.Flags += -ftest-coverage -fprofile-arcs
C.Flags += -ftest-coverage -fprofile-arcs C.Flags += -ftest-coverage -fprofile-arcs
LD.Flags += -ftest-coverage -fprofile-arcs LD.Flags += -ftest-coverage -fprofile-arcs
endif endif
# If DISABLE_ASSERTIONS=1 is specified (make command line or configured), # If DISABLE_ASSERTIONS=1 is specified (make command line or configured),
# then disable assertions by defining the appropriate preprocessor symbols. # then disable assertions by defining the appropriate preprocessor symbols.
ifeq ($(DISABLE_ASSERTIONS),1) ifeq ($(DISABLE_ASSERTIONS),1)
CPP.Defines += -DNDEBUG CPP.Defines += -DNDEBUG -DLLVM_NDEBUG
else else
BuildMode := $(BuildMode)+Asserts BuildMode := $(BuildMode)+Asserts
CPP.Defines += -D_DEBUG CPP.Defines += -D_DEBUG
endif endif
# If ENABLE_EXPENSIVE_CHECKS=1 is specified (make command line or # If ENABLE_EXPENSIVE_CHECKS=1 is specified (make command line or
# configured), then enable expensive checks by defining the # configured), then enable expensive checks by defining the
# appropriate preprocessor symbols. # appropriate preprocessor symbols.
▲ Show 20 Lines • Show All 1,777 Lines • Show Last 20 Lines

cmake/modules/HandleLLVMOptions.cmake

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines foreach (flags_var_to_scrub
CMAKE_CXX_FLAGS_MINSIZEREL CMAKE_CXX_FLAGS_MINSIZEREL
CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELEASE
CMAKE_C_FLAGS_RELWITHDEBINFO CMAKE_C_FLAGS_RELWITHDEBINFO
CMAKE_C_FLAGS_MINSIZEREL) CMAKE_C_FLAGS_MINSIZEREL)
string (REGEX REPLACE "(^| )[/-]D *NDEBUG($| )" " " string (REGEX REPLACE "(^| )[/-]D *NDEBUG($| )" " "
"${flags_var_to_scrub}" "${${flags_var_to_scrub}}") "${flags_var_to_scrub}" "${${flags_var_to_scrub}}")
endforeach() endforeach()
endif() endif()
else()
add_definitions( -DLLVM_NDEBUG )
endif() endif()
string(TOUPPER "${LLVM_ABI_BREAKING_CHECKS}" uppercase_LLVM_ABI_BREAKING_CHECKS) string(TOUPPER "${LLVM_ABI_BREAKING_CHECKS}" uppercase_LLVM_ABI_BREAKING_CHECKS)
if( uppercase_LLVM_ABI_BREAKING_CHECKS STREQUAL "WITH_ASSERTS" ) if( uppercase_LLVM_ABI_BREAKING_CHECKS STREQUAL "WITH_ASSERTS" )
if( LLVM_ENABLE_ASSERTIONS ) if( LLVM_ENABLE_ASSERTIONS )
set( LLVM_ENABLE_ABI_BREAKING_CHECKS 1 ) set( LLVM_ENABLE_ABI_BREAKING_CHECKS 1 )
endif() endif()
▲ Show 20 Lines • Show All 476 Lines • Show Last 20 Lines

include/llvm/ADT/IntervalMap.h

Show First 20 Lines • Show All 357 Lines • ▼ Show 20 Lines for (unsigned m = n + 1; m != Nodes; ++m) {
CurSize[m] += d; CurSize[m] += d;
CurSize[n] -= d; CurSize[n] -= d;
// Keep going if the current node was exhausted. // Keep going if the current node was exhausted.
if (CurSize[n] >= NewSize[n]) if (CurSize[n] >= NewSize[n])
break; break;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned n = 0; n != Nodes; n++) for (unsigned n = 0; n != Nodes; n++)
assert(CurSize[n] == NewSize[n] && "Insufficient element shuffle"); assert(CurSize[n] == NewSize[n] && "Insufficient element shuffle");
#endif #endif
} }
/// IntervalMapImpl::distribute - Compute a new distribution of node elements /// IntervalMapImpl::distribute - Compute a new distribution of node elements
/// after an overflow or underflow. Reserve space for a new element at Position, /// after an overflow or underflow. Reserve space for a new element at Position,
/// and compute the node that will hold Position after redistributing node /// and compute the node that will hold Position after redistributing node
▲ Show 20 Lines • Show All 1,782 Lines • Show Last 20 Lines

include/llvm/ADT/Statistic.h

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linespublic:
void construct(const char *name, const char *desc) { void construct(const char *name, const char *desc) {
Name = name; Desc = desc; Name = name; Desc = desc;
Value = 0; Initialized = false; Value = 0; Initialized = false;
} }
// Allow use of this class as the value itself. // Allow use of this class as the value itself.
operator unsigned() const { return Value; } operator unsigned() const { return Value; }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_STATS) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_STATS)
const Statistic &operator=(unsigned Val) { const Statistic &operator=(unsigned Val) {
Value = Val; Value = Val;
return init(); return init();
} }
const Statistic &operator++() { const Statistic &operator++() {
// FIXME: This function and all those that follow carefully use an // FIXME: This function and all those that follow carefully use an
// atomic operation to update the value safely in the presence of // atomic operation to update the value safely in the presence of
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines#else // Statistics are disabled in release builds.
const Statistic &operator*=(const unsigned &V) { const Statistic &operator*=(const unsigned &V) {
return *this; return *this;
} }
const Statistic &operator/=(const unsigned &V) { const Statistic &operator/=(const unsigned &V) {
return *this; return *this;
} }
#endif // !defined(NDEBUG) || defined(LLVM_ENABLE_STATS) #endif // !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_STATS)
protected: protected:
Statistic &init() { Statistic &init() {
bool tmp = Initialized; bool tmp = Initialized;
sys::MemoryFence(); sys::MemoryFence();
if (!tmp) RegisterStatistic(); if (!tmp) RegisterStatistic();
TsanHappensAfter(this); TsanHappensAfter(this);
return *this; return *this;
Show All 24 Lines

include/llvm/Analysis/DominanceFrontier.h

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Linespublic:
/// this dominance frontier base. Otherwise return false. /// this dominance frontier base. Otherwise return false.
bool compare(DominanceFrontierBase<BlockT> &Other) const; bool compare(DominanceFrontierBase<BlockT> &Other) const;
/// print - Convert to human readable form /// print - Convert to human readable form
/// ///
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
/// dump - Dump the dominance frontier to dbgs(). /// dump - Dump the dominance frontier to dbgs().
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dump() const; void dump() const;
#endif #endif
}; };
//===------------------------------------- //===-------------------------------------
/// DominanceFrontier Class - Concrete subclass of DominanceFrontierBase that is /// DominanceFrontier Class - Concrete subclass of DominanceFrontierBase that is
/// used to compute a forward dominator frontiers. /// used to compute a forward dominator frontiers.
/// ///
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include/llvm/Analysis/DominanceFrontierImpl.h

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines for (const BlockT *BB : BBs) {
BB->printAsOperand(OS, false); BB->printAsOperand(OS, false);
else else
OS << "<<exit node>>"; OS << "<<exit node>>";
} }
OS << '\n'; OS << '\n';
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
template <class BlockT> template <class BlockT>
void DominanceFrontierBase<BlockT>::dump() const { void DominanceFrontierBase<BlockT>::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
template <class BlockT> template <class BlockT>
const typename ForwardDominanceFrontierBase<BlockT>::DomSetType & const typename ForwardDominanceFrontierBase<BlockT>::DomSetType &
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include/llvm/Analysis/LoopAccessAnalysis.h

Show First 20 Lines • Show All 525 Lines • ▼ Show 20 Lines SmallVector<Instruction *, 4> getInstructionsForAccess(Value *Ptr,
return DepChecker.getInstructionsForAccess(Ptr, isWrite); return DepChecker.getInstructionsForAccess(Ptr, isWrite);
} }
/// \brief Print the information about the memory accesses in the loop. /// \brief Print the information about the memory accesses in the loop.
void print(raw_ostream &OS, unsigned Depth = 0) const; void print(raw_ostream &OS, unsigned Depth = 0) const;
/// \brief Used to ensure that if the analysis was run with speculating the /// \brief Used to ensure that if the analysis was run with speculating the
/// value of symbolic strides, the client queries it with the same assumption. /// value of symbolic strides, the client queries it with the same assumption.
/// Only used in DEBUG build but we don't want NDEBUG-dependent ABI. /// Only used in DEBUG build but we don't want LLVM_NDEBUG-dependent ABI.
unsigned NumSymbolicStrides; unsigned NumSymbolicStrides;
/// \brief Checks existence of store to invariant address inside loop. /// \brief Checks existence of store to invariant address inside loop.
/// If the loop has any store to invariant address, then it returns true, /// If the loop has any store to invariant address, then it returns true,
/// else returns false. /// else returns false.
bool hasStoreToLoopInvariantAddress() const { bool hasStoreToLoopInvariantAddress() const {
return StoreToLoopInvariantAddress; return StoreToLoopInvariantAddress;
} }
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include/llvm/Analysis/LoopInfoImpl.h

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 LinesreplaceChildLoopWith(LoopT *OldChild, LoopT *NewChild) {
*I = NewChild; *I = NewChild;
OldChild->ParentLoop = nullptr; OldChild->ParentLoop = nullptr;
NewChild->ParentLoop = static_cast<LoopT *>(this); NewChild->ParentLoop = static_cast<LoopT *>(this);
} }
/// verifyLoop - Verify loop structure /// verifyLoop - Verify loop structure
template<class BlockT, class LoopT> template<class BlockT, class LoopT>
void LoopBase<BlockT, LoopT>::verifyLoop() const { void LoopBase<BlockT, LoopT>::verifyLoop() const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(!Blocks.empty() && "Loop header is missing"); assert(!Blocks.empty() && "Loop header is missing");
// Setup for using a depth-first iterator to visit every block in the loop. // Setup for using a depth-first iterator to visit every block in the loop.
SmallVector<BlockT*, 8> ExitBBs; SmallVector<BlockT*, 8> ExitBBs;
getExitBlocks(ExitBBs); getExitBlocks(ExitBBs);
llvm::SmallPtrSet<BlockT*, 8> VisitSet; llvm::SmallPtrSet<BlockT*, 8> VisitSet;
VisitSet.insert(ExitBBs.begin(), ExitBBs.end()); VisitSet.insert(ExitBBs.begin(), ExitBBs.end());
df_ext_iterator<BlockT*, llvm::SmallPtrSet<BlockT*, 8> > df_ext_iterator<BlockT*, llvm::SmallPtrSet<BlockT*, 8> >
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void LoopInfoBase<BlockT, LoopT>::verify() const { void LoopInfoBase<BlockT, LoopT>::verify() const {
DenseSet<const LoopT*> Loops; DenseSet<const LoopT*> Loops;
for (iterator I = begin(), E = end(); I != E; ++I) { for (iterator I = begin(), E = end(); I != E; ++I) {
assert(!(*I)->getParentLoop() && "Top-level loop has a parent!"); assert(!(*I)->getParentLoop() && "Top-level loop has a parent!");
(*I)->verifyLoopNest(&Loops); (*I)->verifyLoopNest(&Loops);
} }
// Verify that blocks are mapped to valid loops. // Verify that blocks are mapped to valid loops.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (auto &Entry : BBMap) { for (auto &Entry : BBMap) {
const BlockT *BB = Entry.first; const BlockT *BB = Entry.first;
LoopT *L = Entry.second; LoopT *L = Entry.second;
assert(Loops.count(L) && "orphaned loop"); assert(Loops.count(L) && "orphaned loop");
assert(L->contains(BB) && "orphaned block"); assert(L->contains(BB) && "orphaned block");
} }
#endif #endif
} }
} // End llvm namespace } // End llvm namespace
#endif #endif

include/llvm/Analysis/RegionInfo.h

Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Linespublic:
/// @brief Print the region. /// @brief Print the region.
/// ///
/// @param OS The output stream the Region is printed to. /// @param OS The output stream the Region is printed to.
/// @param printTree Print also the tree of subregions. /// @param printTree Print also the tree of subregions.
/// @param level The indentation level used for printing. /// @param level The indentation level used for printing.
void print(raw_ostream &OS, bool printTree = true, unsigned level = 0, void print(raw_ostream &OS, bool printTree = true, unsigned level = 0,
PrintStyle Style = PrintNone) const; PrintStyle Style = PrintNone) const;
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// @brief Print the region to stderr. /// @brief Print the region to stderr.
void dump() const; void dump() const;
#endif #endif
/// @brief Check if the region contains a BasicBlock. /// @brief Check if the region contains a BasicBlock.
/// ///
/// @param BB The BasicBlock that might be contained in this Region. /// @param BB The BasicBlock that might be contained in this Region.
/// @return True if the block is contained in the region otherwise false. /// @return True if the block is contained in the region otherwise false.
▲ Show 20 Lines • Show All 293 Lines • ▼ Show 20 Linesprivate:
// calculate - detect all regions in function and build the region tree. // calculate - detect all regions in function and build the region tree.
void calculate(FuncT &F); void calculate(FuncT &F);
public: public:
static bool VerifyRegionInfo; static bool VerifyRegionInfo;
static typename RegionT::PrintStyle printStyle; static typename RegionT::PrintStyle printStyle;
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dump() const; void dump() const;
#endif #endif
void releaseMemory(); void releaseMemory();
/// @brief Get the smallest region that contains a BasicBlock. /// @brief Get the smallest region that contains a BasicBlock.
/// ///
/// @param BB The basic block. /// @param BB The basic block.
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include/llvm/Analysis/RegionInfoImpl.h

Show First 20 Lines • Show All 502 Lines • ▼ Show 20 Lines if (print_tree) {
for (const_iterator RI = begin(), RE = end(); RI != RE; ++RI) for (const_iterator RI = begin(), RE = end(); RI != RE; ++RI)
(*RI)->print(OS, print_tree, level + 1, Style); (*RI)->print(OS, print_tree, level + 1, Style);
} }
if (Style != PrintNone) if (Style != PrintNone)
OS.indent(level * 2) << "} \n"; OS.indent(level * 2) << "} \n";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
template <class Tr> template <class Tr>
void RegionBase<Tr>::dump() const { void RegionBase<Tr>::dump() const {
print(dbgs(), true, getDepth(), RegionInfoBase<Tr>::printStyle); print(dbgs(), true, getDepth(), RegionInfoBase<Tr>::printStyle);
} }
#endif #endif
template <class Tr> template <class Tr>
void RegionBase<Tr>::clearNodeCache() { void RegionBase<Tr>::clearNodeCache() {
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template <class Tr> template <class Tr>
void RegionInfoBase<Tr>::print(raw_ostream &OS) const { void RegionInfoBase<Tr>::print(raw_ostream &OS) const {
OS << "Region tree:\n"; OS << "Region tree:\n";
TopLevelRegion->print(OS, true, 0, printStyle); TopLevelRegion->print(OS, true, 0, printStyle);
OS << "End region tree\n"; OS << "End region tree\n";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
template <class Tr> template <class Tr>
void RegionInfoBase<Tr>::dump() const { print(dbgs()); } void RegionInfoBase<Tr>::dump() const { print(dbgs()); }
#endif #endif
template <class Tr> template <class Tr>
void RegionInfoBase<Tr>::releaseMemory() { void RegionInfoBase<Tr>::releaseMemory() {
BBtoRegion.clear(); BBtoRegion.clear();
if (TopLevelRegion) if (TopLevelRegion)
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include/llvm/Analysis/ScalarEvolution.h

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines public:
/// but not a constant. /// but not a constant.
bool isNonConstantNegative() const; bool isNonConstantNegative() const;
/// print - Print out the internal representation of this scalar to the /// print - Print out the internal representation of this scalar to the
/// specified stream. This should really only be used for debugging /// specified stream. This should really only be used for debugging
/// purposes. /// purposes.
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dump - This method is used for debugging. /// dump - This method is used for debugging.
/// ///
void dump() const; void dump() const;
#endif #endif
}; };
// Specialize FoldingSetTrait for SCEV to avoid needing to compute // Specialize FoldingSetTrait for SCEV to avoid needing to compute
// temporary FoldingSetNodeID values. // temporary FoldingSetNodeID values.
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include/llvm/Analysis/ScalarEvolutionExpander.h

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> {
/// \brief When invoked from LSR, the expander is in "strength reduction" /// \brief When invoked from LSR, the expander is in "strength reduction"
/// mode. The only difference is that phi's are only reused if they are /// mode. The only difference is that phi's are only reused if they are
/// already in "expanded" form. /// already in "expanded" form.
bool LSRMode; bool LSRMode;
typedef IRBuilder<true, TargetFolder> BuilderType; typedef IRBuilder<true, TargetFolder> BuilderType;
BuilderType Builder; BuilderType Builder;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const char *DebugType; const char *DebugType;
#endif #endif
friend struct SCEVVisitor<SCEVExpander, Value*>; friend struct SCEVVisitor<SCEVExpander, Value*>;
public: public:
/// \brief Construct a SCEVExpander in "canonical" mode. /// \brief Construct a SCEVExpander in "canonical" mode.
explicit SCEVExpander(ScalarEvolution &se, const DataLayout &DL, explicit SCEVExpander(ScalarEvolution &se, const DataLayout &DL,
const char *name) const char *name)
: SE(se), DL(DL), IVName(name), IVIncInsertLoop(nullptr), : SE(se), DL(DL), IVName(name), IVIncInsertLoop(nullptr),
IVIncInsertPos(nullptr), CanonicalMode(true), LSRMode(false), IVIncInsertPos(nullptr), CanonicalMode(true), LSRMode(false),
Builder(se.getContext(), TargetFolder(DL)) { Builder(se.getContext(), TargetFolder(DL)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DebugType = ""; DebugType = "";
#endif #endif
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void setDebugType(const char* s) { DebugType = s; } void setDebugType(const char* s) { DebugType = s; }
#endif #endif
/// \brief Erase the contents of the InsertedExpressions map so that users /// \brief Erase the contents of the InsertedExpressions map so that users
/// trying to expand the same expression into multiple BasicBlocks or /// trying to expand the same expression into multiple BasicBlocks or
/// different places within the same BasicBlock can do so. /// different places within the same BasicBlock can do so.
void clear() { void clear() {
InsertedExpressions.clear(); InsertedExpressions.clear();
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include/llvm/CodeGen/DIE.h

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Linespublic:
/// Profile - Used to gather unique data for the abbreviation folding set. /// Profile - Used to gather unique data for the abbreviation folding set.
/// ///
void Profile(FoldingSetNodeID &ID) const; void Profile(FoldingSetNodeID &ID) const;
/// Emit - Print the abbreviation using the specified asm printer. /// Emit - Print the abbreviation using the specified asm printer.
/// ///
void Emit(const AsmPrinter *AP) const; void Emit(const AsmPrinter *AP) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O); void print(raw_ostream &O);
void dump(); void dump();
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIEInteger - An integer value DIE. /// DIEInteger - An integer value DIE.
/// ///
Show All 26 Linespublic:
} }
uint64_t getValue() const { return Integer; } uint64_t getValue() const { return Integer; }
void setValue(uint64_t Val) { Integer = Val; } void setValue(uint64_t Val) { Integer = Val; }
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIEExpr - An expression DIE. /// DIEExpr - An expression DIE.
// //
class DIEExpr { class DIEExpr {
const MCExpr *Expr; const MCExpr *Expr;
public: public:
explicit DIEExpr(const MCExpr *E) : Expr(E) {} explicit DIEExpr(const MCExpr *E) : Expr(E) {}
/// getValue - Get MCExpr. /// getValue - Get MCExpr.
/// ///
const MCExpr *getValue() const { return Expr; } const MCExpr *getValue() const { return Expr; }
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIELabel - A label DIE. /// DIELabel - A label DIE.
// //
class DIELabel { class DIELabel {
const MCSymbol *Label; const MCSymbol *Label;
public: public:
explicit DIELabel(const MCSymbol *L) : Label(L) {} explicit DIELabel(const MCSymbol *L) : Label(L) {}
/// getValue - Get MCSymbol. /// getValue - Get MCSymbol.
/// ///
const MCSymbol *getValue() const { return Label; } const MCSymbol *getValue() const { return Label; }
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIEDelta - A simple label difference DIE. /// DIEDelta - A simple label difference DIE.
/// ///
class DIEDelta { class DIEDelta {
const MCSymbol *LabelHi; const MCSymbol *LabelHi;
const MCSymbol *LabelLo; const MCSymbol *LabelLo;
public: public:
DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo) : LabelHi(Hi), LabelLo(Lo) {} DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo) : LabelHi(Hi), LabelLo(Lo) {}
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIEString - A container for string values. /// DIEString - A container for string values.
/// ///
class DIEString { class DIEString {
DwarfStringPoolEntryRef S; DwarfStringPoolEntryRef S;
public: public:
DIEString(DwarfStringPoolEntryRef S) : S(S) {} DIEString(DwarfStringPoolEntryRef S) : S(S) {}
/// getString - Grab the string out of the object. /// getString - Grab the string out of the object.
StringRef getString() const { return S.getString(); } StringRef getString() const { return S.getString(); }
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIEEntry - A pointer to another debug information entry. An instance of /// DIEEntry - A pointer to another debug information entry. An instance of
/// this class can also be used as a proxy for a debug information entry not /// this class can also be used as a proxy for a debug information entry not
/// yet defined (ie. types.) /// yet defined (ie. types.)
Show All 12 Linespublic:
static unsigned getRefAddrSize(const AsmPrinter *AP); static unsigned getRefAddrSize(const AsmPrinter *AP);
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const { unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
return Form == dwarf::DW_FORM_ref_addr ? getRefAddrSize(AP) return Form == dwarf::DW_FORM_ref_addr ? getRefAddrSize(AP)
: sizeof(int32_t); : sizeof(int32_t);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// \brief A signature reference to a type unit. /// \brief A signature reference to a type unit.
class DIETypeSignature { class DIETypeSignature {
const DwarfTypeUnit *Unit; const DwarfTypeUnit *Unit;
DIETypeSignature() = delete; DIETypeSignature() = delete;
public: public:
explicit DIETypeSignature(const DwarfTypeUnit &Unit) : Unit(&Unit) {} explicit DIETypeSignature(const DwarfTypeUnit &Unit) : Unit(&Unit) {}
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const { unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
assert(Form == dwarf::DW_FORM_ref_sig8); assert(Form == dwarf::DW_FORM_ref_sig8);
return 8; return 8;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIELocList - Represents a pointer to a location list in the debug_loc /// DIELocList - Represents a pointer to a location list in the debug_loc
/// section. /// section.
// //
class DIELocList { class DIELocList {
// Index into the .debug_loc vector. // Index into the .debug_loc vector.
size_t Index; size_t Index;
public: public:
DIELocList(size_t I) : Index(I) {} DIELocList(size_t I) : Index(I) {}
/// getValue - Grab the current index out. /// getValue - Grab the current index out.
size_t getValue() const { return Index; } size_t getValue() const { return Index; }
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIEValue - A debug information entry value. Some of these roughly correlate /// DIEValue - A debug information entry value. Some of these roughly correlate
/// to DWARF attribute classes. /// to DWARF attribute classes.
/// ///
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines#include "llvm/CodeGen/DIEValue.def"
/// EmitValue - Emit value via the Dwarf writer. /// EmitValue - Emit value via the Dwarf writer.
/// ///
void EmitValue(const AsmPrinter *AP) const; void EmitValue(const AsmPrinter *AP) const;
/// SizeOf - Return the size of a value in bytes. /// SizeOf - Return the size of a value in bytes.
/// ///
unsigned SizeOf(const AsmPrinter *AP) const; unsigned SizeOf(const AsmPrinter *AP) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
void dump() const; void dump() const;
#endif #endif
}; };
struct IntrusiveBackListNode { struct IntrusiveBackListNode {
PointerIntPair<IntrusiveBackListNode *, 1> Next; PointerIntPair<IntrusiveBackListNode *, 1> Next;
IntrusiveBackListNode() : Next(this, true) {} IntrusiveBackListNode() : Next(this, true) {}
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Linespublic:
} }
/// Find a value in the DIE with the attribute given. /// Find a value in the DIE with the attribute given.
/// ///
/// Returns a default-constructed DIEValue (where \a DIEValue::getType() /// Returns a default-constructed DIEValue (where \a DIEValue::getType()
/// gives \a DIEValue::isNone) if no such attribute exists. /// gives \a DIEValue::isNone) if no such attribute exists.
DIEValue findAttribute(dwarf::Attribute Attribute) const; DIEValue findAttribute(dwarf::Attribute Attribute) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O, unsigned IndentCount = 0) const; void print(raw_ostream &O, unsigned IndentCount = 0) const;
void dump(); void dump();
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIELoc - Represents an expression location. /// DIELoc - Represents an expression location.
// //
Show All 20 Lines dwarf::Form BestForm(unsigned DwarfVersion) const {
if ((unsigned int)Size == Size) if ((unsigned int)Size == Size)
return dwarf::DW_FORM_block4; return dwarf::DW_FORM_block4;
return dwarf::DW_FORM_block; return dwarf::DW_FORM_block;
} }
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// DIEBlock - Represents a block of values. /// DIEBlock - Represents a block of values.
// //
class DIEBlock : public DIEValueList { class DIEBlock : public DIEValueList {
Show All 16 Lines dwarf::Form BestForm() const {
if ((unsigned int)Size == Size) if ((unsigned int)Size == Size)
return dwarf::DW_FORM_block4; return dwarf::DW_FORM_block4;
return dwarf::DW_FORM_block; return dwarf::DW_FORM_block;
} }
void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const; void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const; void print(raw_ostream &O) const;
#endif #endif
}; };
} // end llvm namespace } // end llvm namespace
#endif #endif

include/llvm/CodeGen/FunctionLoweringInfo.h

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Linespublic:
SmallVector<unsigned, 50> StatepointStackSlots; SmallVector<unsigned, 50> StatepointStackSlots;
/// MBB - The current block. /// MBB - The current block.
MachineBasicBlock *MBB; MachineBasicBlock *MBB;
/// MBB - The current insert position inside the current block. /// MBB - The current insert position inside the current block.
MachineBasicBlock::iterator InsertPt; MachineBasicBlock::iterator InsertPt;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
SmallPtrSet<const Instruction *, 8> CatchInfoLost; SmallPtrSet<const Instruction *, 8> CatchInfoLost;
SmallPtrSet<const Instruction *, 8> CatchInfoFound; SmallPtrSet<const Instruction *, 8> CatchInfoFound;
#endif #endif
struct LiveOutInfo { struct LiveOutInfo {
unsigned NumSignBits : 31; unsigned NumSignBits : 31;
bool IsValid : 1; bool IsValid : 1;
APInt KnownOne, KnownZero; APInt KnownOne, KnownZero;
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include/llvm/CodeGen/LiveInterval.h

Show First 20 Lines • Show All 555 Lines • ▼ Show 20 Lines public:
void flushSegmentSet(); void flushSegmentSet();
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
void dump() const; void dump() const;
/// \brief Walk the range and assert if any invariants fail to hold. /// \brief Walk the range and assert if any invariants fail to hold.
/// ///
/// Note that this is a no-op when asserts are disabled. /// Note that this is a no-op when asserts are disabled.
#ifdef NDEBUG #ifdef LLVM_NDEBUG
void verify() const {} void verify() const {}
#else #else
void verify() const; void verify() const;
#endif #endif
protected: protected:
/// Append a segment to the list of segments. /// Append a segment to the list of segments.
void append(const LiveRange::Segment S); void append(const LiveRange::Segment S);
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines public:
} }
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
void dump() const; void dump() const;
/// \brief Walks the interval and assert if any invariants fail to hold. /// \brief Walks the interval and assert if any invariants fail to hold.
/// ///
/// Note that this is a no-op when asserts are disabled. /// Note that this is a no-op when asserts are disabled.
#ifdef NDEBUG #ifdef LLVM_NDEBUG
void verify(const MachineRegisterInfo *MRI = nullptr) const {} void verify(const MachineRegisterInfo *MRI = nullptr) const {}
#else #else
void verify(const MachineRegisterInfo *MRI = nullptr) const; void verify(const MachineRegisterInfo *MRI = nullptr) const;
#endif #endif
private: private:
/// Appends @p Range to SubRanges list. /// Appends @p Range to SubRanges list.
void appendSubRange(SubRange *Range) { void appendSubRange(SubRange *Range) {
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include/llvm/CodeGen/LiveIntervalUnion.h

Show All 18 Lines
#include "llvm/ADT/IntervalMap.h" #include "llvm/ADT/IntervalMap.h"
#include "llvm/CodeGen/LiveInterval.h" #include "llvm/CodeGen/LiveInterval.h"
namespace llvm { namespace llvm {
class TargetRegisterInfo; class TargetRegisterInfo;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// forward declaration // forward declaration
template <unsigned Element> class SparseBitVector; template <unsigned Element> class SparseBitVector;
typedef SparseBitVector<128> LiveVirtRegBitSet; typedef SparseBitVector<128> LiveVirtRegBitSet;
#endif #endif
/// Compare a live virtual register segment to a LiveIntervalUnion segment. /// Compare a live virtual register segment to a LiveIntervalUnion segment.
inline bool inline bool
overlap(const LiveInterval::Segment &VRSeg, overlap(const LiveInterval::Segment &VRSeg,
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Linespublic:
} }
// Remove all inserted virtual registers. // Remove all inserted virtual registers.
void clear() { Segments.clear(); ++Tag; } void clear() { Segments.clear(); ++Tag; }
// Print union, using TRI to translate register names // Print union, using TRI to translate register names
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const; void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify the live intervals in this union and add them to the visited set. // Verify the live intervals in this union and add them to the visited set.
void verify(LiveVirtRegBitSet& VisitedVRegs); void verify(LiveVirtRegBitSet& VisitedVRegs);
#endif #endif
/// Query interferences between a single live virtual register and a live /// Query interferences between a single live virtual register and a live
/// interval union. /// interval union.
class Query { class Query {
LiveIntervalUnion *LiveUnion; LiveIntervalUnion *LiveUnion;
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include/llvm/CodeGen/MachineRegisterInfo.h

Show First 20 Lines • Show All 539 Lines • ▼ Show 20 Linespublic:
MachineInstr *getUniqueVRegDef(unsigned Reg) const; MachineInstr *getUniqueVRegDef(unsigned Reg) const;
/// clearKillFlags - Iterate over all the uses of the given register and /// clearKillFlags - Iterate over all the uses of the given register and
/// clear the kill flag from the MachineOperand. This function is used by /// clear the kill flag from the MachineOperand. This function is used by
/// optimization passes which extend register lifetimes and need only /// optimization passes which extend register lifetimes and need only
/// preserve conservative kill flag information. /// preserve conservative kill flag information.
void clearKillFlags(unsigned Reg) const; void clearKillFlags(unsigned Reg) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void dumpUses(unsigned RegNo) const; void dumpUses(unsigned RegNo) const;
#endif #endif
/// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
/// throughout the function. It is safe to move instructions that read such /// throughout the function. It is safe to move instructions that read such
/// a physreg. /// a physreg.
bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
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include/llvm/CodeGen/MachineScheduler.h

Show First 20 Lines • Show All 235 Lines • ▼ Show 20 Linesprotected:
/// The bottom of the unscheduled zone. /// The bottom of the unscheduled zone.
MachineBasicBlock::iterator CurrentBottom; MachineBasicBlock::iterator CurrentBottom;
/// Record the next node in a scheduled cluster. /// Record the next node in a scheduled cluster.
const SUnit *NextClusterPred; const SUnit *NextClusterPred;
const SUnit *NextClusterSucc; const SUnit *NextClusterSucc;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// The number of instructions scheduled so far. Used to cut off the /// The number of instructions scheduled so far. Used to cut off the
/// scheduler at the point determined by misched-cutoff. /// scheduler at the point determined by misched-cutoff.
unsigned NumInstrsScheduled; unsigned NumInstrsScheduled;
#endif #endif
public: public:
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S, ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
bool IsPostRA) bool IsPostRA)
: ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA, : ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA,
/*RemoveKillFlags=*/IsPostRA, C->LIS), /*RemoveKillFlags=*/IsPostRA, C->LIS),
AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(), AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) { CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
NumInstrsScheduled = 0; NumInstrsScheduled = 0;
#endif #endif
} }
// Provide a vtable anchor // Provide a vtable anchor
~ScheduleDAGMI() override; ~ScheduleDAGMI() override;
/// Return true if this DAG supports VReg liveness and RegPressure. /// Return true if this DAG supports VReg liveness and RegPressure.
▲ Show 20 Lines • Show All 350 Lines • ▼ Show 20 Linesprivate:
// Is the scheduled region resource limited vs. latency limited. // Is the scheduled region resource limited vs. latency limited.
bool IsResourceLimited; bool IsResourceLimited;
// Record the highest cycle at which each resource has been reserved by a // Record the highest cycle at which each resource has been reserved by a
// scheduled instruction. // scheduled instruction.
SmallVector<unsigned, 16> ReservedCycles; SmallVector<unsigned, 16> ReservedCycles;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Remember the greatest possible stall as an upper bound on the number of // Remember the greatest possible stall as an upper bound on the number of
// times we should retry the pending queue because of a hazard. // times we should retry the pending queue because of a hazard.
unsigned MaxObservedStall; unsigned MaxObservedStall;
#endif #endif
public: public:
/// Pending queues extend the ready queues with the same ID and the /// Pending queues extend the ready queues with the same ID and the
/// PendingFlag set. /// PendingFlag set.
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Linespublic:
void removeReady(SUnit *SU); void removeReady(SUnit *SU);
/// Call this before applying any other heuristics to the Available queue. /// Call this before applying any other heuristics to the Available queue.
/// Updates the Available/Pending Q's if necessary and returns the single /// Updates the Available/Pending Q's if necessary and returns the single
/// available instruction, or NULL if there are multiple candidates. /// available instruction, or NULL if there are multiple candidates.
SUnit *pickOnlyChoice(); SUnit *pickOnlyChoice();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void dumpScheduledState(); void dumpScheduledState();
#endif #endif
}; };
/// Base class for GenericScheduler. This class maintains information about /// Base class for GenericScheduler. This class maintains information about
/// scheduling candidates based on TargetSchedModel making it easy to implement /// scheduling candidates based on TargetSchedModel making it easy to implement
/// heuristics for either preRA or postRA scheduling. /// heuristics for either preRA or postRA scheduling.
class GenericSchedulerBase : public MachineSchedStrategy { class GenericSchedulerBase : public MachineSchedStrategy {
public: public:
/// Represent the type of SchedCandidate found within a single queue. /// Represent the type of SchedCandidate found within a single queue.
/// pickNodeBidirectional depends on these listed by decreasing priority. /// pickNodeBidirectional depends on these listed by decreasing priority.
enum CandReason { enum CandReason {
NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax, NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax,
ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce, ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder}; TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static const char *getReasonStr(GenericSchedulerBase::CandReason Reason); static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
#endif #endif
/// Policy for scheduling the next instruction in the candidate's zone. /// Policy for scheduling the next instruction in the candidate's zone.
struct CandPolicy { struct CandPolicy {
bool ReduceLatency; bool ReduceLatency;
unsigned ReduceResIdx; unsigned ReduceResIdx;
unsigned DemandResIdx; unsigned DemandResIdx;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesprotected:
SchedRemainder Rem; SchedRemainder Rem;
protected: protected:
GenericSchedulerBase(const MachineSchedContext *C): GenericSchedulerBase(const MachineSchedContext *C):
Context(C), SchedModel(nullptr), TRI(nullptr) {} Context(C), SchedModel(nullptr), TRI(nullptr) {}
void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone, void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
SchedBoundary *OtherZone); SchedBoundary *OtherZone);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void traceCandidate(const SchedCandidate &Cand); void traceCandidate(const SchedCandidate &Cand);
#endif #endif
}; };
/// GenericScheduler shrinks the unscheduled zone using heuristics to balance /// GenericScheduler shrinks the unscheduled zone using heuristics to balance
/// the schedule. /// the schedule.
class GenericScheduler : public GenericSchedulerBase { class GenericScheduler : public GenericSchedulerBase {
ScheduleDAGMILive *DAG; ScheduleDAGMILive *DAG;
▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines

include/llvm/CodeGen/PBQP/ReductionRules.h

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines void applyR2(GraphT &G, typename GraphT::NodeId NId) {
} }
G.disconnectEdge(YXEId, YNId); G.disconnectEdge(YXEId, YNId);
G.disconnectEdge(ZXEId, ZNId); G.disconnectEdge(ZXEId, ZNId);
// TODO: Try to normalize newly added/modified edge. // TODO: Try to normalize newly added/modified edge.
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Does this Cost vector have any register options ? // Does this Cost vector have any register options ?
template <typename VectorT> template <typename VectorT>
bool hasRegisterOptions(const VectorT &V) { bool hasRegisterOptions(const VectorT &V) {
unsigned VL = V.getLength(); unsigned VL = V.getLength();
// An empty or spill only cost vector does not provide any register option. // An empty or spill only cost vector does not provide any register option.
if (VL <= 1) if (VL <= 1)
return false; return false;
Show All 28 Lines Solution backpropagate(GraphT& G, StackT stack) {
Solution s; Solution s;
while (!stack.empty()) { while (!stack.empty()) {
NodeId NId = stack.back(); NodeId NId = stack.back();
stack.pop_back(); stack.pop_back();
RawVector v = G.getNodeCosts(NId); RawVector v = G.getNodeCosts(NId);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Although a conservatively allocatable node can be allocated to a register, // Although a conservatively allocatable node can be allocated to a register,
// spilling it may provide a lower cost solution. Assert here that spilling // spilling it may provide a lower cost solution. Assert here that spilling
// is done by choice, not because there were no register available. // is done by choice, not because there were no register available.
if (G.getNodeMetadata(NId).wasConservativelyAllocatable()) if (G.getNodeMetadata(NId).wasConservativelyAllocatable())
assert(hasRegisterOptions(v) && "A conservatively allocatable node " assert(hasRegisterOptions(v) && "A conservatively allocatable node "
"must have available register options"); "must have available register options");
#endif #endif
Show All 21 Lines

include/llvm/CodeGen/RegAllocPBQP.h

Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Lines typedef enum {
NotProvablyAllocatable, NotProvablyAllocatable,
ConservativelyAllocatable, ConservativelyAllocatable,
OptimallyReducible OptimallyReducible
} ReductionState; } ReductionState;
NodeMetadata() NodeMetadata()
: RS(Unprocessed), NumOpts(0), DeniedOpts(0), OptUnsafeEdges(nullptr), : RS(Unprocessed), NumOpts(0), DeniedOpts(0), OptUnsafeEdges(nullptr),
VReg(0) VReg(0)
#ifndef NDEBUG #ifndef LLVM_NDEBUG
, everConservativelyAllocatable(false) , everConservativelyAllocatable(false)
#endif #endif
{} {}
// FIXME: Re-implementing default behavior to work around MSVC. Remove once // FIXME: Re-implementing default behavior to work around MSVC. Remove once
// MSVC synthesizes move constructors properly. // MSVC synthesizes move constructors properly.
NodeMetadata(const NodeMetadata &Other) NodeMetadata(const NodeMetadata &Other)
: RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts), : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts),
OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg), OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg),
AllowedRegs(Other.AllowedRegs) AllowedRegs(Other.AllowedRegs)
#ifndef NDEBUG #ifndef LLVM_NDEBUG
, everConservativelyAllocatable(Other.everConservativelyAllocatable) , everConservativelyAllocatable(Other.everConservativelyAllocatable)
#endif #endif
{ {
if (NumOpts > 0) { if (NumOpts > 0) {
std::copy(&Other.OptUnsafeEdges[0], &Other.OptUnsafeEdges[NumOpts], std::copy(&Other.OptUnsafeEdges[0], &Other.OptUnsafeEdges[NumOpts],
&OptUnsafeEdges[0]); &OptUnsafeEdges[0]);
} }
} }
// FIXME: Re-implementing default behavior to work around MSVC. Remove once // FIXME: Re-implementing default behavior to work around MSVC. Remove once
// MSVC synthesizes move constructors properly. // MSVC synthesizes move constructors properly.
NodeMetadata(NodeMetadata &&Other) NodeMetadata(NodeMetadata &&Other)
: RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts), : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts),
OptUnsafeEdges(std::move(Other.OptUnsafeEdges)), VReg(Other.VReg), OptUnsafeEdges(std::move(Other.OptUnsafeEdges)), VReg(Other.VReg),
AllowedRegs(std::move(Other.AllowedRegs)) AllowedRegs(std::move(Other.AllowedRegs))
#ifndef NDEBUG #ifndef LLVM_NDEBUG
, everConservativelyAllocatable(Other.everConservativelyAllocatable) , everConservativelyAllocatable(Other.everConservativelyAllocatable)
#endif #endif
{} {}
// FIXME: Re-implementing default behavior to work around MSVC. Remove once // FIXME: Re-implementing default behavior to work around MSVC. Remove once
// MSVC synthesizes move constructors properly. // MSVC synthesizes move constructors properly.
NodeMetadata& operator=(const NodeMetadata &Other) { NodeMetadata& operator=(const NodeMetadata &Other) {
RS = Other.RS; RS = Other.RS;
NumOpts = Other.NumOpts; NumOpts = Other.NumOpts;
DeniedOpts = Other.DeniedOpts; DeniedOpts = Other.DeniedOpts;
OptUnsafeEdges.reset(new unsigned[NumOpts]); OptUnsafeEdges.reset(new unsigned[NumOpts]);
std::copy(Other.OptUnsafeEdges.get(), Other.OptUnsafeEdges.get() + NumOpts, std::copy(Other.OptUnsafeEdges.get(), Other.OptUnsafeEdges.get() + NumOpts,
OptUnsafeEdges.get()); OptUnsafeEdges.get());
VReg = Other.VReg; VReg = Other.VReg;
AllowedRegs = Other.AllowedRegs; AllowedRegs = Other.AllowedRegs;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
everConservativelyAllocatable = Other.everConservativelyAllocatable; everConservativelyAllocatable = Other.everConservativelyAllocatable;
#endif #endif
return *this; return *this;
} }
// FIXME: Re-implementing default behavior to work around MSVC. Remove once // FIXME: Re-implementing default behavior to work around MSVC. Remove once
// MSVC synthesizes move constructors properly. // MSVC synthesizes move constructors properly.
NodeMetadata& operator=(NodeMetadata &&Other) { NodeMetadata& operator=(NodeMetadata &&Other) {
RS = Other.RS; RS = Other.RS;
NumOpts = Other.NumOpts; NumOpts = Other.NumOpts;
DeniedOpts = Other.DeniedOpts; DeniedOpts = Other.DeniedOpts;
OptUnsafeEdges = std::move(Other.OptUnsafeEdges); OptUnsafeEdges = std::move(Other.OptUnsafeEdges);
VReg = Other.VReg; VReg = Other.VReg;
AllowedRegs = std::move(Other.AllowedRegs); AllowedRegs = std::move(Other.AllowedRegs);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
everConservativelyAllocatable = Other.everConservativelyAllocatable; everConservativelyAllocatable = Other.everConservativelyAllocatable;
#endif #endif
return *this; return *this;
} }
void setVReg(unsigned VReg) { this->VReg = VReg; } void setVReg(unsigned VReg) { this->VReg = VReg; }
unsigned getVReg() const { return VReg; } unsigned getVReg() const { return VReg; }
void setAllowedRegs(GraphMetadata::AllowedRegVecRef AllowedRegs) { void setAllowedRegs(GraphMetadata::AllowedRegVecRef AllowedRegs) {
this->AllowedRegs = std::move(AllowedRegs); this->AllowedRegs = std::move(AllowedRegs);
} }
const AllowedRegVector& getAllowedRegs() const { return *AllowedRegs; } const AllowedRegVector& getAllowedRegs() const { return *AllowedRegs; }
void setup(const Vector& Costs) { void setup(const Vector& Costs) {
NumOpts = Costs.getLength() - 1; NumOpts = Costs.getLength() - 1;
OptUnsafeEdges = std::unique_ptr<unsigned[]>(new unsigned[NumOpts]()); OptUnsafeEdges = std::unique_ptr<unsigned[]>(new unsigned[NumOpts]());
} }
ReductionState getReductionState() const { return RS; } ReductionState getReductionState() const { return RS; }
void setReductionState(ReductionState RS) { void setReductionState(ReductionState RS) {
assert(RS >= this->RS && "A node's reduction state can not be downgraded"); assert(RS >= this->RS && "A node's reduction state can not be downgraded");
this->RS = RS; this->RS = RS;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Remember this state to assert later that a non-infinite register // Remember this state to assert later that a non-infinite register
// option was available. // option was available.
if (RS == ConservativelyAllocatable) if (RS == ConservativelyAllocatable)
everConservativelyAllocatable = true; everConservativelyAllocatable = true;
#endif #endif
} }
Show All 14 Lines#endif
} }
bool isConservativelyAllocatable() const { bool isConservativelyAllocatable() const {
return (DeniedOpts < NumOpts) || return (DeniedOpts < NumOpts) ||
(std::find(&OptUnsafeEdges[0], &OptUnsafeEdges[NumOpts], 0) != (std::find(&OptUnsafeEdges[0], &OptUnsafeEdges[NumOpts], 0) !=
&OptUnsafeEdges[NumOpts]); &OptUnsafeEdges[NumOpts]);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool wasConservativelyAllocatable() const { bool wasConservativelyAllocatable() const {
return everConservativelyAllocatable; return everConservativelyAllocatable;
} }
#endif #endif
private: private:
ReductionState RS; ReductionState RS;
unsigned NumOpts; unsigned NumOpts;
unsigned DeniedOpts; unsigned DeniedOpts;
std::unique_ptr<unsigned[]> OptUnsafeEdges; std::unique_ptr<unsigned[]> OptUnsafeEdges;
unsigned VReg; unsigned VReg;
GraphMetadata::AllowedRegVecRef AllowedRegs; GraphMetadata::AllowedRegVecRef AllowedRegs;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool everConservativelyAllocatable; bool everConservativelyAllocatable;
#endif #endif
}; };
class RegAllocSolverImpl { class RegAllocSolverImpl {
private: private:
typedef MDMatrix<MatrixMetadata> RAMatrix; typedef MDMatrix<MatrixMetadata> RAMatrix;
public: public:
▲ Show 20 Lines • Show All 267 Lines • Show Last 20 Lines

include/llvm/CodeGen/ScheduleDAG.h

Show First 20 Lines • Show All 560 Lines • ▼ Show 20 Lines public:
const TargetInstrInfo *TII; // Target instruction information const TargetInstrInfo *TII; // Target instruction information
const TargetRegisterInfo *TRI; // Target processor register info const TargetRegisterInfo *TRI; // Target processor register info
MachineFunction &MF; // Machine function MachineFunction &MF; // Machine function
MachineRegisterInfo &MRI; // Virtual/real register map MachineRegisterInfo &MRI; // Virtual/real register map
std::vector<SUnit> SUnits; // The scheduling units. std::vector<SUnit> SUnits; // The scheduling units.
SUnit EntrySU; // Special node for the region entry. SUnit EntrySU; // Special node for the region entry.
SUnit ExitSU; // Special node for the region exit. SUnit ExitSU; // Special node for the region exit.
#ifdef NDEBUG #ifdef LLVM_NDEBUG
static const bool StressSched = false; static const bool StressSched = false;
#else #else
bool StressSched; bool StressSched;
#endif #endif
explicit ScheduleDAG(MachineFunction &mf); explicit ScheduleDAG(MachineFunction &mf);
virtual ~ScheduleDAG(); virtual ~ScheduleDAG();
Show All 22 Lines#endif
/// getDAGLabel - Return a label for the region of code covered by the DAG. /// getDAGLabel - Return a label for the region of code covered by the DAG.
virtual std::string getDAGName() const = 0; virtual std::string getDAGName() const = 0;
/// addCustomGraphFeatures - Add custom features for a visualization of /// addCustomGraphFeatures - Add custom features for a visualization of
/// the ScheduleDAG. /// the ScheduleDAG.
virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// VerifyScheduledDAG - Verify that all SUnits were scheduled and that /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
/// their state is consistent. Return the number of scheduled SUnits. /// their state is consistent. Return the number of scheduled SUnits.
unsigned VerifyScheduledDAG(bool isBottomUp); unsigned VerifyScheduledDAG(bool isBottomUp);
#endif #endif
private: private:
// Return the MCInstrDesc of this SDNode or NULL. // Return the MCInstrDesc of this SDNode or NULL.
const MCInstrDesc *getNodeDesc(const SDNode *Node) const; const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

include/llvm/CodeGen/ScheduleDAGInstrs.h

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Lines protected:
/// ///
/// Other adjustments may be made to the instruction if necessary. Return /// Other adjustments may be made to the instruction if necessary. Return
/// true if the operand has been deleted, false if not. /// true if the operand has been deleted, false if not.
bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO); bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO);
}; };
/// newSUnit - Creates a new SUnit and return a ptr to it. /// newSUnit - Creates a new SUnit and return a ptr to it.
inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) { inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0]; const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0];
#endif #endif
SUnits.emplace_back(MI, (unsigned)SUnits.size()); SUnits.emplace_back(MI, (unsigned)SUnits.size());
assert((Addr == nullptr || Addr == &SUnits[0]) && assert((Addr == nullptr || Addr == &SUnits[0]) &&
"SUnits std::vector reallocated on the fly!"); "SUnits std::vector reallocated on the fly!");
SUnits.back().OrigNode = &SUnits.back(); SUnits.back().OrigNode = &SUnits.back();
return &SUnits.back(); return &SUnits.back();
} }
Show All 11 Lines

include/llvm/CodeGen/ScoreboardHazardRecognizer.h

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines public:
void recede() { void recede() {
Head = (Head - 1) & (Depth-1); Head = (Head - 1) & (Depth-1);
} }
// Print the scoreboard. // Print the scoreboard.
void dump() const; void dump() const;
}; };
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Support for tracing ScoreboardHazardRecognizer as a component within // Support for tracing ScoreboardHazardRecognizer as a component within
// another module. Follows the current thread-unsafe model of tracing. // another module. Follows the current thread-unsafe model of tracing.
static const char *DebugType; static const char *DebugType;
#endif #endif
// Itinerary data for the target. // Itinerary data for the target.
const InstrItineraryData *ItinData; const InstrItineraryData *ItinData;
Show All 32 Lines

include/llvm/CodeGen/SelectionDAG.h

Show First 20 Lines • Show All 286 Lines • ▼ Show 20 Linespublic:
const TargetLowering &getTargetLoweringInfo() const { return *TLI; } const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return *TSI; } const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return *TSI; }
LLVMContext *getContext() const {return Context; } LLVMContext *getContext() const {return Context; }
/// Pop up a GraphViz/gv window with the DAG rendered using 'dot'. /// Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
void viewGraph(const std::string &Title); void viewGraph(const std::string &Title);
void viewGraph(); void viewGraph();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
std::map<const SDNode *, std::string> NodeGraphAttrs; std::map<const SDNode *, std::string> NodeGraphAttrs;
#endif #endif
/// Clear all previously defined node graph attributes. /// Clear all previously defined node graph attributes.
/// Intended to be used from a debugging tool (eg. gdb). /// Intended to be used from a debugging tool (eg. gdb).
void clearGraphAttrs(); void clearGraphAttrs();
/// Set graph attributes for a node. (eg. "color=red".) /// Set graph attributes for a node. (eg. "color=red".)
▲ Show 20 Lines • Show All 1,004 Lines • Show Last 20 Lines

include/llvm/CodeGen/TargetSchedule.h

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines unsigned getNumProcResourceKinds() const {
return SchedModel.getNumProcResourceKinds(); return SchedModel.getNumProcResourceKinds();
} }
/// \brief Get a processor resource by ID for convenience. /// \brief Get a processor resource by ID for convenience.
const MCProcResourceDesc *getProcResource(unsigned PIdx) const { const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
return SchedModel.getProcResource(PIdx); return SchedModel.getProcResource(PIdx);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const char *getResourceName(unsigned PIdx) const { const char *getResourceName(unsigned PIdx) const {
if (!PIdx) if (!PIdx)
return "MOps"; return "MOps";
return SchedModel.getProcResource(PIdx)->Name; return SchedModel.getProcResource(PIdx)->Name;
} }
#endif #endif
typedef const MCWriteProcResEntry *ProcResIter; typedef const MCWriteProcResEntry *ProcResIter;
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

include/llvm/IR/DebugInfoMetadata.h

Show First 20 Lines • Show All 839 Lines • ▼ Show 20 Linespublic:
/// \brief Replace operands. /// \brief Replace operands.
/// ///
/// If this \a isUniqued() and not \a isResolved(), on a uniquing collision /// If this \a isUniqued() and not \a isResolved(), on a uniquing collision
/// this will be RAUW'ed and deleted. Use a \a TrackingMDRef to keep track /// this will be RAUW'ed and deleted. Use a \a TrackingMDRef to keep track
/// of its movement if necessary. /// of its movement if necessary.
/// @{ /// @{
void replaceElements(DINodeArray Elements) { void replaceElements(DINodeArray Elements) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (DINode *Op : getElements()) for (DINode *Op : getElements())
assert(std::find(Elements->op_begin(), Elements->op_end(), Op) && assert(std::find(Elements->op_begin(), Elements->op_end(), Op) &&
"Lost a member during member list replacement"); "Lost a member during member list replacement");
#endif #endif
replaceOperandWith(4, Elements.get()); replaceOperandWith(4, Elements.get());
} }
void replaceVTableHolder(DITypeRef VTableHolder) { void replaceVTableHolder(DITypeRef VTableHolder) {
replaceOperandWith(5, VTableHolder); replaceOperandWith(5, VTableHolder);
▲ Show 20 Lines • Show All 1,392 Lines • Show Last 20 Lines

include/llvm/IR/Instructions.h

Show First 20 Lines • Show All 1,114 Lines • ▼ Show 20 Lines ICmpInst(
Instruction *InsertBefore, ///< Where to insert Instruction *InsertBefore, ///< Where to insert
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::ICmp, pred, LHS, RHS, NameStr, Instruction::ICmp, pred, LHS, RHS, NameStr,
InsertBefore) { InsertBefore) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
AssertOK(); AssertOK();
#endif #endif
} }
/// \brief Constructor with insert-at-end semantics. /// \brief Constructor with insert-at-end semantics.
ICmpInst( ICmpInst(
BasicBlock &InsertAtEnd, ///< Block to insert into. BasicBlock &InsertAtEnd, ///< Block to insert into.
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::ICmp, pred, LHS, RHS, NameStr, Instruction::ICmp, pred, LHS, RHS, NameStr,
&InsertAtEnd) { &InsertAtEnd) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
AssertOK(); AssertOK();
#endif #endif
} }
/// \brief Constructor with no-insertion semantics /// \brief Constructor with no-insertion semantics
ICmpInst( ICmpInst(
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::ICmp, pred, LHS, RHS, NameStr) { Instruction::ICmp, pred, LHS, RHS, NameStr) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
AssertOK(); AssertOK();
#endif #endif
} }
/// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc. /// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc.
/// @returns the predicate that would be the result if the operand were /// @returns the predicate that would be the result if the operand were
/// regarded as signed. /// regarded as signed.
/// \brief Return the signed version of the predicate /// \brief Return the signed version of the predicate
▲ Show 20 Lines • Show All 3,483 Lines • Show Last 20 Lines

include/llvm/IR/Statepoint.h

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linespublic:
InstructionTy *getGCResult() const { InstructionTy *getGCResult() const {
for (auto *U : getInstruction()->users()) for (auto *U : getInstruction()->users())
if (isGCResult(U)) if (isGCResult(U))
return cast<CallInst>(U); return cast<CallInst>(U);
return nullptr; return nullptr;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// Asserts if this statepoint is malformed. Common cases for failure /// Asserts if this statepoint is malformed. Common cases for failure
/// include incorrect length prefixes for variable length sections or /// include incorrect length prefixes for variable length sections or
/// illegal values for parameters. /// illegal values for parameters.
void verify() { void verify() {
assert(getNumCallArgs() >= 0 && assert(getNumCallArgs() >= 0 &&
"number of arguments to actually callee can't be negative"); "number of arguments to actually callee can't be negative");
// The internal asserts in the iterator accessors do the rest. // The internal asserts in the iterator accessors do the rest.
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

include/llvm/IR/ValueHandle.h

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
/// delete occurs. /// delete occurs.
/// ///
/// Note that an AssertingVH handle does *not* follow values across RAUW /// Note that an AssertingVH handle does *not* follow values across RAUW
/// operations. This means that RAUW's need to explicitly update the /// operations. This means that RAUW's need to explicitly update the
/// AssertingVH's as it moves. This is required because in non-assert mode this /// AssertingVH's as it moves. This is required because in non-assert mode this
/// class turns into a trivial wrapper around a pointer. /// class turns into a trivial wrapper around a pointer.
template <typename ValueTy> template <typename ValueTy>
class AssertingVH class AssertingVH
#ifndef NDEBUG #ifndef LLVM_NDEBUG
: public ValueHandleBase : public ValueHandleBase
#endif #endif
{ {
friend struct DenseMapInfo<AssertingVH<ValueTy> >; friend struct DenseMapInfo<AssertingVH<ValueTy> >;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Value *getRawValPtr() const { return ValueHandleBase::getValPtr(); } Value *getRawValPtr() const { return ValueHandleBase::getValPtr(); }
void setRawValPtr(Value *P) { ValueHandleBase::operator=(P); } void setRawValPtr(Value *P) { ValueHandleBase::operator=(P); }
#else #else
Value *ThePtr; Value *ThePtr;
Value *getRawValPtr() const { return ThePtr; } Value *getRawValPtr() const { return ThePtr; }
void setRawValPtr(Value *P) { ThePtr = P; } void setRawValPtr(Value *P) { ThePtr = P; }
#endif #endif
// Convert a ValueTy*, which may be const, to the raw Value*. // Convert a ValueTy*, which may be const, to the raw Value*.
static Value *GetAsValue(Value *V) { return V; } static Value *GetAsValue(Value *V) { return V; }
static Value *GetAsValue(const Value *V) { return const_cast<Value*>(V); } static Value *GetAsValue(const Value *V) { return const_cast<Value*>(V); }
ValueTy *getValPtr() const { return static_cast<ValueTy *>(getRawValPtr()); } ValueTy *getValPtr() const { return static_cast<ValueTy *>(getRawValPtr()); }
void setValPtr(ValueTy *P) { setRawValPtr(GetAsValue(P)); } void setValPtr(ValueTy *P) { setRawValPtr(GetAsValue(P)); }
public: public:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
AssertingVH() : ValueHandleBase(Assert) {} AssertingVH() : ValueHandleBase(Assert) {}
AssertingVH(ValueTy *P) : ValueHandleBase(Assert, GetAsValue(P)) {} AssertingVH(ValueTy *P) : ValueHandleBase(Assert, GetAsValue(P)) {}
AssertingVH(const AssertingVH &RHS) : ValueHandleBase(Assert, RHS) {} AssertingVH(const AssertingVH &RHS) : ValueHandleBase(Assert, RHS) {}
#else #else
AssertingVH() : ThePtr(nullptr) {} AssertingVH() : ThePtr(nullptr) {}
AssertingVH(ValueTy *P) : ThePtr(GetAsValue(P)) {} AssertingVH(ValueTy *P) : ThePtr(GetAsValue(P)) {}
#endif #endif
Show All 33 Linesstruct DenseMapInfo<AssertingVH<T> > {
static bool isEqual(const AssertingVH<T> &LHS, const AssertingVH<T> &RHS) { static bool isEqual(const AssertingVH<T> &LHS, const AssertingVH<T> &RHS) {
return DenseMapInfo<Value *>::isEqual(LHS.getRawValPtr(), return DenseMapInfo<Value *>::isEqual(LHS.getRawValPtr(),
RHS.getRawValPtr()); RHS.getRawValPtr());
} }
}; };
template <typename T> template <typename T>
struct isPodLike<AssertingVH<T> > { struct isPodLike<AssertingVH<T> > {
#ifdef NDEBUG #ifdef LLVM_NDEBUG
static const bool value = true; static const bool value = true;
#else #else
static const bool value = false; static const bool value = false;
#endif #endif
}; };
/// \brief Value handle that tracks a Value across RAUW. /// \brief Value handle that tracks a Value across RAUW.
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include/llvm/MC/MCSchedule.h

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#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
struct InstrItinerary; struct InstrItinerary;
/// Define a kind of processor resource that will be modeled by the scheduler. /// Define a kind of processor resource that will be modeled by the scheduler.
struct MCProcResourceDesc { struct MCProcResourceDesc {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const char *Name; const char *Name;
#endif #endif
unsigned NumUnits; // Number of resource of this kind unsigned NumUnits; // Number of resource of this kind
unsigned SuperIdx; // Index of the resources kind that contains this kind. unsigned SuperIdx; // Index of the resources kind that contains this kind.
// Number of resources that may be buffered. // Number of resources that may be buffered.
// //
// Buffered resources (BufferSize != 0) may be consumed at some indeterminate // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
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/// Summarize the scheduling resources required for an instruction of a /// Summarize the scheduling resources required for an instruction of a
/// particular scheduling class. /// particular scheduling class.
/// ///
/// Defined as an aggregate struct for creating tables with initializer lists. /// Defined as an aggregate struct for creating tables with initializer lists.
struct MCSchedClassDesc { struct MCSchedClassDesc {
static const unsigned short InvalidNumMicroOps = UINT16_MAX; static const unsigned short InvalidNumMicroOps = UINT16_MAX;
static const unsigned short VariantNumMicroOps = UINT16_MAX - 1; static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const char* Name; const char* Name;
#endif #endif
unsigned short NumMicroOps; unsigned short NumMicroOps;
bool BeginGroup; bool BeginGroup;
bool EndGroup; bool EndGroup;
unsigned WriteProcResIdx; // First index into WriteProcResTable. unsigned WriteProcResIdx; // First index into WriteProcResTable.
unsigned NumWriteProcResEntries; unsigned NumWriteProcResEntries;
unsigned WriteLatencyIdx; // First index into WriteLatencyTable. unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
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include/llvm/MC/MachineLocation.h

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linespublic:
} }
/// Make this location a register-indirect+offset location. /// Make this location a register-indirect+offset location.
void set(unsigned R, int O) { void set(unsigned R, int O) {
IsRegister = false; IsRegister = false;
Register = R; Register = R;
Offset = O; Offset = O;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void dump(); void dump();
#endif #endif
}; };
inline bool operator!=(const MachineLocation &LHS, const MachineLocation &RHS) { inline bool operator!=(const MachineLocation &LHS, const MachineLocation &RHS) {
return !(LHS == RHS); return !(LHS == RHS);
} }
} // End llvm namespace } // End llvm namespace
#endif #endif

include/llvm/Support/Compiler.h

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# define LLVM_ADDRESS_SANITIZER_BUILD 1 # define LLVM_ADDRESS_SANITIZER_BUILD 1
#else #else
# define LLVM_ADDRESS_SANITIZER_BUILD 0 # define LLVM_ADDRESS_SANITIZER_BUILD 0
#endif #endif
/// \brief Mark debug helper function definitions like dump() that should not be /// \brief Mark debug helper function definitions like dump() that should not be
/// stripped from debug builds. /// stripped from debug builds.
// FIXME: Move this to a private config.h as it's not usable in public headers. // FIXME: Move this to a private config.h as it's not usable in public headers.
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define LLVM_DUMP_METHOD LLVM_ATTRIBUTE_NOINLINE LLVM_ATTRIBUTE_USED #define LLVM_DUMP_METHOD LLVM_ATTRIBUTE_NOINLINE LLVM_ATTRIBUTE_USED
#else #else
#define LLVM_DUMP_METHOD LLVM_ATTRIBUTE_NOINLINE #define LLVM_DUMP_METHOD LLVM_ATTRIBUTE_NOINLINE
#endif #endif
/// \macro LLVM_THREAD_LOCAL /// \macro LLVM_THREAD_LOCAL
/// \brief A thread-local storage specifier which can be used with globals, /// \brief A thread-local storage specifier which can be used with globals,
/// extern globals, and static globals. /// extern globals, and static globals.
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include/llvm/Support/Debug.h

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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_SUPPORT_DEBUG_H #ifndef LLVM_SUPPORT_DEBUG_H
#define LLVM_SUPPORT_DEBUG_H #define LLVM_SUPPORT_DEBUG_H
namespace llvm { namespace llvm {
class raw_ostream; class raw_ostream;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// DebugFlag - This boolean is set to true if the '-debug' command line option /// DebugFlag - This boolean is set to true if the '-debug' command line option
/// is specified. This should probably not be referenced directly, instead, use /// is specified. This should probably not be referenced directly, instead, use
/// the DEBUG macro below. /// the DEBUG macro below.
/// ///
extern bool DebugFlag; extern bool DebugFlag;
/// isCurrentDebugType - Return true if the specified string is the debug type /// isCurrentDebugType - Return true if the specified string is the debug type
/// specified on the command line, or if none was specified on the command line /// specified on the command line, or if none was specified on the command line
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include/llvm/Support/ErrorHandling.h

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Linesnamespace llvm {
/// Use the llvm_unreachable macro (that adds location info), instead of /// Use the llvm_unreachable macro (that adds location info), instead of
/// calling this function directly. /// calling this function directly.
LLVM_ATTRIBUTE_NORETURN void LLVM_ATTRIBUTE_NORETURN void
llvm_unreachable_internal(const char *msg=nullptr, const char *file=nullptr, llvm_unreachable_internal(const char *msg=nullptr, const char *file=nullptr,
unsigned line=0); unsigned line=0);
} }
/// Marks that the current location is not supposed to be reachable. /// Marks that the current location is not supposed to be reachable.
/// In !NDEBUG builds, prints the message and location info to stderr. /// In !LLVM_NDEBUG builds, prints the message and location info to stderr.
/// In NDEBUG builds, becomes an optimizer hint that the current location /// In LLVM_NDEBUG builds, becomes an optimizer hint that the current location
/// is not supposed to be reachable. On compilers that don't support /// is not supposed to be reachable. On compilers that don't support
/// such hints, prints a reduced message instead. /// such hints, prints a reduced message instead.
/// ///
/// Use this instead of assert(0). It conveys intent more clearly and /// Use this instead of assert(0). It conveys intent more clearly and
/// allows compilers to omit some unnecessary code. /// allows compilers to omit some unnecessary code.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
#define llvm_unreachable(msg) \ #define llvm_unreachable(msg) \
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__) ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
#elif defined(LLVM_BUILTIN_UNREACHABLE) #elif defined(LLVM_BUILTIN_UNREACHABLE)
#define llvm_unreachable(msg) LLVM_BUILTIN_UNREACHABLE #define llvm_unreachable(msg) LLVM_BUILTIN_UNREACHABLE
#else #else
#define llvm_unreachable(msg) ::llvm::llvm_unreachable_internal() #define llvm_unreachable(msg) ::llvm::llvm_unreachable_internal()
#endif #endif
#endif #endif

include/llvm/Support/UnicodeCharRanges.h

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linespublic:
/// \brief Constructs a UnicodeCharSet instance from an array of /// \brief Constructs a UnicodeCharSet instance from an array of
/// UnicodeCharRanges. /// UnicodeCharRanges.
/// ///
/// Array pointed by \p Ranges should have the lifetime at least as long as /// Array pointed by \p Ranges should have the lifetime at least as long as
/// the UnicodeCharSet instance, and should not change. Array is validated by /// the UnicodeCharSet instance, and should not change. Array is validated by
/// the constructor, so it makes sense to create as few UnicodeCharSet /// the constructor, so it makes sense to create as few UnicodeCharSet
/// instances per each array of ranges, as possible. /// instances per each array of ranges, as possible.
#ifdef NDEBUG #ifdef LLVM_NDEBUG
LLVM_CONSTEXPR UnicodeCharSet(CharRanges Ranges) : Ranges(Ranges) {} LLVM_CONSTEXPR UnicodeCharSet(CharRanges Ranges) : Ranges(Ranges) {}
#else #else
UnicodeCharSet(CharRanges Ranges) : Ranges(Ranges) { UnicodeCharSet(CharRanges Ranges) : Ranges(Ranges) {
assert(rangesAreValid()); assert(rangesAreValid());
} }
#endif #endif
/// \brief Returns true if the character set contains the Unicode code point /// \brief Returns true if the character set contains the Unicode code point
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include/llvm/Support/Valgrind.h

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#ifndef LLVM_SUPPORT_VALGRIND_H #ifndef LLVM_SUPPORT_VALGRIND_H
#define LLVM_SUPPORT_VALGRIND_H #define LLVM_SUPPORT_VALGRIND_H
#include "llvm/Config/llvm-config.h" #include "llvm/Config/llvm-config.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include <stddef.h> #include <stddef.h>
#if LLVM_ENABLE_THREADS != 0 && !defined(NDEBUG) #if LLVM_ENABLE_THREADS != 0 && !defined(LLVM_NDEBUG)
// tsan (Thread Sanitizer) is a valgrind-based tool that detects these exact // tsan (Thread Sanitizer) is a valgrind-based tool that detects these exact
// functions by name. // functions by name.
extern "C" { extern "C" {
void AnnotateHappensAfter(const char *file, int line, const volatile void *cv); void AnnotateHappensAfter(const char *file, int line, const volatile void *cv);
void AnnotateHappensBefore(const char *file, int line, const volatile void *cv); void AnnotateHappensBefore(const char *file, int line, const volatile void *cv);
void AnnotateIgnoreWritesBegin(const char *file, int line); void AnnotateIgnoreWritesBegin(const char *file, int line);
void AnnotateIgnoreWritesEnd(const char *file, int line); void AnnotateIgnoreWritesEnd(const char *file, int line);
} }
#endif #endif
namespace llvm { namespace llvm {
namespace sys { namespace sys {
// True if Valgrind is controlling this process. // True if Valgrind is controlling this process.
bool RunningOnValgrind(); bool RunningOnValgrind();
// Discard valgrind's translation of code in the range [Addr .. Addr + Len). // Discard valgrind's translation of code in the range [Addr .. Addr + Len).
// Otherwise valgrind may continue to execute the old version of the code. // Otherwise valgrind may continue to execute the old version of the code.
void ValgrindDiscardTranslations(const void *Addr, size_t Len); void ValgrindDiscardTranslations(const void *Addr, size_t Len);
#if LLVM_ENABLE_THREADS != 0 && !defined(NDEBUG) #if LLVM_ENABLE_THREADS != 0 && !defined(LLVM_NDEBUG)
// Thread Sanitizer is a valgrind tool that finds races in code. // Thread Sanitizer is a valgrind tool that finds races in code.
// See http://code.google.com/p/data-race-test/wiki/DynamicAnnotations . // See http://code.google.com/p/data-race-test/wiki/DynamicAnnotations .
// This marker is used to define a happens-before arc. The race detector will // This marker is used to define a happens-before arc. The race detector will
// infer an arc from the begin to the end when they share the same pointer // infer an arc from the begin to the end when they share the same pointer
// argument. // argument.
#define TsanHappensBefore(cv) \ #define TsanHappensBefore(cv) \
AnnotateHappensBefore(__FILE__, __LINE__, cv) AnnotateHappensBefore(__FILE__, __LINE__, cv)
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lib/Analysis/AliasSetTracker.cpp

Show First 20 Lines • Show All 601 Lines • ▼ Show 20 Lines
void AliasSetTracker::print(raw_ostream &OS) const { void AliasSetTracker::print(raw_ostream &OS) const {
OS << "Alias Set Tracker: " << AliasSets.size() << " alias sets for " OS << "Alias Set Tracker: " << AliasSets.size() << " alias sets for "
<< PointerMap.size() << " pointer values.\n"; << PointerMap.size() << " pointer values.\n";
for (const_iterator I = begin(), E = end(); I != E; ++I) for (const_iterator I = begin(), E = end(); I != E; ++I)
I->print(OS); I->print(OS);
OS << "\n"; OS << "\n";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void AliasSet::dump() const { print(dbgs()); } void AliasSet::dump() const { print(dbgs()); }
void AliasSetTracker::dump() const { print(dbgs()); } void AliasSetTracker::dump() const { print(dbgs()); }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ASTCallbackVH Class Implementation // ASTCallbackVH Class Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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lib/Analysis/AssumptionCache.cpp

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesvoid AssumptionCache::registerAssumption(CallInst *CI) {
// If we haven't scanned the function yet, just drop this assumption. It will // If we haven't scanned the function yet, just drop this assumption. It will
// be found when we scan later. // be found when we scan later.
if (!Scanned) if (!Scanned)
return; return;
AssumeHandles.push_back(CI); AssumeHandles.push_back(CI);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(CI->getParent() && assert(CI->getParent() &&
"Cannot register @llvm.assume call not in a basic block"); "Cannot register @llvm.assume call not in a basic block");
assert(&F == CI->getParent()->getParent() && assert(&F == CI->getParent()->getParent() &&
"Cannot register @llvm.assume call not in this function"); "Cannot register @llvm.assume call not in this function");
// We expect the number of assumptions to be small, so in an asserts build // We expect the number of assumptions to be small, so in an asserts build
// check that we don't accumulate duplicates and that all assumptions point // check that we don't accumulate duplicates and that all assumptions point
// to the same function. // to the same function.
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 LinesAssumptionCache &AssumptionCacheTracker::getAssumptionCache(Function &F) {
// handle into our map, and return the newly populated cache. // handle into our map, and return the newly populated cache.
auto IP = AssumptionCaches.insert(std::make_pair( auto IP = AssumptionCaches.insert(std::make_pair(
FunctionCallbackVH(&F, this), llvm::make_unique<AssumptionCache>(F))); FunctionCallbackVH(&F, this), llvm::make_unique<AssumptionCache>(F)));
assert(IP.second && "Scanning function already in the map?"); assert(IP.second && "Scanning function already in the map?");
return *IP.first->second; return *IP.first->second;
} }
void AssumptionCacheTracker::verifyAnalysis() const { void AssumptionCacheTracker::verifyAnalysis() const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
SmallPtrSet<const CallInst *, 4> AssumptionSet; SmallPtrSet<const CallInst *, 4> AssumptionSet;
for (const auto &I : AssumptionCaches) { for (const auto &I : AssumptionCaches) {
for (auto &VH : I.second->assumptions()) for (auto &VH : I.second->assumptions())
if (VH) if (VH)
AssumptionSet.insert(cast<CallInst>(VH)); AssumptionSet.insert(cast<CallInst>(VH));
for (const BasicBlock &B : cast<Function>(*I.first)) for (const BasicBlock &B : cast<Function>(*I.first))
for (const Instruction &II : B) for (const Instruction &II : B)
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lib/Analysis/BlockFrequencyInfo.cpp

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#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/GraphWriter.h" #include "llvm/Support/GraphWriter.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "block-freq" #define DEBUG_TYPE "block-freq"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
enum GVDAGType { enum GVDAGType {
GVDT_None, GVDT_None,
GVDT_Fraction, GVDT_Fraction,
GVDT_Integer GVDT_Integer
}; };
static cl::opt<GVDAGType> static cl::opt<GVDAGType>
ViewBlockFreqPropagationDAG("view-block-freq-propagation-dags", cl::Hidden, ViewBlockFreqPropagationDAG("view-block-freq-propagation-dags", cl::Hidden,
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} }
void BlockFrequencyInfo::calculate(const Function &F, void BlockFrequencyInfo::calculate(const Function &F,
const BranchProbabilityInfo &BPI, const BranchProbabilityInfo &BPI,
const LoopInfo &LI) { const LoopInfo &LI) {
if (!BFI) if (!BFI)
BFI.reset(new ImplType); BFI.reset(new ImplType);
BFI->calculate(F, BPI, LI); BFI->calculate(F, BPI, LI);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (ViewBlockFreqPropagationDAG != GVDT_None) if (ViewBlockFreqPropagationDAG != GVDT_None)
view(); view();
#endif #endif
} }
BlockFrequency BlockFrequencyInfo::getBlockFreq(const BasicBlock *BB) const { BlockFrequency BlockFrequencyInfo::getBlockFreq(const BasicBlock *BB) const {
return BFI ? BFI->getBlockFreq(BB) : 0; return BFI ? BFI->getBlockFreq(BB) : 0;
} }
/// Pop up a ghostview window with the current block frequency propagation /// Pop up a ghostview window with the current block frequency propagation
/// rendered using dot. /// rendered using dot.
void BlockFrequencyInfo::view() const { void BlockFrequencyInfo::view() const {
// This code is only for debugging. // This code is only for debugging.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ViewGraph(const_cast<BlockFrequencyInfo *>(this), "BlockFrequencyDAGs"); ViewGraph(const_cast<BlockFrequencyInfo *>(this), "BlockFrequencyDAGs");
#else #else
errs() << "BlockFrequencyInfo::view is only available in debug builds on " errs() << "BlockFrequencyInfo::view is only available in debug builds on "
"systems with Graphviz or gv!\n"; "systems with Graphviz or gv!\n";
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
const Function *BlockFrequencyInfo::getFunction() const { const Function *BlockFrequencyInfo::getFunction() const {
return BFI ? BFI->getFunction() : nullptr; return BFI ? BFI->getFunction() : nullptr;
} }
raw_ostream &BlockFrequencyInfo:: raw_ostream &BlockFrequencyInfo::
printBlockFreq(raw_ostream &OS, const BlockFrequency Freq) const { printBlockFreq(raw_ostream &OS, const BlockFrequency Freq) const {
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lib/Analysis/BlockFrequencyInfoImpl.cpp

Show First 20 Lines • Show All 265 Lines • ▼ Show 20 Lines if (!Weight)
Weight = 1; Weight = 1;
auto isLoopHeader = [&OuterLoop](const BlockNode &Node) { auto isLoopHeader = [&OuterLoop](const BlockNode &Node) {
return OuterLoop && OuterLoop->isHeader(Node); return OuterLoop && OuterLoop->isHeader(Node);
}; };
BlockNode Resolved = Working[Succ.Index].getResolvedNode(); BlockNode Resolved = Working[Succ.Index].getResolvedNode();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
auto debugSuccessor = [&](const char *Type) { auto debugSuccessor = [&](const char *Type) {
dbgs() << " =>" dbgs() << " =>"
<< " [" << Type << "] weight = " << Weight; << " [" << Type << "] weight = " << Weight;
if (!isLoopHeader(Resolved)) if (!isLoopHeader(Resolved))
dbgs() << ", succ = " << getBlockName(Succ); dbgs() << ", succ = " << getBlockName(Succ);
if (Resolved != Succ) if (Resolved != Succ)
dbgs() << ", resolved = " << getBlockName(Resolved); dbgs() << ", resolved = " << getBlockName(Resolved);
dbgs() << "\n"; dbgs() << "\n";
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Linesvoid BlockFrequencyInfoImplBase::packageLoop(LoopData &Loop) {
for (const BlockNode &M : Loop.Nodes) { for (const BlockNode &M : Loop.Nodes) {
if (auto *Loop = Working[M.Index].getPackagedLoop()) if (auto *Loop = Working[M.Index].getPackagedLoop())
Loop->Exits.clear(); Loop->Exits.clear();
DEBUG(dbgs() << " - node: " << getBlockName(M.Index) << "\n"); DEBUG(dbgs() << " - node: " << getBlockName(M.Index) << "\n");
} }
Loop.IsPackaged = true; Loop.IsPackaged = true;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static void debugAssign(const BlockFrequencyInfoImplBase &BFI, static void debugAssign(const BlockFrequencyInfoImplBase &BFI,
const DitheringDistributer &D, const BlockNode &T, const DitheringDistributer &D, const BlockNode &T,
const BlockMass &M, const char *Desc) { const BlockMass &M, const char *Desc) {
dbgs() << " => assign " << M << " (" << D.RemMass << ")"; dbgs() << " => assign " << M << " (" << D.RemMass << ")";
if (Desc) if (Desc)
dbgs() << " [" << Desc << "]"; dbgs() << " [" << Desc << "]";
if (T.isValid()) if (T.isValid())
dbgs() << " to " << BFI.getBlockName(T); dbgs() << " to " << BFI.getBlockName(T);
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lib/Analysis/CFG.cpp

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
} }
/// GetSuccessorNumber - Search for the specified successor of basic block BB /// GetSuccessorNumber - Search for the specified successor of basic block BB
/// and return its position in the terminator instruction's list of /// and return its position in the terminator instruction's list of
/// successors. It is an error to call this with a block that is not a /// successors. It is an error to call this with a block that is not a
/// successor. /// successor.
unsigned llvm::GetSuccessorNumber(BasicBlock *BB, BasicBlock *Succ) { unsigned llvm::GetSuccessorNumber(BasicBlock *BB, BasicBlock *Succ) {
TerminatorInst *Term = BB->getTerminator(); TerminatorInst *Term = BB->getTerminator();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned e = Term->getNumSuccessors(); unsigned e = Term->getNumSuccessors();
#endif #endif
for (unsigned i = 0; ; ++i) { for (unsigned i = 0; ; ++i) {
assert(i != e && "Didn't find edge?"); assert(i != e && "Didn't find edge?");
if (Term->getSuccessor(i) == Succ) if (Term->getSuccessor(i) == Succ)
return i; return i;
} }
} }
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lib/Analysis/DependenceAnalysis.cpp

Show First 20 Lines • Show All 2,516 Lines • ▼ Show 20 Linesbool DependenceAnalysis::banerjeeMIVtest(const SCEV *Src,
// Compute bounds for all the * directions. // Compute bounds for all the * directions.
DEBUG(dbgs() << "\tBounds[*]\n"); DEBUG(dbgs() << "\tBounds[*]\n");
for (unsigned K = 1; K <= MaxLevels; ++K) { for (unsigned K = 1; K <= MaxLevels; ++K) {
Bound[K].Iterations = A[K].Iterations ? A[K].Iterations : B[K].Iterations; Bound[K].Iterations = A[K].Iterations ? A[K].Iterations : B[K].Iterations;
Bound[K].Direction = Dependence::DVEntry::ALL; Bound[K].Direction = Dependence::DVEntry::ALL;
Bound[K].DirSet = Dependence::DVEntry::NONE; Bound[K].DirSet = Dependence::DVEntry::NONE;
findBoundsALL(A, B, Bound, K); findBoundsALL(A, B, Bound, K);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(dbgs() << "\t " << K << '\t'); DEBUG(dbgs() << "\t " << K << '\t');
if (Bound[K].Lower[Dependence::DVEntry::ALL]) if (Bound[K].Lower[Dependence::DVEntry::ALL])
DEBUG(dbgs() << *Bound[K].Lower[Dependence::DVEntry::ALL] << '\t'); DEBUG(dbgs() << *Bound[K].Lower[Dependence::DVEntry::ALL] << '\t');
else else
DEBUG(dbgs() << "-inf\t"); DEBUG(dbgs() << "-inf\t");
if (Bound[K].Upper[Dependence::DVEntry::ALL]) if (Bound[K].Upper[Dependence::DVEntry::ALL])
DEBUG(dbgs() << *Bound[K].Upper[Dependence::DVEntry::ALL] << '\n'); DEBUG(dbgs() << *Bound[K].Upper[Dependence::DVEntry::ALL] << '\n');
else else
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesunsigned DependenceAnalysis::exploreDirections(unsigned Level,
unsigned &DepthExpanded, unsigned &DepthExpanded,
const SCEV *Delta) const { const SCEV *Delta) const {
if (Level > CommonLevels) { if (Level > CommonLevels) {
// record result // record result
DEBUG(dbgs() << "\t["); DEBUG(dbgs() << "\t[");
for (unsigned K = 1; K <= CommonLevels; ++K) { for (unsigned K = 1; K <= CommonLevels; ++K) {
if (Loops[K]) { if (Loops[K]) {
Bound[K].DirSet |= Bound[K].Direction; Bound[K].DirSet |= Bound[K].Direction;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
switch (Bound[K].Direction) { switch (Bound[K].Direction) {
case Dependence::DVEntry::LT: case Dependence::DVEntry::LT:
DEBUG(dbgs() << " <"); DEBUG(dbgs() << " <");
break; break;
case Dependence::DVEntry::EQ: case Dependence::DVEntry::EQ:
DEBUG(dbgs() << " ="); DEBUG(dbgs() << " =");
break; break;
case Dependence::DVEntry::GT: case Dependence::DVEntry::GT:
Show All 13 Lines#endif
} }
if (Loops[Level]) { if (Loops[Level]) {
if (Level > DepthExpanded) { if (Level > DepthExpanded) {
DepthExpanded = Level; DepthExpanded = Level;
// compute bounds for <, =, > at current level // compute bounds for <, =, > at current level
findBoundsLT(A, B, Bound, Level); findBoundsLT(A, B, Bound, Level);
findBoundsGT(A, B, Bound, Level); findBoundsGT(A, B, Bound, Level);
findBoundsEQ(A, B, Bound, Level); findBoundsEQ(A, B, Bound, Level);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(dbgs() << "\tBound for level = " << Level << '\n'); DEBUG(dbgs() << "\tBound for level = " << Level << '\n');
DEBUG(dbgs() << "\t <\t"); DEBUG(dbgs() << "\t <\t");
if (Bound[Level].Lower[Dependence::DVEntry::LT]) if (Bound[Level].Lower[Dependence::DVEntry::LT])
DEBUG(dbgs() << *Bound[Level].Lower[Dependence::DVEntry::LT] << '\t'); DEBUG(dbgs() << *Bound[Level].Lower[Dependence::DVEntry::LT] << '\t');
else else
DEBUG(dbgs() << "-inf\t"); DEBUG(dbgs() << "-inf\t");
if (Bound[Level].Upper[Dependence::DVEntry::LT]) if (Bound[Level].Upper[Dependence::DVEntry::LT])
DEBUG(dbgs() << *Bound[Level].Upper[Dependence::DVEntry::LT] << '\n'); DEBUG(dbgs() << *Bound[Level].Upper[Dependence::DVEntry::LT] << '\n');
▲ Show 20 Lines • Show All 270 Lines • ▼ Show 20 Lines while (const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(Subscript)) {
unsigned K = SrcFlag ? mapSrcLoop(L) : mapDstLoop(L); unsigned K = SrcFlag ? mapSrcLoop(L) : mapDstLoop(L);
CI[K].Coeff = AddRec->getStepRecurrence(*SE); CI[K].Coeff = AddRec->getStepRecurrence(*SE);
CI[K].PosPart = getPositivePart(CI[K].Coeff); CI[K].PosPart = getPositivePart(CI[K].Coeff);
CI[K].NegPart = getNegativePart(CI[K].Coeff); CI[K].NegPart = getNegativePart(CI[K].Coeff);
CI[K].Iterations = collectUpperBound(L, Subscript->getType()); CI[K].Iterations = collectUpperBound(L, Subscript->getType());
Subscript = AddRec->getStart(); Subscript = AddRec->getStart();
} }
Constant = Subscript; Constant = Subscript;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(dbgs() << "\tCoefficient Info\n"); DEBUG(dbgs() << "\tCoefficient Info\n");
for (unsigned K = 1; K <= MaxLevels; ++K) { for (unsigned K = 1; K <= MaxLevels; ++K) {
DEBUG(dbgs() << "\t " << K << "\t" << *CI[K].Coeff); DEBUG(dbgs() << "\t " << K << "\t" << *CI[K].Coeff);
DEBUG(dbgs() << "\tPos Part = "); DEBUG(dbgs() << "\tPos Part = ");
DEBUG(dbgs() << *CI[K].PosPart); DEBUG(dbgs() << *CI[K].PosPart);
DEBUG(dbgs() << "\tNeg Part = "); DEBUG(dbgs() << "\tNeg Part = ");
DEBUG(dbgs() << *CI[K].NegPart); DEBUG(dbgs() << *CI[K].NegPart);
DEBUG(dbgs() << "\tUpper Bound = "); DEBUG(dbgs() << "\tUpper Bound = ");
▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines for (int i = 0; i < size; ++i) {
// C one can access an array A[100][100]; as A[0][9999], *A[9999], etc. // C one can access an array A[100][100]; as A[0][9999], *A[9999], etc.
} }
return true; return true;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// For debugging purposes, dump a small bit vector to dbgs(). // For debugging purposes, dump a small bit vector to dbgs().
static void dumpSmallBitVector(SmallBitVector &BV) { static void dumpSmallBitVector(SmallBitVector &BV) {
dbgs() << "{"; dbgs() << "{";
for (int VI = BV.find_first(); VI >= 0; VI = BV.find_next(VI)) { for (int VI = BV.find_first(); VI >= 0; VI = BV.find_next(VI)) {
dbgs() << VI; dbgs() << VI;
if (BV.find_next(VI) >= 0) if (BV.find_next(VI) >= 0)
dbgs() << ' '; dbgs() << ' ';
} }
▲ Show 20 Lines • Show All 673 Lines • Show Last 20 Lines

lib/Analysis/DominanceFrontier.cpp

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesvoid DominanceFrontier::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll(); AU.setPreservesAll();
AU.addRequired<DominatorTreeWrapperPass>(); AU.addRequired<DominatorTreeWrapperPass>();
} }
void DominanceFrontier::print(raw_ostream &OS, const Module *) const { void DominanceFrontier::print(raw_ostream &OS, const Module *) const {
Base.print(OS); Base.print(OS);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void DominanceFrontier::dump() const { void DominanceFrontier::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif

lib/Analysis/IPA/CallGraph.cpp

Show All 33 Lines
CallGraph::~CallGraph() { CallGraph::~CallGraph() {
// CallsExternalNode is not in the function map, delete it explicitly. // CallsExternalNode is not in the function map, delete it explicitly.
if (CallsExternalNode) if (CallsExternalNode)
CallsExternalNode->allReferencesDropped(); CallsExternalNode->allReferencesDropped();
// Reset all node's use counts to zero before deleting them to prevent an // Reset all node's use counts to zero before deleting them to prevent an
// assertion from firing. // assertion from firing.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (auto &I : FunctionMap) for (auto &I : FunctionMap)
I.second->allReferencesDropped(); I.second->allReferencesDropped();
#endif #endif
} }
void CallGraph::addToCallGraph(Function *F) { void CallGraph::addToCallGraph(Function *F) {
CallGraphNode *Node = getOrInsertFunction(F); CallGraphNode *Node = getOrInsertFunction(F);
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines std::sort(Nodes.begin(), Nodes.end(),
return RHS->getFunction() != nullptr; return RHS->getFunction() != nullptr;
}); });
for (CallGraphNode *CN : Nodes) for (CallGraphNode *CN : Nodes)
CN->print(OS); CN->print(OS);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void CallGraph::dump() const { print(dbgs()); } void CallGraph::dump() const { print(dbgs()); }
#endif #endif
// removeFunctionFromModule - Unlink the function from this module, returning // removeFunctionFromModule - Unlink the function from this module, returning
// it. Because this removes the function from the module, the call graph node // it. Because this removes the function from the module, the call graph node
// is destroyed. This is only valid if the function does not call any other // is destroyed. This is only valid if the function does not call any other
// functions (ie, there are no edges in it's CGN). The easiest way to do this // functions (ie, there are no edges in it's CGN). The easiest way to do this
// is to dropAllReferences before calling this. // is to dropAllReferences before calling this.
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines for (const_iterator I = begin(), E = end(); I != E; ++I) {
if (Function *FI = I->second->getFunction()) if (Function *FI = I->second->getFunction())
OS << "function '" << FI->getName() <<"'\n"; OS << "function '" << FI->getName() <<"'\n";
else else
OS << "external node\n"; OS << "external node\n";
} }
OS << '\n'; OS << '\n';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void CallGraphNode::dump() const { print(dbgs()); } void CallGraphNode::dump() const { print(dbgs()); }
#endif #endif
/// removeCallEdgeFor - This method removes the edge in the node for the /// removeCallEdgeFor - This method removes the edge in the node for the
/// specified call site. Note that this method takes linear time, so it /// specified call site. Note that this method takes linear time, so it
/// should be used sparingly. /// should be used sparingly.
void CallGraphNode::removeCallEdgeFor(CallSite CS) { void CallGraphNode::removeCallEdgeFor(CallSite CS) {
for (CalledFunctionsVector::iterator I = CalledFunctions.begin(); ; ++I) { for (CalledFunctionsVector::iterator I = CalledFunctions.begin(); ; ++I) {
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines if (!G) {
OS << "No call graph has been built!\n"; OS << "No call graph has been built!\n";
return; return;
} }
// Just delegate. // Just delegate.
G->print(OS); G->print(OS);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void CallGraphWrapperPass::dump() const { print(dbgs(), nullptr); } void CallGraphWrapperPass::dump() const { print(dbgs(), nullptr); }
#endif #endif

lib/Analysis/IPA/CallGraphSCCPass.cpp

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines if (!PM) {
{ {
TimeRegion PassTimer(getPassTimer(CGSP)); TimeRegion PassTimer(getPassTimer(CGSP));
Changed = CGSP->runOnSCC(CurSCC); Changed = CGSP->runOnSCC(CurSCC);
} }
// After the CGSCCPass is done, when assertions are enabled, use // After the CGSCCPass is done, when assertions are enabled, use
// RefreshCallGraph to verify that the callgraph was correctly updated. // RefreshCallGraph to verify that the callgraph was correctly updated.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (Changed) if (Changed)
RefreshCallGraph(CurSCC, CG, true); RefreshCallGraph(CurSCC, CG, true);
#endif #endif
return Changed; return Changed;
} }
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesbool CGPassManager::RunAllPassesOnSCC(CallGraphSCC &CurSCC, CallGraph &CG,
for (unsigned PassNo = 0, e = getNumContainedPasses(); for (unsigned PassNo = 0, e = getNumContainedPasses();
PassNo != e; ++PassNo) { PassNo != e; ++PassNo) {
Pass *P = getContainedPass(PassNo); Pass *P = getContainedPass(PassNo);
// If we're in -debug-pass=Executions mode, construct the SCC node list, // If we're in -debug-pass=Executions mode, construct the SCC node list,
// otherwise avoid constructing this string as it is expensive. // otherwise avoid constructing this string as it is expensive.
if (isPassDebuggingExecutionsOrMore()) { if (isPassDebuggingExecutionsOrMore()) {
std::string Functions; std::string Functions;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
raw_string_ostream OS(Functions); raw_string_ostream OS(Functions);
for (CallGraphSCC::iterator I = CurSCC.begin(), E = CurSCC.end(); for (CallGraphSCC::iterator I = CurSCC.begin(), E = CurSCC.end();
I != E; ++I) { I != E; ++I) {
if (I != CurSCC.begin()) OS << ", "; if (I != CurSCC.begin()) OS << ", ";
(*I)->print(OS); (*I)->print(OS);
} }
OS.flush(); OS.flush();
#endif #endif
▲ Show 20 Lines • Show All 222 Lines • Show Last 20 Lines

lib/Analysis/IPA/InlineCost.cpp

Show First 20 Lines • Show All 1,292 Lines • ▼ Show 20 Linesbool CallAnalyzer::analyzeCall(CallSite CS) {
if (NumVectorInstructions <= NumInstructions / 10) if (NumVectorInstructions <= NumInstructions / 10)
Threshold -= FiftyPercentVectorBonus; Threshold -= FiftyPercentVectorBonus;
else if (NumVectorInstructions <= NumInstructions / 2) else if (NumVectorInstructions <= NumInstructions / 2)
Threshold -= (FiftyPercentVectorBonus - TenPercentVectorBonus); Threshold -= (FiftyPercentVectorBonus - TenPercentVectorBonus);
return Cost < Threshold; return Cost < Threshold;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// \brief Dump stats about this call's analysis. /// \brief Dump stats about this call's analysis.
void CallAnalyzer::dump() { void CallAnalyzer::dump() {
#define DEBUG_PRINT_STAT(x) dbgs() << " " #x ": " << x << "\n" #define DEBUG_PRINT_STAT(x) dbgs() << " " #x ": " << x << "\n"
DEBUG_PRINT_STAT(NumConstantArgs); DEBUG_PRINT_STAT(NumConstantArgs);
DEBUG_PRINT_STAT(NumConstantOffsetPtrArgs); DEBUG_PRINT_STAT(NumConstantOffsetPtrArgs);
DEBUG_PRINT_STAT(NumAllocaArgs); DEBUG_PRINT_STAT(NumAllocaArgs);
DEBUG_PRINT_STAT(NumConstantPtrCmps); DEBUG_PRINT_STAT(NumConstantPtrCmps);
DEBUG_PRINT_STAT(NumConstantPtrDiffs); DEBUG_PRINT_STAT(NumConstantPtrDiffs);
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lib/Analysis/IVUsers.cpp

Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines for (ilist<IVStrideUse>::const_iterator UI = IVUses.begin(),
if (UI->getUser()) if (UI->getUser())
UI->getUser()->print(OS); UI->getUser()->print(OS);
else else
OS << "Printing <null> User"; OS << "Printing <null> User";
OS << '\n'; OS << '\n';
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void IVUsers::dump() const { void IVUsers::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
void IVUsers::releaseMemory() { void IVUsers::releaseMemory() {
Processed.clear(); Processed.clear();
IVUses.clear(); IVUses.clear();
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lib/Analysis/LazyCallGraph.cpp

Show First 20 Lines • Show All 503 Lines • ▼ Show 20 Lines for (Node *N : Nodes) {
for (Node &ChildN : *N) { for (Node &ChildN : *N) {
SCC &ChildSCC = *G->SCCMap.lookup(&ChildN); SCC &ChildSCC = *G->SCCMap.lookup(&ChildN);
if (&ChildSCC == this) if (&ChildSCC == this)
continue; continue;
ChildSCC.ParentSCCs.insert(this); ChildSCC.ParentSCCs.insert(this);
IsLeafSCC = false; IsLeafSCC = false;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (!ResultSCCs.empty()) if (!ResultSCCs.empty())
assert(!IsLeafSCC && "This SCC cannot be a leaf as we have split out new " assert(!IsLeafSCC && "This SCC cannot be a leaf as we have split out new "
"SCCs by removing this edge."); "SCCs by removing this edge.");
if (!std::any_of(G->LeafSCCs.begin(), G->LeafSCCs.end(), if (!std::any_of(G->LeafSCCs.begin(), G->LeafSCCs.end(),
[&](SCC *C) { return C == this; })) [&](SCC *C) { return C == this; }))
assert(!IsLeafSCC && "This SCC cannot be a leaf as it already had child " assert(!IsLeafSCC && "This SCC cannot be a leaf as it already had child "
"SCCs before we removed this edge."); "SCCs before we removed this edge.");
#endif #endif
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

lib/Analysis/LoopAccessAnalysis.cpp

Show First 20 Lines • Show All 1,773 Lines • ▼ Show 20 Lines OS.indent(Depth) << "Store to invariant address was "
<< (StoreToLoopInvariantAddress ? "" : "not ") << (StoreToLoopInvariantAddress ? "" : "not ")
<< "found in loop.\n"; << "found in loop.\n";
} }
const LoopAccessInfo & const LoopAccessInfo &
LoopAccessAnalysis::getInfo(Loop *L, const ValueToValueMap &Strides) { LoopAccessAnalysis::getInfo(Loop *L, const ValueToValueMap &Strides) {
auto &LAI = LoopAccessInfoMap[L]; auto &LAI = LoopAccessInfoMap[L];
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert((!LAI || LAI->NumSymbolicStrides == Strides.size()) && assert((!LAI || LAI->NumSymbolicStrides == Strides.size()) &&
"Symbolic strides changed for loop"); "Symbolic strides changed for loop");
#endif #endif
if (!LAI) { if (!LAI) {
const DataLayout &DL = L->getHeader()->getModule()->getDataLayout(); const DataLayout &DL = L->getHeader()->getModule()->getDataLayout();
LAI = llvm::make_unique<LoopAccessInfo>(L, SE, DL, TLI, AA, DT, LI, LAI = llvm::make_unique<LoopAccessInfo>(L, SE, DL, TLI, AA, DT, LI,
Strides); Strides);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
LAI->NumSymbolicStrides = Strides.size(); LAI->NumSymbolicStrides = Strides.size();
#endif #endif
} }
return *LAI.get(); return *LAI.get();
} }
void LoopAccessAnalysis::print(raw_ostream &OS, const Module *M) const { void LoopAccessAnalysis::print(raw_ostream &OS, const Module *M) const {
LoopAccessAnalysis &LAA = *const_cast<LoopAccessAnalysis *>(this); LoopAccessAnalysis &LAA = *const_cast<LoopAccessAnalysis *>(this);
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

lib/Analysis/LoopInfo.cpp

Show First 20 Lines • Show All 394 Lines • ▼ Show 20 Lines
BasicBlock *Loop::getUniqueExitBlock() const { BasicBlock *Loop::getUniqueExitBlock() const {
SmallVector<BasicBlock *, 8> UniqueExitBlocks; SmallVector<BasicBlock *, 8> UniqueExitBlocks;
getUniqueExitBlocks(UniqueExitBlocks); getUniqueExitBlocks(UniqueExitBlocks);
if (UniqueExitBlocks.size() == 1) if (UniqueExitBlocks.size() == 1)
return UniqueExitBlocks[0]; return UniqueExitBlocks[0];
return nullptr; return nullptr;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void Loop::dump() const { void Loop::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// UnloopUpdater implementation // UnloopUpdater implementation
// //
▲ Show 20 Lines • Show All 328 Lines • Show Last 20 Lines

lib/Analysis/MemoryDependenceAnalysis.cpp

Show First 20 Lines • Show All 708 Lines • ▼ Show 20 LinesMemDepResult MemoryDependenceAnalysis::getDependency(Instruction *QueryInst) {
// Remember the result! // Remember the result!
if (Instruction *I = LocalCache.getInst()) if (Instruction *I = LocalCache.getInst())
ReverseLocalDeps[I].insert(QueryInst); ReverseLocalDeps[I].insert(QueryInst);
return LocalCache; return LocalCache;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// AssertSorted - This method is used when -debug is specified to verify that /// AssertSorted - This method is used when -debug is specified to verify that
/// cache arrays are properly kept sorted. /// cache arrays are properly kept sorted.
static void AssertSorted(MemoryDependenceAnalysis::NonLocalDepInfo &Cache, static void AssertSorted(MemoryDependenceAnalysis::NonLocalDepInfo &Cache,
int Count = -1) { int Count = -1) {
if (Count == -1) Count = Cache.size(); if (Count == -1) Count = Cache.size();
if (Count == 0) return; if (Count == 0) return;
for (unsigned i = 1; i != unsigned(Count); ++i) for (unsigned i = 1; i != unsigned(Count); ++i)
▲ Show 20 Lines • Show All 900 Lines • ▼ Show 20 Linesvoid MemoryDependenceAnalysis::removeInstruction(Instruction *RemInst) {
assert(!NonLocalDeps.count(RemInst) && "RemInst got reinserted?"); assert(!NonLocalDeps.count(RemInst) && "RemInst got reinserted?");
DEBUG(verifyRemoved(RemInst)); DEBUG(verifyRemoved(RemInst));
} }
/// verifyRemoved - Verify that the specified instruction does not occur /// verifyRemoved - Verify that the specified instruction does not occur
/// in our internal data structures. This function verifies by asserting in /// in our internal data structures. This function verifies by asserting in
/// debug builds. /// debug builds.
void MemoryDependenceAnalysis::verifyRemoved(Instruction *D) const { void MemoryDependenceAnalysis::verifyRemoved(Instruction *D) const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (LocalDepMapType::const_iterator I = LocalDeps.begin(), for (LocalDepMapType::const_iterator I = LocalDeps.begin(),
E = LocalDeps.end(); I != E; ++I) { E = LocalDeps.end(); I != E; ++I) {
assert(I->first != D && "Inst occurs in data structures"); assert(I->first != D && "Inst occurs in data structures");
assert(I->second.getInst() != D && assert(I->second.getInst() != D &&
"Inst occurs in data structures"); "Inst occurs in data structures");
} }
for (CachedNonLocalPointerInfo::const_iterator I =NonLocalPointerDeps.begin(), for (CachedNonLocalPointerInfo::const_iterator I =NonLocalPointerDeps.begin(),
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

lib/Analysis/PHITransAddr.cpp

Show All 35 Lines if (Inst->getOpcode() == Instruction::Add &&
return true; return true;
// cerr << "MEMDEP: Could not PHI translate: " << *Pointer; // cerr << "MEMDEP: Could not PHI translate: " << *Pointer;
// if (isa<BitCastInst>(PtrInst) || isa<GetElementPtrInst>(PtrInst)) // if (isa<BitCastInst>(PtrInst) || isa<GetElementPtrInst>(PtrInst))
// cerr << "OP:\t\t\t\t" << *PtrInst->getOperand(0); // cerr << "OP:\t\t\t\t" << *PtrInst->getOperand(0);
return false; return false;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void PHITransAddr::dump() const { void PHITransAddr::dump() const {
if (!Addr) { if (!Addr) {
dbgs() << "PHITransAddr: null\n"; dbgs() << "PHITransAddr: null\n";
return; return;
} }
dbgs() << "PHITransAddr: " << *Addr << "\n"; dbgs() << "PHITransAddr: " << *Addr << "\n";
for (unsigned i = 0, e = InstInputs.size(); i != e; ++i) for (unsigned i = 0, e = InstInputs.size(); i != e; ++i)
dbgs() << " Input #" << i << " is " << *InstInputs[i] << "\n"; dbgs() << " Input #" << i << " is " << *InstInputs[i] << "\n";
▲ Show 20 Lines • Show All 389 Lines • Show Last 20 Lines

lib/Analysis/RegionInfo.cpp

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Linesvoid RegionInfoPass::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<PostDominatorTree>(); AU.addRequired<PostDominatorTree>();
AU.addRequired<DominanceFrontier>(); AU.addRequired<DominanceFrontier>();
} }
void RegionInfoPass::print(raw_ostream &OS, const Module *) const { void RegionInfoPass::print(raw_ostream &OS, const Module *) const {
RI.print(OS); RI.print(OS);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void RegionInfoPass::dump() const { void RegionInfoPass::dump() const {
RI.dump(); RI.dump();
} }
#endif #endif
char RegionInfoPass::ID = 0; char RegionInfoPass::ID = 0;
INITIALIZE_PASS_BEGIN(RegionInfoPass, "regions", INITIALIZE_PASS_BEGIN(RegionInfoPass, "regions",
Show All 17 Lines

lib/Analysis/ScalarEvolution.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SCEV class definitions // SCEV class definitions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Implementation of the SCEV class. // Implementation of the SCEV class.
// //
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void SCEV::dump() const { void SCEV::dump() const {
print(dbgs()); print(dbgs());
dbgs() << '\n'; dbgs() << '\n';
} }
#endif #endif
void SCEV::print(raw_ostream &OS) const { void SCEV::print(raw_ostream &OS) const {
switch (static_cast<SCEVTypes>(getSCEVType())) { switch (static_cast<SCEVTypes>(getSCEVType())) {
▲ Show 20 Lines • Show All 1,824 Lines • ▼ Show 20 Lines
/// getAddExpr - Get a canonical add expression, or something simpler if /// getAddExpr - Get a canonical add expression, or something simpler if
/// possible. /// possible.
const SCEV *ScalarEvolution::getAddExpr(SmallVectorImpl<const SCEV *> &Ops, const SCEV *ScalarEvolution::getAddExpr(SmallVectorImpl<const SCEV *> &Ops,
SCEV::NoWrapFlags Flags) { SCEV::NoWrapFlags Flags) {
assert(!(Flags & ~(SCEV::FlagNUW | SCEV::FlagNSW)) && assert(!(Flags & ~(SCEV::FlagNUW | SCEV::FlagNSW)) &&
"only nuw or nsw allowed"); "only nuw or nsw allowed");
assert(!Ops.empty() && "Cannot get empty add!"); assert(!Ops.empty() && "Cannot get empty add!");
if (Ops.size() == 1) return Ops[0]; if (Ops.size() == 1) return Ops[0];
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Type *ETy = getEffectiveSCEVType(Ops[0]->getType()); Type *ETy = getEffectiveSCEVType(Ops[0]->getType());
for (unsigned i = 1, e = Ops.size(); i != e; ++i) for (unsigned i = 1, e = Ops.size(); i != e; ++i)
assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy && assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy &&
"SCEVAddExpr operand types don't match!"); "SCEVAddExpr operand types don't match!");
#endif #endif
Flags = StrengthenNoWrapFlags(this, scAddExpr, Ops, Flags); Flags = StrengthenNoWrapFlags(this, scAddExpr, Ops, Flags);
▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines
/// getMulExpr - Get a canonical multiply expression, or something simpler if /// getMulExpr - Get a canonical multiply expression, or something simpler if
/// possible. /// possible.
const SCEV *ScalarEvolution::getMulExpr(SmallVectorImpl<const SCEV *> &Ops, const SCEV *ScalarEvolution::getMulExpr(SmallVectorImpl<const SCEV *> &Ops,
SCEV::NoWrapFlags Flags) { SCEV::NoWrapFlags Flags) {
assert(Flags == maskFlags(Flags, SCEV::FlagNUW | SCEV::FlagNSW) && assert(Flags == maskFlags(Flags, SCEV::FlagNUW | SCEV::FlagNSW) &&
"only nuw or nsw allowed"); "only nuw or nsw allowed");
assert(!Ops.empty() && "Cannot get empty mul!"); assert(!Ops.empty() && "Cannot get empty mul!");
if (Ops.size() == 1) return Ops[0]; if (Ops.size() == 1) return Ops[0];
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Type *ETy = getEffectiveSCEVType(Ops[0]->getType()); Type *ETy = getEffectiveSCEVType(Ops[0]->getType());
for (unsigned i = 1, e = Ops.size(); i != e; ++i) for (unsigned i = 1, e = Ops.size(); i != e; ++i)
assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy && assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy &&
"SCEVMulExpr operand types don't match!"); "SCEVMulExpr operand types don't match!");
#endif #endif
Flags = StrengthenNoWrapFlags(this, scMulExpr, Ops, Flags); Flags = StrengthenNoWrapFlags(this, scMulExpr, Ops, Flags);
▲ Show 20 Lines • Show All 435 Lines • ▼ Show 20 Lines
} }
/// getAddRecExpr - Get an add recurrence expression for the specified loop. /// getAddRecExpr - Get an add recurrence expression for the specified loop.
/// Simplify the expression as much as possible. /// Simplify the expression as much as possible.
const SCEV * const SCEV *
ScalarEvolution::getAddRecExpr(SmallVectorImpl<const SCEV *> &Operands, ScalarEvolution::getAddRecExpr(SmallVectorImpl<const SCEV *> &Operands,
const Loop *L, SCEV::NoWrapFlags Flags) { const Loop *L, SCEV::NoWrapFlags Flags) {
if (Operands.size() == 1) return Operands[0]; if (Operands.size() == 1) return Operands[0];
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Type *ETy = getEffectiveSCEVType(Operands[0]->getType()); Type *ETy = getEffectiveSCEVType(Operands[0]->getType());
for (unsigned i = 1, e = Operands.size(); i != e; ++i) for (unsigned i = 1, e = Operands.size(); i != e; ++i)
assert(getEffectiveSCEVType(Operands[i]->getType()) == ETy && assert(getEffectiveSCEVType(Operands[i]->getType()) == ETy &&
"SCEVAddRecExpr operand types don't match!"); "SCEVAddRecExpr operand types don't match!");
for (unsigned i = 0, e = Operands.size(); i != e; ++i) for (unsigned i = 0, e = Operands.size(); i != e; ++i)
assert(isLoopInvariant(Operands[i], L) && assert(isLoopInvariant(Operands[i], L) &&
"SCEVAddRecExpr operand is not loop-invariant!"); "SCEVAddRecExpr operand is not loop-invariant!");
#endif #endif
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Linesconst SCEV *ScalarEvolution::getSMaxExpr(const SCEV *LHS,
Ops.push_back(RHS); Ops.push_back(RHS);
return getSMaxExpr(Ops); return getSMaxExpr(Ops);
} }
const SCEV * const SCEV *
ScalarEvolution::getSMaxExpr(SmallVectorImpl<const SCEV *> &Ops) { ScalarEvolution::getSMaxExpr(SmallVectorImpl<const SCEV *> &Ops) {
assert(!Ops.empty() && "Cannot get empty smax!"); assert(!Ops.empty() && "Cannot get empty smax!");
if (Ops.size() == 1) return Ops[0]; if (Ops.size() == 1) return Ops[0];
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Type *ETy = getEffectiveSCEVType(Ops[0]->getType()); Type *ETy = getEffectiveSCEVType(Ops[0]->getType());
for (unsigned i = 1, e = Ops.size(); i != e; ++i) for (unsigned i = 1, e = Ops.size(); i != e; ++i)
assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy && assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy &&
"SCEVSMaxExpr operand types don't match!"); "SCEVSMaxExpr operand types don't match!");
#endif #endif
// Sort by complexity, this groups all similar expression types together. // Sort by complexity, this groups all similar expression types together.
GroupByComplexity(Ops, LI); GroupByComplexity(Ops, LI);
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Linesconst SCEV *ScalarEvolution::getUMaxExpr(const SCEV *LHS,
Ops.push_back(RHS); Ops.push_back(RHS);
return getUMaxExpr(Ops); return getUMaxExpr(Ops);
} }
const SCEV * const SCEV *
ScalarEvolution::getUMaxExpr(SmallVectorImpl<const SCEV *> &Ops) { ScalarEvolution::getUMaxExpr(SmallVectorImpl<const SCEV *> &Ops) {
assert(!Ops.empty() && "Cannot get empty umax!"); assert(!Ops.empty() && "Cannot get empty umax!");
if (Ops.size() == 1) return Ops[0]; if (Ops.size() == 1) return Ops[0];
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Type *ETy = getEffectiveSCEVType(Ops[0]->getType()); Type *ETy = getEffectiveSCEVType(Ops[0]->getType());
for (unsigned i = 1, e = Ops.size(); i != e; ++i) for (unsigned i = 1, e = Ops.size(); i != e; ++i)
assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy && assert(getEffectiveSCEVType(Ops[i]->getType()) == ETy &&
"SCEVUMaxExpr operand types don't match!"); "SCEVUMaxExpr operand types don't match!");
#endif #endif
// Sort by complexity, this groups all similar expression types together. // Sort by complexity, this groups all similar expression types together.
GroupByComplexity(Ops, LI); GroupByComplexity(Ops, LI);
▲ Show 20 Lines • Show All 3,592 Lines • ▼ Show 20 Linesbool ScalarEvolution::isKnownPredicate(ICmpInst::Predicate Pred,
return isKnownPredicateWithRanges(Pred, LHS, RHS); return isKnownPredicateWithRanges(Pred, LHS, RHS);
} }
bool ScalarEvolution::isMonotonicPredicate(const SCEVAddRecExpr *LHS, bool ScalarEvolution::isMonotonicPredicate(const SCEVAddRecExpr *LHS,
ICmpInst::Predicate Pred, ICmpInst::Predicate Pred,
bool &Increasing) { bool &Increasing) {
bool Result = isMonotonicPredicateImpl(LHS, Pred, Increasing); bool Result = isMonotonicPredicateImpl(LHS, Pred, Increasing);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify an invariant: inverting the predicate should turn a monotonically // Verify an invariant: inverting the predicate should turn a monotonically
// increasing change to a monotonically decreasing one, and vice versa. // increasing change to a monotonically decreasing one, and vice versa.
bool IncreasingSwapped; bool IncreasingSwapped;
bool ResultSwapped = isMonotonicPredicateImpl( bool ResultSwapped = isMonotonicPredicateImpl(
LHS, ICmpInst::getSwappedPredicate(Pred), IncreasingSwapped); LHS, ICmpInst::getSwappedPredicate(Pred), IncreasingSwapped);
assert(Result == ResultSwapped && "should be able to analyze both!"); assert(Result == ResultSwapped && "should be able to analyze both!");
if (ResultSwapped) if (ResultSwapped)
▲ Show 20 Lines • Show All 2,029 Lines • Show Last 20 Lines

lib/Analysis/TargetLibraryInfo.cpp

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Linesstatic bool hasSinCosPiStret(const Triple &T) {
return true; return true;
} }
/// initialize - Initialize the set of available library functions based on the /// initialize - Initialize the set of available library functions based on the
/// specified target triple. This should be carefully written so that a missing /// specified target triple. This should be carefully written so that a missing
/// target triple gets a sane set of defaults. /// target triple gets a sane set of defaults.
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T,
const char *const *StandardNames) { const char *const *StandardNames) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify that the StandardNames array is in alphabetical order. // Verify that the StandardNames array is in alphabetical order.
for (unsigned F = 1; F < LibFunc::NumLibFuncs; ++F) { for (unsigned F = 1; F < LibFunc::NumLibFuncs; ++F) {
if (strcmp(StandardNames[F-1], StandardNames[F]) >= 0) if (strcmp(StandardNames[F-1], StandardNames[F]) >= 0)
llvm_unreachable("TargetLibraryInfoImpl function names must be sorted"); llvm_unreachable("TargetLibraryInfoImpl function names must be sorted");
} }
#endif // !NDEBUG #endif // !LLVM_NDEBUG
// There are no library implementations of mempcy and memset for AMD gpus and // There are no library implementations of mempcy and memset for AMD gpus and
// these can be difficult to lower in the backend. // these can be difficult to lower in the backend.
if (T.getArch() == Triple::r600 || if (T.getArch() == Triple::r600 ||
T.getArch() == Triple::amdgcn) { T.getArch() == Triple::amdgcn) {
TLI.setUnavailable(LibFunc::memcpy); TLI.setUnavailable(LibFunc::memcpy);
TLI.setUnavailable(LibFunc::memset); TLI.setUnavailable(LibFunc::memset);
TLI.setUnavailable(LibFunc::memset_pattern16); TLI.setUnavailable(LibFunc::memset_pattern16);
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lib/Analysis/Trace.cpp

Show All 36 Linesvoid Trace::print(raw_ostream &O) const {
for (const_iterator i = begin(), e = end(); i != e; ++i) { for (const_iterator i = begin(), e = end(); i != e; ++i) {
O << "; "; O << "; ";
(*i)->printAsOperand(O, true, getModule()); (*i)->printAsOperand(O, true, getModule());
O << "\n"; O << "\n";
} }
O << "; Trace parent function: \n" << *F; O << "; Trace parent function: \n" << *F;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dump - Debugger convenience method; writes trace to standard error /// dump - Debugger convenience method; writes trace to standard error
/// output stream. /// output stream.
/// ///
void Trace::dump() const { void Trace::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif

lib/AsmParser/LLParser.cpp

Show First 20 Lines • Show All 3,712 Lines • ▼ Show 20 Lines
#undef VISIT_MD_FIELDS #undef VISIT_MD_FIELDS
Result = GET_OR_DISTINCT(DINamespace, Result = GET_OR_DISTINCT(DINamespace,
(Context, scope.Val, file.Val, name.Val, line.Val)); (Context, scope.Val, file.Val, name.Val, line.Val));
return false; return false;
} }
/// ParseDIModule: /// ParseDIModule:
/// ::= !DIModule(scope: !0, name: "SomeModule", configMacros: "-DNDEBUG", /// ::= !DIModule(scope: !0, name: "SomeModule", configMacros: "-DLLVM_NDEBUG",
/// includePath: "/usr/include", isysroot: "/") /// includePath: "/usr/include", isysroot: "/")
bool LLParser::ParseDIModule(MDNode *&Result, bool IsDistinct) { bool LLParser::ParseDIModule(MDNode *&Result, bool IsDistinct) {
#define VISIT_MD_FIELDS(OPTIONAL, REQUIRED) \ #define VISIT_MD_FIELDS(OPTIONAL, REQUIRED) \
REQUIRED(scope, MDField, ); \ REQUIRED(scope, MDField, ); \
REQUIRED(name, MDStringField, ); \ REQUIRED(name, MDStringField, ); \
OPTIONAL(configMacros, MDStringField, ); \ OPTIONAL(configMacros, MDStringField, ); \
OPTIONAL(includePath, MDStringField, ); \ OPTIONAL(includePath, MDStringField, ); \
OPTIONAL(isysroot, MDStringField, ); OPTIONAL(isysroot, MDStringField, );
▲ Show 20 Lines • Show All 2,328 Lines • Show Last 20 Lines

lib/Bitcode/Writer/BitcodeWriter.cpp

Show First 20 Lines • Show All 1,611 Lines • ▼ Show 20 Lines if (C->isNullValue()) {
break; break;
} }
} else if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) { } else if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) {
Code = bitc::CST_CODE_BLOCKADDRESS; Code = bitc::CST_CODE_BLOCKADDRESS;
Record.push_back(VE.getTypeID(BA->getFunction()->getType())); Record.push_back(VE.getTypeID(BA->getFunction()->getType()));
Record.push_back(VE.getValueID(BA->getFunction())); Record.push_back(VE.getValueID(BA->getFunction()));
Record.push_back(VE.getGlobalBasicBlockID(BA->getBasicBlock())); Record.push_back(VE.getGlobalBasicBlockID(BA->getBasicBlock()));
} else { } else {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
C->dump(); C->dump();
#endif #endif
llvm_unreachable("Unknown constant!"); llvm_unreachable("Unknown constant!");
} }
Stream.EmitRecord(Code, Record, AbbrevToUse); Stream.EmitRecord(Code, Record, AbbrevToUse);
Record.clear(); Record.clear();
} }
▲ Show 20 Lines • Show All 942 Lines • Show Last 20 Lines

lib/CodeGen/AggressiveAntiDepBreaker.cpp

Show First 20 Lines • Show All 577 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
bool IsSub = TRI->isSubRegister(SuperReg, Reg); bool IsSub = TRI->isSubRegister(SuperReg, Reg);
// FIXME: remove this once PR18663 has been properly fixed. For now, // FIXME: remove this once PR18663 has been properly fixed. For now,
// return a conservative answer: // return a conservative answer:
// assert(IsSub && "Expecting group subregister"); // assert(IsSub && "Expecting group subregister");
if (!IsSub) if (!IsSub)
return false; return false;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
if (DebugDiv > 0) { if (DebugDiv > 0) {
static int renamecnt = 0; static int renamecnt = 0;
if (renamecnt++ % DebugDiv != DebugMod) if (renamecnt++ % DebugDiv != DebugMod)
return false; return false;
dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
" for debug ***\n"; " for debug ***\n";
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
(CriticalPathSU->getDepth() + CriticalPathSU->Latency))) { (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
CriticalPathSU = SU; CriticalPathSU = SU;
} }
} }
CriticalPathMI = CriticalPathSU->getInstr(); CriticalPathMI = CriticalPathSU->getInstr();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n"); DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
DEBUG(dbgs() << "Available regs:"); DEBUG(dbgs() << "Available regs:");
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
if (!State->IsLive(Reg)) if (!State->IsLive(Reg))
DEBUG(dbgs() << " " << TRI->getName(Reg)); DEBUG(dbgs() << " " << TRI->getName(Reg));
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
#endif #endif
▲ Show 20 Lines • Show All 185 Lines • Show Last 20 Lines

lib/CodeGen/AllocationOrder.cpp

Show All 40 LinesAllocationOrder::AllocationOrder(unsigned VirtReg,
DEBUG({ DEBUG({
if (!Hints.empty()) { if (!Hints.empty()) {
dbgs() << "hints:"; dbgs() << "hints:";
for (unsigned I = 0, E = Hints.size(); I != E; ++I) for (unsigned I = 0, E = Hints.size(); I != E; ++I)
dbgs() << ' ' << PrintReg(Hints[I], TRI); dbgs() << ' ' << PrintReg(Hints[I], TRI);
dbgs() << '\n'; dbgs() << '\n';
} }
}); });
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned I = 0, E = Hints.size(); I != E; ++I) for (unsigned I = 0, E = Hints.size(); I != E; ++I)
assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() && assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
"Target hint is outside allocation order."); "Target hint is outside allocation order.");
#endif #endif
} }

lib/CodeGen/AsmPrinter/DIE.cpp

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines AP->EmitULEB128(AttrData.getForm(),
dwarf::FormEncodingString(AttrData.getForm())); dwarf::FormEncodingString(AttrData.getForm()));
} }
// Mark end of abbreviation. // Mark end of abbreviation.
AP->EmitULEB128(0, "EOM(1)"); AP->EmitULEB128(0, "EOM(1)");
AP->EmitULEB128(0, "EOM(2)"); AP->EmitULEB128(0, "EOM(2)");
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEAbbrev::print(raw_ostream &O) { void DIEAbbrev::print(raw_ostream &O) {
O << "Abbreviation @" O << "Abbreviation @"
<< format("0x%lx", (long)(intptr_t)this) << format("0x%lx", (long)(intptr_t)this)
<< " " << " "
<< dwarf::TagString(Tag) << dwarf::TagString(Tag)
<< " " << " "
<< dwarf::ChildrenString(Children) << dwarf::ChildrenString(Children)
<< '\n'; << '\n';
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 LinesDIEValue DIE::findAttribute(dwarf::Attribute Attribute) const {
// Iterate through all the attributes until we find the one we're // Iterate through all the attributes until we find the one we're
// looking for, if we can't find it return NULL. // looking for, if we can't find it return NULL.
for (const auto &V : values()) for (const auto &V : values())
if (V.getAttribute() == Attribute) if (V.getAttribute() == Attribute)
return V; return V;
return DIEValue(); return DIEValue();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static void printValues(raw_ostream &O, const DIEValueList &Values, static void printValues(raw_ostream &O, const DIEValueList &Values,
StringRef Type, unsigned Size, unsigned IndentCount) { StringRef Type, unsigned Size, unsigned IndentCount) {
O << Type << ": Size: " << Size << "\n"; O << Type << ": Size: " << Size << "\n";
unsigned I = 0; unsigned I = 0;
const std::string Indent(IndentCount, ' '); const std::string Indent(IndentCount, ' ');
for (const auto &V : Values.values()) { for (const auto &V : Values.values()) {
O << Indent; O << Indent;
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
#define HANDLE_DIEVALUE(T) \ #define HANDLE_DIEVALUE(T) \
case is##T: \ case is##T: \
return getDIE##T().SizeOf(AP, Form); return getDIE##T().SizeOf(AP, Form);
#include "llvm/CodeGen/DIEValue.def" #include "llvm/CodeGen/DIEValue.def"
} }
llvm_unreachable("Unknown DIE kind"); llvm_unreachable("Unknown DIE kind");
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEValue::print(raw_ostream &O) const { void DIEValue::print(raw_ostream &O) const {
switch (Ty) { switch (Ty) {
case isNone: case isNone:
llvm_unreachable("Expected valid DIEValue"); llvm_unreachable("Expected valid DIEValue");
#define HANDLE_DIEVALUE(T) \ #define HANDLE_DIEVALUE(T) \
case is##T: \ case is##T: \
getDIE##T().print(O); \ getDIE##T().print(O); \
break; break;
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesunsigned DIEInteger::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
case dwarf::DW_FORM_ref_addr: case dwarf::DW_FORM_ref_addr:
if (AP->OutStreamer->getContext().getDwarfVersion() == 2) if (AP->OutStreamer->getContext().getDwarfVersion() == 2)
return AP->getPointerSize(); return AP->getPointerSize();
return sizeof(int32_t); return sizeof(int32_t);
default: llvm_unreachable("DIE Value form not supported yet"); default: llvm_unreachable("DIE Value form not supported yet");
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEInteger::print(raw_ostream &O) const { void DIEInteger::print(raw_ostream &O) const {
O << "Int: " << (int64_t)Integer << " 0x"; O << "Int: " << (int64_t)Integer << " 0x";
O.write_hex(Integer); O.write_hex(Integer);
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIEExpr Implementation // DIEExpr Implementation
Show All 9 Lines
/// ///
unsigned DIEExpr::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const { unsigned DIEExpr::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
if (Form == dwarf::DW_FORM_data4) return 4; if (Form == dwarf::DW_FORM_data4) return 4;
if (Form == dwarf::DW_FORM_sec_offset) return 4; if (Form == dwarf::DW_FORM_sec_offset) return 4;
if (Form == dwarf::DW_FORM_strp) return 4; if (Form == dwarf::DW_FORM_strp) return 4;
return AP->getPointerSize(); return AP->getPointerSize();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEExpr::print(raw_ostream &O) const { O << "Expr: " << *Expr; } void DIEExpr::print(raw_ostream &O) const { O << "Expr: " << *Expr; }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIELabel Implementation // DIELabel Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// EmitValue - Emit label value. /// EmitValue - Emit label value.
Show All 9 Lines
/// ///
unsigned DIELabel::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const { unsigned DIELabel::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
if (Form == dwarf::DW_FORM_data4) return 4; if (Form == dwarf::DW_FORM_data4) return 4;
if (Form == dwarf::DW_FORM_sec_offset) return 4; if (Form == dwarf::DW_FORM_sec_offset) return 4;
if (Form == dwarf::DW_FORM_strp) return 4; if (Form == dwarf::DW_FORM_strp) return 4;
return AP->getPointerSize(); return AP->getPointerSize();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIELabel::print(raw_ostream &O) const { O << "Lbl: " << Label->getName(); } void DIELabel::print(raw_ostream &O) const { O << "Lbl: " << Label->getName(); }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIEDelta Implementation // DIEDelta Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// EmitValue - Emit delta value. /// EmitValue - Emit delta value.
/// ///
void DIEDelta::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { void DIEDelta::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const {
AP->EmitLabelDifference(LabelHi, LabelLo, SizeOf(AP, Form)); AP->EmitLabelDifference(LabelHi, LabelLo, SizeOf(AP, Form));
} }
/// SizeOf - Determine size of delta value in bytes. /// SizeOf - Determine size of delta value in bytes.
/// ///
unsigned DIEDelta::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const { unsigned DIEDelta::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
if (Form == dwarf::DW_FORM_data4) return 4; if (Form == dwarf::DW_FORM_data4) return 4;
if (Form == dwarf::DW_FORM_sec_offset) return 4; if (Form == dwarf::DW_FORM_sec_offset) return 4;
if (Form == dwarf::DW_FORM_strp) return 4; if (Form == dwarf::DW_FORM_strp) return 4;
return AP->getPointerSize(); return AP->getPointerSize();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEDelta::print(raw_ostream &O) const { void DIEDelta::print(raw_ostream &O) const {
O << "Del: " << LabelHi->getName() << "-" << LabelLo->getName(); O << "Del: " << LabelHi->getName() << "-" << LabelLo->getName();
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIEString Implementation // DIEString Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 36 Linesunsigned DIEString::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
// Relocatable symbol. // Relocatable symbol.
if (AP->MAI->doesDwarfUseRelocationsAcrossSections()) if (AP->MAI->doesDwarfUseRelocationsAcrossSections())
return DIELabel(S.getSymbol()).SizeOf(AP, Form); return DIELabel(S.getSymbol()).SizeOf(AP, Form);
// Offset into symbol table. // Offset into symbol table.
return DIEInteger(S.getOffset()).SizeOf(AP, Form); return DIEInteger(S.getOffset()).SizeOf(AP, Form);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEString::print(raw_ostream &O) const { void DIEString::print(raw_ostream &O) const {
O << "String: " << S.getString(); O << "String: " << S.getString();
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIEEntry Implementation // DIEEntry Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 28 Linesunsigned DIEEntry::getRefAddrSize(const AsmPrinter *AP) {
// references have the same size as an address on the target system. // references have the same size as an address on the target system.
const DwarfDebug *DD = AP->getDwarfDebug(); const DwarfDebug *DD = AP->getDwarfDebug();
assert(DD && "Expected Dwarf Debug info to be available"); assert(DD && "Expected Dwarf Debug info to be available");
if (DD->getDwarfVersion() == 2) if (DD->getDwarfVersion() == 2)
return AP->getPointerSize(); return AP->getPointerSize();
return sizeof(int32_t); return sizeof(int32_t);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEEntry::print(raw_ostream &O) const { void DIEEntry::print(raw_ostream &O) const {
O << format("Die: 0x%lx", (long)(intptr_t)&Entry); O << format("Die: 0x%lx", (long)(intptr_t)&Entry);
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIETypeSignature Implementation // DIETypeSignature Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void DIETypeSignature::EmitValue(const AsmPrinter *Asm, void DIETypeSignature::EmitValue(const AsmPrinter *Asm,
dwarf::Form Form) const { dwarf::Form Form) const {
assert(Form == dwarf::DW_FORM_ref_sig8); assert(Form == dwarf::DW_FORM_ref_sig8);
Asm->OutStreamer->EmitIntValue(Unit->getTypeSignature(), 8); Asm->OutStreamer->EmitIntValue(Unit->getTypeSignature(), 8);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIETypeSignature::print(raw_ostream &O) const { void DIETypeSignature::print(raw_ostream &O) const {
O << format("Type Unit: 0x%lx", Unit->getTypeSignature()); O << format("Type Unit: 0x%lx", Unit->getTypeSignature());
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIELoc Implementation // DIELoc Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 35 Linesunsigned DIELoc::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
case dwarf::DW_FORM_block4: return Size + sizeof(int32_t); case dwarf::DW_FORM_block4: return Size + sizeof(int32_t);
case dwarf::DW_FORM_block: case dwarf::DW_FORM_block:
case dwarf::DW_FORM_exprloc: case dwarf::DW_FORM_exprloc:
return Size + getULEB128Size(Size); return Size + getULEB128Size(Size);
default: llvm_unreachable("Improper form for block"); default: llvm_unreachable("Improper form for block");
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIELoc::print(raw_ostream &O) const { void DIELoc::print(raw_ostream &O) const {
printValues(O, *this, "ExprLoc", Size, 5); printValues(O, *this, "ExprLoc", Size, 5);
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIEBlock Implementation // DIEBlock Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 31 Linesunsigned DIEBlock::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
case dwarf::DW_FORM_block1: return Size + sizeof(int8_t); case dwarf::DW_FORM_block1: return Size + sizeof(int8_t);
case dwarf::DW_FORM_block2: return Size + sizeof(int16_t); case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
case dwarf::DW_FORM_block4: return Size + sizeof(int32_t); case dwarf::DW_FORM_block4: return Size + sizeof(int32_t);
case dwarf::DW_FORM_block: return Size + getULEB128Size(Size); case dwarf::DW_FORM_block: return Size + getULEB128Size(Size);
default: llvm_unreachable("Improper form for block"); default: llvm_unreachable("Improper form for block");
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIEBlock::print(raw_ostream &O) const { void DIEBlock::print(raw_ostream &O) const {
printValues(O, *this, "Blk", Size, 5); printValues(O, *this, "Blk", Size, 5);
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DIELocList Implementation // DIELocList Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 9 Lines
/// EmitValue - Emit label value. /// EmitValue - Emit label value.
/// ///
void DIELocList::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { void DIELocList::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const {
DwarfDebug *DD = AP->getDwarfDebug(); DwarfDebug *DD = AP->getDwarfDebug();
MCSymbol *Label = DD->getDebugLocs().getList(Index).Label; MCSymbol *Label = DD->getDebugLocs().getList(Index).Label;
AP->emitDwarfSymbolReference(Label, /*ForceOffset*/ DD->useSplitDwarf()); AP->emitDwarfSymbolReference(Label, /*ForceOffset*/ DD->useSplitDwarf());
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DIELocList::print(raw_ostream &O) const { O << "LocList: " << Index; } void DIELocList::print(raw_ostream &O) const { O << "LocList: " << Index; }
#endif #endif

lib/CodeGen/AsmPrinter/DwarfAccelTable.h

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines struct TableHeader {
static const uint32_t MagicHash = 0x48415348; static const uint32_t MagicHash = 0x48415348;
TableHeader(uint32_t data_len) TableHeader(uint32_t data_len)
: magic(MagicHash), version(1), : magic(MagicHash), version(1),
hash_function(dwarf::DW_hash_function_djb), bucket_count(0), hash_function(dwarf::DW_hash_function_djb), bucket_count(0),
hashes_count(0), header_data_len(data_len) {} hashes_count(0), header_data_len(data_len) {}
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) { void print(raw_ostream &O) {
O << "Magic: " << format("0x%x", magic) << "\n" O << "Magic: " << format("0x%x", magic) << "\n"
<< "Version: " << version << "\n" << "Version: " << version << "\n"
<< "Hash Function: " << hash_function << "\n" << "Hash Function: " << hash_function << "\n"
<< "Bucket Count: " << bucket_count << "\n" << "Bucket Count: " << bucket_count << "\n"
<< "Header Data Length: " << header_data_len << "\n"; << "Header Data Length: " << header_data_len << "\n";
} }
void dump() { print(dbgs()); } void dump() { print(dbgs()); }
Show All 16 Linespublic:
// Make these public so that they can be used as a general interface to // Make these public so that they can be used as a general interface to
// the class. // the class.
struct Atom { struct Atom {
uint16_t type; // enum AtomType uint16_t type; // enum AtomType
uint16_t form; // DWARF DW_FORM_ defines uint16_t form; // DWARF DW_FORM_ defines
LLVM_CONSTEXPR Atom(uint16_t type, uint16_t form) LLVM_CONSTEXPR Atom(uint16_t type, uint16_t form)
: type(type), form(form) {} : type(type), form(form) {}
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) { void print(raw_ostream &O) {
O << "Type: " << dwarf::AtomTypeString(type) << "\n" O << "Type: " << dwarf::AtomTypeString(type) << "\n"
<< "Form: " << dwarf::FormEncodingString(form) << "\n"; << "Form: " << dwarf::FormEncodingString(form) << "\n";
} }
void dump() { print(dbgs()); } void dump() { print(dbgs()); }
#endif #endif
}; };
private: private:
struct TableHeaderData { struct TableHeaderData {
uint32_t die_offset_base; uint32_t die_offset_base;
SmallVector<Atom, 3> Atoms; SmallVector<Atom, 3> Atoms;
TableHeaderData(ArrayRef<Atom> AtomList, uint32_t offset = 0) TableHeaderData(ArrayRef<Atom> AtomList, uint32_t offset = 0)
: die_offset_base(offset), Atoms(AtomList.begin(), AtomList.end()) {} : die_offset_base(offset), Atoms(AtomList.begin(), AtomList.end()) {}
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) { void print(raw_ostream &O) {
O << "die_offset_base: " << die_offset_base << "\n"; O << "die_offset_base: " << die_offset_base << "\n";
for (size_t i = 0; i < Atoms.size(); i++) for (size_t i = 0; i < Atoms.size(); i++)
Atoms[i].print(O); Atoms[i].print(O);
} }
void dump() { print(dbgs()); } void dump() { print(dbgs()); }
#endif #endif
}; };
// The data itself consists of a str_offset, a count of the DIEs in the // The data itself consists of a str_offset, a count of the DIEs in the
// hash and the offsets to the DIEs themselves. // hash and the offsets to the DIEs themselves.
// On disk each data section is ended with a 0 KeyType as the end of the // On disk each data section is ended with a 0 KeyType as the end of the
// hash chain. // hash chain.
// On output this looks like: // On output this looks like:
// uint32_t str_offset // uint32_t str_offset
// uint32_t hash_data_count // uint32_t hash_data_count
// HashData[hash_data_count] // HashData[hash_data_count]
public: public:
struct HashDataContents { struct HashDataContents {
const DIE *Die; // Offsets const DIE *Die; // Offsets
char Flags; // Specific flags to output char Flags; // Specific flags to output
HashDataContents(const DIE *D, char Flags) : Die(D), Flags(Flags) {} HashDataContents(const DIE *D, char Flags) : Die(D), Flags(Flags) {}
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) const { void print(raw_ostream &O) const {
O << " Offset: " << Die->getOffset() << "\n"; O << " Offset: " << Die->getOffset() << "\n";
O << " Tag: " << dwarf::TagString(Die->getTag()) << "\n"; O << " Tag: " << dwarf::TagString(Die->getTag()) << "\n";
O << " Flags: " << Flags << "\n"; O << " Flags: " << Flags << "\n";
} }
#endif #endif
}; };
private: private:
// String Data // String Data
struct DataArray { struct DataArray {
DwarfStringPoolEntryRef Name; DwarfStringPoolEntryRef Name;
std::vector<HashDataContents *> Values; std::vector<HashDataContents *> Values;
}; };
friend struct HashData; friend struct HashData;
struct HashData { struct HashData {
StringRef Str; StringRef Str;
uint32_t HashValue; uint32_t HashValue;
MCSymbol *Sym; MCSymbol *Sym;
DwarfAccelTable::DataArray &Data; // offsets DwarfAccelTable::DataArray &Data; // offsets
HashData(StringRef S, DwarfAccelTable::DataArray &Data) HashData(StringRef S, DwarfAccelTable::DataArray &Data)
: Str(S), Data(Data) { : Str(S), Data(Data) {
HashValue = DwarfAccelTable::HashDJB(S); HashValue = DwarfAccelTable::HashDJB(S);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O) { void print(raw_ostream &O) {
O << "Name: " << Str << "\n"; O << "Name: " << Str << "\n";
O << " Hash Value: " << format("0x%x", HashValue) << "\n"; O << " Hash Value: " << format("0x%x", HashValue) << "\n";
O << " Symbol: "; O << " Symbol: ";
if (Sym) if (Sym)
O << *Sym; O << *Sym;
else else
O << "<none>"; O << "<none>";
Show All 36 Lines#endif
HashList Hashes; HashList Hashes;
// Public Implementation // Public Implementation
public: public:
DwarfAccelTable(ArrayRef<DwarfAccelTable::Atom>); DwarfAccelTable(ArrayRef<DwarfAccelTable::Atom>);
void AddName(DwarfStringPoolEntryRef Name, const DIE *Die, char Flags = 0); void AddName(DwarfStringPoolEntryRef Name, const DIE *Die, char Flags = 0);
void FinalizeTable(AsmPrinter *, StringRef); void FinalizeTable(AsmPrinter *, StringRef);
void emit(AsmPrinter *, const MCSymbol *, DwarfDebug *); void emit(AsmPrinter *, const MCSymbol *, DwarfDebug *);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void print(raw_ostream &O); void print(raw_ostream &O);
void dump() { print(dbgs()); } void dump() { print(dbgs()); }
#endif #endif
}; };
} }
#endif #endif

lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp

Show First 20 Lines • Show All 252 Lines • ▼ Show 20 Linesvoid DwarfAccelTable::emit(AsmPrinter *Asm, const MCSymbol *SecBegin,
// Emit the offsets. // Emit the offsets.
emitOffsets(Asm, SecBegin); emitOffsets(Asm, SecBegin);
// Emit the hash data. // Emit the hash data.
EmitData(Asm, D); EmitData(Asm, D);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void DwarfAccelTable::print(raw_ostream &O) { void DwarfAccelTable::print(raw_ostream &O) {
Header.print(O); Header.print(O);
HeaderData.print(O); HeaderData.print(O);
O << "Entries: \n"; O << "Entries: \n";
for (StringMap<DataArray>::const_iterator EI = Entries.begin(), for (StringMap<DataArray>::const_iterator EI = Entries.begin(),
EE = Entries.end(); EE = Entries.end();
Show All 20 Lines

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Show First 20 Lines • Show All 1,234 Lines • ▼ Show 20 Lines if (TheCU.getCUNode()->getEmissionKind() == DIBuilder::LineTablesOnly &&
assert(AbstractVariables.empty()); assert(AbstractVariables.empty());
LabelsBeforeInsn.clear(); LabelsBeforeInsn.clear();
LabelsAfterInsn.clear(); LabelsAfterInsn.clear();
PrevLabel = nullptr; PrevLabel = nullptr;
CurFn = nullptr; CurFn = nullptr;
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
size_t NumAbstractScopes = LScopes.getAbstractScopesList().size(); size_t NumAbstractScopes = LScopes.getAbstractScopesList().size();
#endif #endif
// Construct abstract scopes. // Construct abstract scopes.
for (LexicalScope *AScope : LScopes.getAbstractScopesList()) { for (LexicalScope *AScope : LScopes.getAbstractScopesList()) {
auto *SP = cast<DISubprogram>(AScope->getScopeNode()); auto *SP = cast<DISubprogram>(AScope->getScopeNode());
// Collect info for variables that were optimized out. // Collect info for variables that were optimized out.
for (const DILocalVariable *DV : SP->getVariables()) { for (const DILocalVariable *DV : SP->getVariables()) {
if (!ProcessedVars.insert(InlinedVariable(DV, nullptr)).second) if (!ProcessedVars.insert(InlinedVariable(DV, nullptr)).second)
▲ Show 20 Lines • Show All 777 Lines • Show Last 20 Lines

lib/CodeGen/CallingConvLower.cpp

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
CCAssignFn Fn) { CCAssignFn Fn) {
unsigned NumArgs = Ins.size(); unsigned NumArgs = Ins.size();
for (unsigned i = 0; i != NumArgs; ++i) { for (unsigned i = 0; i != NumArgs; ++i) {
MVT ArgVT = Ins[i].VT; MVT ArgVT = Ins[i].VT;
ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Formal argument #" << i << " has unhandled type " dbgs() << "Formal argument #" << i << " has unhandled type "
<< EVT(ArgVT).getEVTString() << '\n'; << EVT(ArgVT).getEVTString() << '\n';
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
} }
Show All 15 Lines
/// incorporating info about the result values into this state. /// incorporating info about the result values into this state.
void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
CCAssignFn Fn) { CCAssignFn Fn) {
// Determine which register each value should be copied into. // Determine which register each value should be copied into.
for (unsigned i = 0, e = Outs.size(); i != e; ++i) { for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
MVT VT = Outs[i].VT; MVT VT = Outs[i].VT;
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Return operand #" << i << " has unhandled type " dbgs() << "Return operand #" << i << " has unhandled type "
<< EVT(VT).getEVTString() << '\n'; << EVT(VT).getEVTString() << '\n';
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
} }
/// Analyze the outgoing arguments to a call, /// Analyze the outgoing arguments to a call,
/// incorporating info about the passed values into this state. /// incorporating info about the passed values into this state.
void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
CCAssignFn Fn) { CCAssignFn Fn) {
unsigned NumOps = Outs.size(); unsigned NumOps = Outs.size();
for (unsigned i = 0; i != NumOps; ++i) { for (unsigned i = 0; i != NumOps; ++i) {
MVT ArgVT = Outs[i].VT; MVT ArgVT = Outs[i].VT;
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Call operand #" << i << " has unhandled type " dbgs() << "Call operand #" << i << " has unhandled type "
<< EVT(ArgVT).getEVTString() << '\n'; << EVT(ArgVT).getEVTString() << '\n';
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
} }
/// Same as above except it takes vectors of types and argument flags. /// Same as above except it takes vectors of types and argument flags.
void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs, void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &Flags, SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
CCAssignFn Fn) { CCAssignFn Fn) {
unsigned NumOps = ArgVTs.size(); unsigned NumOps = ArgVTs.size();
for (unsigned i = 0; i != NumOps; ++i) { for (unsigned i = 0; i != NumOps; ++i) {
MVT ArgVT = ArgVTs[i]; MVT ArgVT = ArgVTs[i];
ISD::ArgFlagsTy ArgFlags = Flags[i]; ISD::ArgFlagsTy ArgFlags = Flags[i];
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Call operand #" << i << " has unhandled type " dbgs() << "Call operand #" << i << " has unhandled type "
<< EVT(ArgVT).getEVTString() << '\n'; << EVT(ArgVT).getEVTString() << '\n';
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
} }
/// Analyze the return values of a call, incorporating info about the passed /// Analyze the return values of a call, incorporating info about the passed
/// values into this state. /// values into this state.
void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
CCAssignFn Fn) { CCAssignFn Fn) {
for (unsigned i = 0, e = Ins.size(); i != e; ++i) { for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
MVT VT = Ins[i].VT; MVT VT = Ins[i].VT;
ISD::ArgFlagsTy Flags = Ins[i].Flags; ISD::ArgFlagsTy Flags = Ins[i].Flags;
if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Call result #" << i << " has unhandled type " dbgs() << "Call result #" << i << " has unhandled type "
<< EVT(VT).getEVTString() << '\n'; << EVT(VT).getEVTString() << '\n';
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
} }
/// Same as above except it's specialized for calls that produce a single value. /// Same as above except it's specialized for calls that produce a single value.
void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Call result has unhandled type " dbgs() << "Call result has unhandled type "
<< EVT(VT).getEVTString() << '\n'; << EVT(VT).getEVTString() << '\n';
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) {
Show All 16 Linesvoid CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
if (isValueTypeInRegForCC(CallingConv, VT)) if (isValueTypeInRegForCC(CallingConv, VT))
Flags.setInReg(); Flags.setInReg();
// Allocate something of this value type repeatedly until we get assigned a // Allocate something of this value type repeatedly until we get assigned a
// location in memory. // location in memory.
bool HaveRegParm = true; bool HaveRegParm = true;
while (HaveRegParm) { while (HaveRegParm) {
if (Fn(0, VT, VT, CCValAssign::Full, Flags, *this)) { if (Fn(0, VT, VT, CCValAssign::Full, Flags, *this)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Call has unhandled type " << EVT(VT).getEVTString() dbgs() << "Call has unhandled type " << EVT(VT).getEVTString()
<< " while computing remaining regparms\n"; << " while computing remaining regparms\n";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
HaveRegParm = Locs.back().isRegLoc(); HaveRegParm = Locs.back().isRegLoc();
} }
Show All 32 Lines

lib/CodeGen/CodeGenPrepare.cpp

Show First 20 Lines • Show All 802 Lines • ▼ Show 20 Linesstatic bool CombineUAddWithOverflow(CmpInst *CI) {
// We don't want to move around uses of condition values this late, so we we // We don't want to move around uses of condition values this late, so we we
// check if it is legal to create the call to the intrinsic in the basic // check if it is legal to create the call to the intrinsic in the basic
// block containing the icmp: // block containing the icmp:
if (AddI->getParent() != CI->getParent() && !AddI->hasOneUse()) if (AddI->getParent() != CI->getParent() && !AddI->hasOneUse())
return false; return false;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Someday m_UAddWithOverflow may get smarter, but this is a safe assumption // Someday m_UAddWithOverflow may get smarter, but this is a safe assumption
// for now: // for now:
if (AddI->hasOneUse()) if (AddI->hasOneUse())
assert(*AddI->user_begin() == CI && "expected!"); assert(*AddI->user_begin() == CI && "expected!");
#endif #endif
Module *M = CI->getParent()->getParent()->getParent(); Module *M = CI->getParent()->getParent()->getParent();
Value *F = Intrinsic::getDeclaration(M, Intrinsic::uadd_with_overflow, Ty); Value *F = Intrinsic::getDeclaration(M, Intrinsic::uadd_with_overflow, Ty);
▲ Show 20 Lines • Show All 785 Lines • ▼ Show 20 Linesstruct ExtAddrMode : public TargetLowering::AddrMode {
bool operator==(const ExtAddrMode& O) const { bool operator==(const ExtAddrMode& O) const {
return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) && return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
(BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) &&
(HasBaseReg == O.HasBaseReg) && (Scale == O.Scale); (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
} }
}; };
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) { static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) {
AM.print(OS); AM.print(OS);
return OS; return OS;
} }
#endif #endif
void ExtAddrMode::print(raw_ostream &OS) const { void ExtAddrMode::print(raw_ostream &OS) const {
bool NeedPlus = false; bool NeedPlus = false;
Show All 21 Lines if (Scale) {
OS << (NeedPlus ? " + " : "") OS << (NeedPlus ? " + " : "")
<< Scale << "*"; << Scale << "*";
ScaledReg->printAsOperand(OS, /*PrintType=*/false); ScaledReg->printAsOperand(OS, /*PrintType=*/false);
} }
OS << ']'; OS << ']';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void ExtAddrMode::dump() const { void ExtAddrMode::dump() const {
print(dbgs()); print(dbgs());
dbgs() << '\n'; dbgs() << '\n';
} }
#endif #endif
/// \brief This class provides transaction based operation on the IR. /// \brief This class provides transaction based operation on the IR.
/// Every change made through this class is recorded in the internal state and /// Every change made through this class is recorded in the internal state and
▲ Show 20 Lines • Show All 3,168 Lines • Show Last 20 Lines

lib/CodeGen/CriticalAntiDepBreaker.cpp

Show First 20 Lines • Show All 438 Lines • ▼ Show 20 LinesBreakAntiDependencies(const std::vector<SUnit>& SUnits,
const SUnit *Max = nullptr; const SUnit *Max = nullptr;
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
const SUnit *SU = &SUnits[i]; const SUnit *SU = &SUnits[i];
MISUnitMap[SU->getInstr()] = SU; MISUnitMap[SU->getInstr()] = SU;
if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
Max = SU; Max = SU;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
{ {
DEBUG(dbgs() << "Critical path has total latency " DEBUG(dbgs() << "Critical path has total latency "
<< (Max->getDepth() + Max->Latency) << "\n"); << (Max->getDepth() + Max->Latency) << "\n");
DEBUG(dbgs() << "Available regs:"); DEBUG(dbgs() << "Available regs:");
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
if (KillIndices[Reg] == ~0u) if (KillIndices[Reg] == ~0u)
DEBUG(dbgs() << " " << TRI->getName(Reg)); DEBUG(dbgs() << " " << TRI->getName(Reg));
} }
▲ Show 20 Lines • Show All 226 Lines • Show Last 20 Lines

lib/CodeGen/IfConversion.cpp

Show First 20 Lines • Show All 1,583 Lines • ▼ Show 20 Lines for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
if (MaySpec && MaySpeculate(I, *LaterRedefs)) { if (MaySpec && MaySpeculate(I, *LaterRedefs)) {
AnyUnpred = true; AnyUnpred = true;
continue; continue;
} }
// If any instruction is predicated, then every instruction after it must // If any instruction is predicated, then every instruction after it must
// be predicated. // be predicated.
MaySpec = false; MaySpec = false;
if (!TII->PredicateInstruction(I, Cond)) { if (!TII->PredicateInstruction(I, Cond)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Unable to predicate " << *I << "!\n"; dbgs() << "Unable to predicate " << *I << "!\n";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
// If the predicated instruction now redefines a register as the result of // If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill. // if-conversion, add an implicit kill.
UpdatePredRedefs(I, Redefs); UpdatePredRedefs(I, Redefs);
Show All 28 Lines for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
unsigned ExtraPredCost = TII->getPredicationCost(&*I); unsigned ExtraPredCost = TII->getPredicationCost(&*I);
unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false); unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
if (NumCycles > 1) if (NumCycles > 1)
ToBBI.ExtraCost += NumCycles-1; ToBBI.ExtraCost += NumCycles-1;
ToBBI.ExtraCost2 += ExtraPredCost; ToBBI.ExtraCost2 += ExtraPredCost;
if (!TII->isPredicated(I) && !MI->isDebugValue()) { if (!TII->isPredicated(I) && !MI->isDebugValue()) {
if (!TII->PredicateInstruction(MI, Cond)) { if (!TII->PredicateInstruction(MI, Cond)) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Unable to predicate " << *I << "!\n"; dbgs() << "Unable to predicate " << *I << "!\n";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
// If the predicated instruction now redefines a register as the result of // If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill. // if-conversion, add an implicit kill.
▲ Show 20 Lines • Show All 82 Lines • Show Last 20 Lines

lib/CodeGen/InlineSpiller.cpp

Show First 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
// the value has already been spilled, or we may want to hoist the spill from a // the value has already been spilled, or we may want to hoist the spill from a
// loop. // loop.
bool InlineSpiller::isSibling(unsigned Reg) { bool InlineSpiller::isSibling(unsigned Reg) {
return TargetRegisterInfo::isVirtualRegister(Reg) && return TargetRegisterInfo::isVirtualRegister(Reg) &&
VRM.getOriginal(Reg) == Original; VRM.getOriginal(Reg) == Original;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static raw_ostream &operator<<(raw_ostream &OS, static raw_ostream &operator<<(raw_ostream &OS,
const InlineSpiller::SibValueInfo &SVI) { const InlineSpiller::SibValueInfo &SVI) {
OS << "spill " << PrintReg(SVI.SpillReg) << ':' OS << "spill " << PrintReg(SVI.SpillReg) << ':'
<< SVI.SpillVNI->id << '@' << SVI.SpillVNI->def; << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
if (SVI.SpillMBB) if (SVI.SpillMBB)
OS << " in BB#" << SVI.SpillMBB->getNumber(); OS << " in BB#" << SVI.SpillMBB->getNumber();
if (SVI.AllDefsAreReloads) if (SVI.AllDefsAreReloads)
OS << " all-reloads"; OS << " all-reloads";
▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Linesbool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
} else { } else {
++NumSpillsRemoved; ++NumSpillsRemoved;
--NumSpills; --NumSpills;
} }
return true; return true;
} }
#if !defined(NDEBUG) #if !defined(LLVM_NDEBUG)
// Dump the range of instructions from B to E with their slot indexes. // Dump the range of instructions from B to E with their slot indexes.
static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B, static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
MachineBasicBlock::iterator E, MachineBasicBlock::iterator E,
LiveIntervals const &LIS, LiveIntervals const &LIS,
const char *const header, const char *const header,
unsigned VReg =0) { unsigned VReg =0) {
char NextLine = '\n'; char NextLine = '\n';
char SlotIndent = '\t'; char SlotIndent = '\t';
▲ Show 20 Lines • Show All 349 Lines • Show Last 20 Lines

lib/CodeGen/LexicalScopes.cpp

Show First 20 Lines • Show All 308 Lines • ▼ Show 20 Lines if (const DILocation *IDL = I->getDebugLoc())
if (Scope->dominates(IScope)) if (Scope->dominates(IScope))
return true; return true;
} }
return Result; return Result;
} }
/// dump - Print data structures. /// dump - Print data structures.
void LexicalScope::dump(unsigned Indent) const { void LexicalScope::dump(unsigned Indent) const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
raw_ostream &err = dbgs(); raw_ostream &err = dbgs();
err.indent(Indent); err.indent(Indent);
err << "DFSIn: " << DFSIn << " DFSOut: " << DFSOut << "\n"; err << "DFSIn: " << DFSIn << " DFSOut: " << DFSOut << "\n";
const MDNode *N = Desc; const MDNode *N = Desc;
err.indent(Indent); err.indent(Indent);
N->dump(); N->dump();
if (AbstractScope) if (AbstractScope)
err << std::string(Indent, ' ') << "Abstract Scope\n"; err << std::string(Indent, ' ') << "Abstract Scope\n";
if (!Children.empty()) if (!Children.empty())
err << std::string(Indent + 2, ' ') << "Children ...\n"; err << std::string(Indent + 2, ' ') << "Children ...\n";
for (unsigned i = 0, e = Children.size(); i != e; ++i) for (unsigned i = 0, e = Children.size(); i != e; ++i)
if (Children[i] != this) if (Children[i] != this)
Children[i]->dump(Indent + 2); Children[i]->dump(Indent + 2);
#endif #endif
} }

lib/CodeGen/LiveDebugVariables.cpp

Show First 20 Lines • Show All 1,045 Lines • ▼ Show 20 Lines if (pImpl)
static_cast<LDVImpl*>(pImpl)->emitDebugValues(VRM); static_cast<LDVImpl*>(pImpl)->emitDebugValues(VRM);
} }
bool LiveDebugVariables::doInitialization(Module &M) { bool LiveDebugVariables::doInitialization(Module &M) {
FunctionDIs = makeSubprogramMap(M); FunctionDIs = makeSubprogramMap(M);
return Pass::doInitialization(M); return Pass::doInitialization(M);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void LiveDebugVariables::dump() { void LiveDebugVariables::dump() {
if (pImpl) if (pImpl)
static_cast<LDVImpl*>(pImpl)->print(dbgs()); static_cast<LDVImpl*>(pImpl)->print(dbgs());
} }
#endif #endif

lib/CodeGen/LiveInterval.cpp

Show First 20 Lines • Show All 1,019 Lines • ▼ Show 20 Lines for (const Segment &S : segments)
Sum += S.start.distance(S.end); Sum += S.start.distance(S.end);
return Sum; return Sum;
} }
raw_ostream& llvm::operator<<(raw_ostream& os, const LiveRange::Segment &S) { raw_ostream& llvm::operator<<(raw_ostream& os, const LiveRange::Segment &S) {
return os << '[' << S.start << ',' << S.end << ':' << S.valno->id << ")"; return os << '[' << S.start << ',' << S.end << ':' << S.valno->id << ")";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void LiveRange::Segment::dump() const { void LiveRange::Segment::dump() const {
dbgs() << *this << "\n"; dbgs() << *this << "\n";
} }
#endif #endif
void LiveRange::print(raw_ostream &OS) const { void LiveRange::print(raw_ostream &OS) const {
if (empty()) if (empty())
OS << "EMPTY"; OS << "EMPTY";
Show All 28 Linesvoid LiveInterval::print(raw_ostream &OS) const {
OS << PrintReg(reg) << ' '; OS << PrintReg(reg) << ' ';
super::print(OS); super::print(OS);
// Print subranges // Print subranges
for (const SubRange &SR : subranges()) { for (const SubRange &SR : subranges()) {
OS << format(" L%04X ", SR.LaneMask) << SR; OS << format(" L%04X ", SR.LaneMask) << SR;
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void LiveRange::dump() const { void LiveRange::dump() const {
dbgs() << *this << "\n"; dbgs() << *this << "\n";
} }
void LiveInterval::dump() const { void LiveInterval::dump() const {
dbgs() << *this << "\n"; dbgs() << *this << "\n";
} }
#endif #endif
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void LiveRange::verify() const { void LiveRange::verify() const {
for (const_iterator I = begin(), E = end(); I != E; ++I) { for (const_iterator I = begin(), E = end(); I != E; ++I) {
assert(I->start.isValid()); assert(I->start.isValid());
assert(I->end.isValid()); assert(I->end.isValid());
assert(I->start < I->end); assert(I->start < I->end);
assert(I->valno != nullptr); assert(I->valno != nullptr);
assert(I->valno->id < valnos.size()); assert(I->valno->id < valnos.size());
assert(I->valno == valnos[I->valno->id]); assert(I->valno == valnos[I->valno->id]);
▲ Show 20 Lines • Show All 344 Lines • Show Last 20 Lines

lib/CodeGen/LiveIntervalAnalysis.cpp

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 LinesINITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
"Live Interval Analysis", false, false) "Live Interval Analysis", false, false)
INITIALIZE_AG_DEPENDENCY(AliasAnalysis) INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
INITIALIZE_PASS_DEPENDENCY(LiveVariables) INITIALIZE_PASS_DEPENDENCY(LiveVariables)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_DEPENDENCY(SlotIndexes) INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
INITIALIZE_PASS_END(LiveIntervals, "liveintervals", INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
"Live Interval Analysis", false, false) "Live Interval Analysis", false, false)
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<bool> EnablePrecomputePhysRegs( static cl::opt<bool> EnablePrecomputePhysRegs(
"precompute-phys-liveness", cl::Hidden, "precompute-phys-liveness", cl::Hidden,
cl::desc("Eagerly compute live intervals for all physreg units.")); cl::desc("Eagerly compute live intervals for all physreg units."));
#else #else
static bool EnablePrecomputePhysRegs = false; static bool EnablePrecomputePhysRegs = false;
#endif // NDEBUG #endif // LLVM_NDEBUG
static cl::opt<bool> EnableSubRegLiveness( static cl::opt<bool> EnableSubRegLiveness(
"enable-subreg-liveness", cl::Hidden, cl::init(true), "enable-subreg-liveness", cl::Hidden, cl::init(true),
cl::desc("Enable subregister liveness tracking.")); cl::desc("Enable subregister liveness tracking."));
namespace llvm { namespace llvm {
cl::opt<bool> UseSegmentSetForPhysRegs( cl::opt<bool> UseSegmentSetForPhysRegs(
"use-segment-set-for-physregs", cl::Hidden, cl::init(true), "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Linesvoid LiveIntervals::print(raw_ostream &OS, const Module* ) const {
printInstrs(OS); printInstrs(OS);
} }
void LiveIntervals::printInstrs(raw_ostream &OS) const { void LiveIntervals::printInstrs(raw_ostream &OS) const {
OS << "********** MACHINEINSTRS **********\n"; OS << "********** MACHINEINSTRS **********\n";
MF->print(OS, Indexes); MF->print(OS, Indexes);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void LiveIntervals::dumpInstrs() const { void LiveIntervals::dumpInstrs() const {
printInstrs(dbgs()); printInstrs(dbgs());
} }
#endif #endif
LiveInterval* LiveIntervals::createInterval(unsigned reg) { LiveInterval* LiveIntervals::createInterval(unsigned reg) {
float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
llvm::huge_valf : 0.0F; llvm::huge_valf : 0.0F;
▲ Show 20 Lines • Show All 1,225 Lines • Show Last 20 Lines

lib/CodeGen/LiveIntervalUnion.cpp

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 LinesLiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
} }
for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) { for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
OS << " [" << SI.start() << ' ' << SI.stop() << "):" OS << " [" << SI.start() << ' ' << SI.stop() << "):"
<< PrintReg(SI.value()->reg, TRI); << PrintReg(SI.value()->reg, TRI);
} }
OS << '\n'; OS << '\n';
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify the live intervals in this union and add them to the visited set. // Verify the live intervals in this union and add them to the visited set.
void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) { void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI) for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
VisitedVRegs.set(SI.value()->reg); VisitedVRegs.set(SI.value()->reg);
} }
#endif //!NDEBUG #endif //!LLVM_NDEBUG
// Scan the vector of interfering virtual registers in this union. Assume it's // Scan the vector of interfering virtual registers in this union. Assume it's
// quite small. // quite small.
bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
SmallVectorImpl<LiveInterval*>::const_iterator I = SmallVectorImpl<LiveInterval*>::const_iterator I =
std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
return I != InterferingVRegs.end(); return I != InterferingVRegs.end();
} }
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

lib/CodeGen/LivePhysRegs.cpp

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Linesvoid LivePhysRegs::print(raw_ostream &OS) const {
for (const_iterator I = begin(), E = end(); I != E; ++I) for (const_iterator I = begin(), E = end(); I != E; ++I)
OS << " " << PrintReg(*I, TRI); OS << " " << PrintReg(*I, TRI);
OS << "\n"; OS << "\n";
} }
/// Dumps the currently live registers to the debug output. /// Dumps the currently live registers to the debug output.
void LivePhysRegs::dump() const { void LivePhysRegs::dump() const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
dbgs() << " " << *this; dbgs() << " " << *this;
#endif #endif
} }
/// Add live-in registers of basic block \p MBB to \p LiveRegs. /// Add live-in registers of basic block \p MBB to \p LiveRegs.
static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) { static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) {
for (unsigned Reg : make_range(MBB.livein_begin(), MBB.livein_end())) for (unsigned Reg : make_range(MBB.livein_begin(), MBB.livein_end()))
LiveRegs.addReg(Reg); LiveRegs.addReg(Reg);
Show All 34 Lines

lib/CodeGen/LiveRangeCalc.cpp

Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Linesbool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
// Remember if we have seen more than one value. // Remember if we have seen more than one value.
bool UniqueVNI = true; bool UniqueVNI = true;
VNInfo *TheVNI = nullptr; VNInfo *TheVNI = nullptr;
// Using Seen as a visited set, perform a BFS for all reaching defs. // Using Seen as a visited set, perform a BFS for all reaching defs.
for (unsigned i = 0; i != WorkList.size(); ++i) { for (unsigned i = 0; i != WorkList.size(); ++i) {
MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]); MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (MBB->pred_empty()) { if (MBB->pred_empty()) {
MBB->getParent()->verify(); MBB->getParent()->verify();
errs() << "Use of " << PrintReg(PhysReg) errs() << "Use of " << PrintReg(PhysReg)
<< " does not have a corresponding definition on every path:\n"; << " does not have a corresponding definition on every path:\n";
const MachineInstr *MI = Indexes->getInstructionFromIndex(Use); const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);
if (MI != nullptr) if (MI != nullptr)
errs() << Use << " " << *MI; errs() << Use << " " << *MI;
llvm_unreachable("Use not jointly dominated by defs."); llvm_unreachable("Use not jointly dominated by defs.");
▲ Show 20 Lines • Show All 187 Lines • Show Last 20 Lines

lib/CodeGen/LiveVariables.cpp

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const { LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
for (unsigned i = 0, e = Kills.size(); i != e; ++i) for (unsigned i = 0, e = Kills.size(); i != e; ++i)
if (Kills[i]->getParent() == MBB) if (Kills[i]->getParent() == MBB)
return Kills[i]; return Kills[i];
return nullptr; return nullptr;
} }
void LiveVariables::VarInfo::dump() const { void LiveVariables::VarInfo::dump() const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
dbgs() << " Alive in blocks: "; dbgs() << " Alive in blocks: ";
for (SparseBitVector<>::iterator I = AliveBlocks.begin(), for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
E = AliveBlocks.end(); I != E; ++I) E = AliveBlocks.end(); I != E; ++I)
dbgs() << *I << ", "; dbgs() << *I << ", ";
dbgs() << "\n Killed by:"; dbgs() << "\n Killed by:";
if (Kills.empty()) if (Kills.empty())
dbgs() << " No instructions.\n"; dbgs() << " No instructions.\n";
else { else {
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesvoid LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
// Check to see if this basic block is already a kill block. // Check to see if this basic block is already a kill block.
if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
// Yes, this register is killed in this basic block already. Increase the // Yes, this register is killed in this basic block already. Increase the
// live range by updating the kill instruction. // live range by updating the kill instruction.
VRInfo.Kills.back() = MI; VRInfo.Kills.back() = MI;
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!"); assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif #endif
// This situation can occur: // This situation can occur:
// //
// ,------. // ,------.
// | | // | |
▲ Show 20 Lines • Show All 503 Lines • ▼ Show 20 Lines for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI); VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
else else
VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI); VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
} }
// Check to make sure there are no unreachable blocks in the MC CFG for the // Check to make sure there are no unreachable blocks in the MC CFG for the
// function. If so, it is due to a bug in the instruction selector or some // function. If so, it is due to a bug in the instruction selector or some
// other part of the code generator if this happens. // other part of the code generator if this happens.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i) for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
assert(Visited.count(&*i) != 0 && "unreachable basic block found"); assert(Visited.count(&*i) != 0 && "unreachable basic block found");
#endif #endif
PhysRegDef.clear(); PhysRegDef.clear();
PhysRegUse.clear(); PhysRegUse.clear();
PHIVarInfo.clear(); PHIVarInfo.clear();
▲ Show 20 Lines • Show All 133 Lines • Show Last 20 Lines

lib/CodeGen/MachineBasicBlock.cpp

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Linesconst MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
if (succ_size() > 2) if (succ_size() > 2)
return nullptr; return nullptr;
for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I) for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
if ((*I)->isLandingPad()) if ((*I)->isLandingPad())
return *I; return *I;
return nullptr; return nullptr;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineBasicBlock::dump() const { void MachineBasicBlock::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
StringRef MachineBasicBlock::getName() const { StringRef MachineBasicBlock::getName() const {
if (const BasicBlock *LBB = getBasicBlock()) if (const BasicBlock *LBB = getBasicBlock())
return LBB->getName(); return LBB->getName();
▲ Show 20 Lines • Show All 971 Lines • Show Last 20 Lines

lib/CodeGen/MachineBlockFrequencyInfo.cpp

Show All 20 Lines
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/GraphWriter.h" #include "llvm/Support/GraphWriter.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "block-freq" #define DEBUG_TYPE "block-freq"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
enum GVDAGType { enum GVDAGType {
GVDT_None, GVDT_None,
GVDT_Fraction, GVDT_Fraction,
GVDT_Integer GVDT_Integer
}; };
static cl::opt<GVDAGType> static cl::opt<GVDAGType>
ViewMachineBlockFreqPropagationDAG("view-machine-block-freq-propagation-dags", ViewMachineBlockFreqPropagationDAG("view-machine-block-freq-propagation-dags",
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
bool MachineBlockFrequencyInfo::runOnMachineFunction(MachineFunction &F) { bool MachineBlockFrequencyInfo::runOnMachineFunction(MachineFunction &F) {
MachineBranchProbabilityInfo &MBPI = MachineBranchProbabilityInfo &MBPI =
getAnalysis<MachineBranchProbabilityInfo>(); getAnalysis<MachineBranchProbabilityInfo>();
MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
if (!MBFI) if (!MBFI)
MBFI.reset(new ImplType); MBFI.reset(new ImplType);
MBFI->calculate(F, MBPI, MLI); MBFI->calculate(F, MBPI, MLI);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (ViewMachineBlockFreqPropagationDAG != GVDT_None) { if (ViewMachineBlockFreqPropagationDAG != GVDT_None) {
view(); view();
} }
#endif #endif
return false; return false;
} }
void MachineBlockFrequencyInfo::releaseMemory() { MBFI.reset(); } void MachineBlockFrequencyInfo::releaseMemory() { MBFI.reset(); }
/// Pop up a ghostview window with the current block frequency propagation /// Pop up a ghostview window with the current block frequency propagation
/// rendered using dot. /// rendered using dot.
void MachineBlockFrequencyInfo::view() const { void MachineBlockFrequencyInfo::view() const {
// This code is only for debugging. // This code is only for debugging.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ViewGraph(const_cast<MachineBlockFrequencyInfo *>(this), ViewGraph(const_cast<MachineBlockFrequencyInfo *>(this),
"MachineBlockFrequencyDAGs"); "MachineBlockFrequencyDAGs");
#else #else
errs() << "MachineBlockFrequencyInfo::view is only available in debug builds " errs() << "MachineBlockFrequencyInfo::view is only available in debug builds "
"on systems with Graphviz or gv!\n"; "on systems with Graphviz or gv!\n";
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
BlockFrequency MachineBlockFrequencyInfo:: BlockFrequency MachineBlockFrequencyInfo::
getBlockFreq(const MachineBasicBlock *MBB) const { getBlockFreq(const MachineBasicBlock *MBB) const {
return MBFI ? MBFI->getBlockFreq(MBB) : 0; return MBFI ? MBFI->getBlockFreq(MBB) : 0;
} }
const MachineFunction *MachineBlockFrequencyInfo::getFunction() const { const MachineFunction *MachineBlockFrequencyInfo::getFunction() const {
Show All 18 Lines

lib/CodeGen/MachineBlockPlacement.cpp

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines void merge(MachineBasicBlock *BB, BlockChain *Chain) {
// chain structure. // chain structure.
for (MachineBasicBlock *ChainBB : *Chain) { for (MachineBasicBlock *ChainBB : *Chain) {
Blocks.push_back(ChainBB); Blocks.push_back(ChainBB);
assert(BlockToChain[ChainBB] == Chain && "Incoming blocks not in chain"); assert(BlockToChain[ChainBB] == Chain && "Incoming blocks not in chain");
BlockToChain[ChainBB] = this; BlockToChain[ChainBB] = this;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// \brief Dump the blocks in this chain. /// \brief Dump the blocks in this chain.
LLVM_DUMP_METHOD void dump() { LLVM_DUMP_METHOD void dump() {
for (MachineBasicBlock *MBB : *this) for (MachineBasicBlock *MBB : *this)
MBB->dump(); MBB->dump();
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
/// \brief Count of predecessors within the loop currently being processed. /// \brief Count of predecessors within the loop currently being processed.
/// ///
/// This count is updated at each loop we process to represent the number of /// This count is updated at each loop we process to represent the number of
/// in-loop predecessors of this chain. /// in-loop predecessors of this chain.
unsigned LoopPredecessors; unsigned LoopPredecessors;
}; };
} }
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 LinesINITIALIZE_PASS_BEGIN(MachineBlockPlacement, "block-placement",
"Branch Probability Basic Block Placement", false, false) "Branch Probability Basic Block Placement", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo) INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
INITIALIZE_PASS_END(MachineBlockPlacement, "block-placement", INITIALIZE_PASS_END(MachineBlockPlacement, "block-placement",
"Branch Probability Basic Block Placement", false, false) "Branch Probability Basic Block Placement", false, false)
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// \brief Helper to print the name of a MBB. /// \brief Helper to print the name of a MBB.
/// ///
/// Only used by debug logging. /// Only used by debug logging.
static std::string getBlockName(MachineBasicBlock *BB) { static std::string getBlockName(MachineBasicBlock *BB) {
std::string Result; std::string Result;
raw_string_ostream OS(Result); raw_string_ostream OS(Result);
OS << "BB#" << BB->getNumber(); OS << "BB#" << BB->getNumber();
OS << " (derived from LLVM BB '" << BB->getName() << "')"; OS << " (derived from LLVM BB '" << BB->getName() << "')";
▲ Show 20 Lines • Show All 667 Lines • ▼ Show 20 Lines for (MachineBasicBlock &MBB : F) {
if (Chain.LoopPredecessors == 0) if (Chain.LoopPredecessors == 0)
BlockWorkList.push_back(*Chain.begin()); BlockWorkList.push_back(*Chain.begin());
} }
BlockChain &FunctionChain = *BlockToChain[&F.front()]; BlockChain &FunctionChain = *BlockToChain[&F.front()];
buildChain(&F.front(), FunctionChain, BlockWorkList); buildChain(&F.front(), FunctionChain, BlockWorkList);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
typedef SmallPtrSet<MachineBasicBlock *, 16> FunctionBlockSetType; typedef SmallPtrSet<MachineBasicBlock *, 16> FunctionBlockSetType;
#endif #endif
DEBUG({ DEBUG({
// Crash at the end so we get all of the debugging output first. // Crash at the end so we get all of the debugging output first.
bool BadFunc = false; bool BadFunc = false;
FunctionBlockSetType FunctionBlockSet; FunctionBlockSetType FunctionBlockSet;
for (MachineBasicBlock &MBB : F) for (MachineBasicBlock &MBB : F)
FunctionBlockSet.insert(&MBB); FunctionBlockSet.insert(&MBB);
▲ Show 20 Lines • Show All 252 Lines • Show Last 20 Lines

lib/CodeGen/MachineFunction.cpp

Show First 20 Lines • Show All 328 Lines • ▼ Show 20 Lines
const char *MachineFunction::createExternalSymbolName(StringRef Name) { const char *MachineFunction::createExternalSymbolName(StringRef Name) {
char *Dest = Allocator.Allocate<char>(Name.size() + 1); char *Dest = Allocator.Allocate<char>(Name.size() + 1);
std::copy(Name.begin(), Name.end(), Dest); std::copy(Name.begin(), Name.end(), Dest);
Dest[Name.size()] = 0; Dest[Name.size()] = 0;
return Dest; return Dest;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineFunction::dump() const { void MachineFunction::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
StringRef MachineFunction::getName() const { StringRef MachineFunction::getName() const {
assert(getFunction() && "No function!"); assert(getFunction() && "No function!");
return getFunction()->getName(); return getFunction()->getName();
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines std::string getNodeLabel(const MachineBasicBlock *Node,
} }
return OutStr; return OutStr;
} }
}; };
} }
void MachineFunction::viewCFG() const void MachineFunction::viewCFG() const
{ {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ViewGraph(this, "mf" + getName()); ViewGraph(this, "mf" + getName());
#else #else
errs() << "MachineFunction::viewCFG is only available in debug builds on " errs() << "MachineFunction::viewCFG is only available in debug builds on "
<< "systems with Graphviz or gv!\n"; << "systems with Graphviz or gv!\n";
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
void MachineFunction::viewCFGOnly() const void MachineFunction::viewCFGOnly() const
{ {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ViewGraph(this, "mf" + getName(), true); ViewGraph(this, "mf" + getName(), true);
#else #else
errs() << "MachineFunction::viewCFGOnly is only available in debug builds on " errs() << "MachineFunction::viewCFGOnly is only available in debug builds on "
<< "systems with Graphviz or gv!\n"; << "systems with Graphviz or gv!\n";
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
/// Add the specified physical register as a live-in value and /// Add the specified physical register as a live-in value and
/// create a corresponding virtual register for it. /// create a corresponding virtual register for it.
unsigned MachineFunction::addLiveIn(unsigned PReg, unsigned MachineFunction::addLiveIn(unsigned PReg,
const TargetRegisterClass *RC) { const TargetRegisterClass *RC) {
MachineRegisterInfo &MRI = getRegInfo(); MachineRegisterInfo &MRI = getRegInfo();
unsigned VReg = MRI.getLiveInVirtReg(PReg); unsigned VReg = MRI.getLiveInVirtReg(PReg);
▲ Show 20 Lines • Show All 238 Lines • ▼ Show 20 Lines if (i < NumFixedObjects || SO.SPOffset != -1) {
else if (Off < 0) else if (Off < 0)
OS << Off; OS << Off;
OS << "]"; OS << "]";
} }
OS << "\n"; OS << "\n";
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineFrameInfo::dump(const MachineFunction &MF) const { void MachineFrameInfo::dump(const MachineFunction &MF) const {
print(MF, dbgs()); print(MF, dbgs());
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MachineJumpTableInfo implementation // MachineJumpTableInfo implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) {
OS << " jt#" << i << ": "; OS << " jt#" << i << ": ";
for (unsigned j = 0, f = JumpTables[i].MBBs.size(); j != f; ++j) for (unsigned j = 0, f = JumpTables[i].MBBs.size(); j != f; ++j)
OS << " BB#" << JumpTables[i].MBBs[j]->getNumber(); OS << " BB#" << JumpTables[i].MBBs[j]->getNumber();
} }
OS << '\n'; OS << '\n';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineJumpTableInfo::dump() const { print(dbgs()); } void MachineJumpTableInfo::dump() const { print(dbgs()); }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MachineConstantPool implementation // MachineConstantPool implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines if (Constants[i].isMachineConstantPoolEntry())
Constants[i].Val.MachineCPVal->print(OS); Constants[i].Val.MachineCPVal->print(OS);
else else
Constants[i].Val.ConstVal->printAsOperand(OS, /*PrintType=*/false); Constants[i].Val.ConstVal->printAsOperand(OS, /*PrintType=*/false);
OS << ", align=" << Constants[i].getAlignment(); OS << ", align=" << Constants[i].getAlignment();
OS << "\n"; OS << "\n";
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineConstantPool::dump() const { print(dbgs()); } void MachineConstantPool::dump() const { print(dbgs()); }
#endif #endif

lib/CodeGen/MachineInstr.cpp

Show First 20 Lines • Show All 726 Lines • ▼ Show 20 Linesvoid MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
bool isImpReg = Op.isReg() && Op.isImplicit(); bool isImpReg = Op.isReg() && Op.isImplicit();
if (!isImpReg && !isInlineAsm()) { if (!isImpReg && !isInlineAsm()) {
while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
--OpNo; --OpNo;
assert(!Operands[OpNo].isTied() && "Cannot move tied operands"); assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata; bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
// OpNo now points as the desired insertion point. Unless this is a variadic // OpNo now points as the desired insertion point. Unless this is a variadic
// instruction, only implicit regs are allowed beyond MCID->getNumOperands(). // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
// RegMask operands go between the explicit and implicit operands. // RegMask operands go between the explicit and implicit operands.
assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
OpNo < MCID->getNumOperands() || isMetaDataOp) && OpNo < MCID->getNumOperands() || isMetaDataOp) &&
"Trying to add an operand to a machine instr that is already done!"); "Trying to add an operand to a machine instr that is already done!");
#endif #endif
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
/// RemoveOperand - Erase an operand from an instruction, leaving it with one /// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with. /// fewer operand than it started with.
/// ///
void MachineInstr::RemoveOperand(unsigned OpNo) { void MachineInstr::RemoveOperand(unsigned OpNo) {
assert(OpNo < getNumOperands() && "Invalid operand number"); assert(OpNo < getNumOperands() && "Invalid operand number");
untieRegOperand(OpNo); untieRegOperand(OpNo);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Moving tied operands would break the ties. // Moving tied operands would break the ties.
for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i) for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
if (Operands[i].isReg()) if (Operands[i].isReg())
assert(!Operands[i].isTied() && "Cannot move tied operands"); assert(!Operands[i].isTied() && "Cannot move tied operands");
#endif #endif
MachineRegisterInfo *MRI = getRegInfo(); MachineRegisterInfo *MRI = getRegInfo();
if (MRI && Operands[OpNo].isReg()) if (MRI && Operands[OpNo].isReg())
▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
i != e; ++i) { i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
addOperand(MF, MO); addOperand(MF, MO);
} }
} }
void MachineInstr::dump() const { void MachineInstr::dump() const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
dbgs() << " " << *this; dbgs() << " " << *this;
#endif #endif
} }
void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const { void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
const Module *M = nullptr; const Module *M = nullptr;
if (const MachineBasicBlock *MBB = getParent()) if (const MachineBasicBlock *MBB = getParent())
if (const MachineFunction *MF = MBB->getParent()) if (const MachineFunction *MF = MBB->getParent())
▲ Show 20 Lines • Show All 455 Lines • Show Last 20 Lines

lib/CodeGen/MachineLoopInfo.cpp

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines while (contains(NextMBB)) {
BotMBB = NextMBB; BotMBB = NextMBB;
if (BotMBB == std::next(MachineFunction::iterator(BotMBB))) break; if (BotMBB == std::next(MachineFunction::iterator(BotMBB))) break;
NextMBB = std::next(MachineFunction::iterator(BotMBB)); NextMBB = std::next(MachineFunction::iterator(BotMBB));
} }
} }
return BotMBB; return BotMBB;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineLoop::dump() const { void MachineLoop::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif

lib/CodeGen/MachineRegionInfo.cpp

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesvoid MachineRegionInfoPass::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<PostDominatorTree>(); AU.addRequired<PostDominatorTree>();
AU.addRequired<DominanceFrontier>(); AU.addRequired<DominanceFrontier>();
} }
void MachineRegionInfoPass::print(raw_ostream &OS, const Module *) const { void MachineRegionInfoPass::print(raw_ostream &OS, const Module *) const {
RI.print(OS); RI.print(OS);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineRegionInfoPass::dump() const { void MachineRegionInfoPass::dump() const {
RI.dump(); RI.dump();
} }
#endif #endif
char MachineRegionInfoPass::ID = 0; char MachineRegionInfoPass::ID = 0;
INITIALIZE_PASS_BEGIN(MachineRegionInfoPass, "regions", INITIALIZE_PASS_BEGIN(MachineRegionInfoPass, "regions",
Show All 17 Lines

lib/CodeGen/MachineRegisterInfo.cpp

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 LinesMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
RegAllocHints.grow(Reg); RegAllocHints.grow(Reg);
if (TheDelegate) if (TheDelegate)
TheDelegate->MRI_NoteNewVirtualRegister(Reg); TheDelegate->MRI_NoteNewVirtualRegister(Reg);
return Reg; return Reg;
} }
/// clearVirtRegs - Remove all virtual registers (after physreg assignment). /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
void MachineRegisterInfo::clearVirtRegs() { void MachineRegisterInfo::clearVirtRegs() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i); unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (!VRegInfo[Reg].second) if (!VRegInfo[Reg].second)
continue; continue;
verifyUseList(Reg); verifyUseList(Reg);
llvm_unreachable("Remaining virtual register operands"); llvm_unreachable("Remaining virtual register operands");
} }
#endif #endif
VRegInfo.clear(); VRegInfo.clear();
for (auto &I : LiveIns) for (auto &I : LiveIns)
I.second = 0; I.second = 0;
} }
void MachineRegisterInfo::verifyUseList(unsigned Reg) const { void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool Valid = true; bool Valid = true;
for (MachineOperand &M : reg_operands(Reg)) { for (MachineOperand &M : reg_operands(Reg)) {
MachineOperand *MO = &M; MachineOperand *MO = &M;
MachineInstr *MI = MO->getParent(); MachineInstr *MI = MO->getParent();
if (!MI) { if (!MI) {
errs() << PrintReg(Reg, getTargetRegisterInfo()) errs() << PrintReg(Reg, getTargetRegisterInfo())
<< " use list MachineOperand " << MO << " use list MachineOperand " << MO
<< " has no parent instruction.\n"; << " has no parent instruction.\n";
Show All 21 Lines if (MO->getReg() != Reg) {
Valid = false; Valid = false;
} }
} }
assert(Valid && "Invalid use list"); assert(Valid && "Invalid use list");
#endif #endif
} }
void MachineRegisterInfo::verifyUseLists() const { void MachineRegisterInfo::verifyUseLists() const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
verifyUseList(TargetRegisterInfo::index2VirtReg(i)); verifyUseList(TargetRegisterInfo::index2VirtReg(i));
for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
verifyUseList(i); verifyUseList(i);
#endif #endif
} }
/// Add MO to the linked list of operands for its register. /// Add MO to the linked list of operands for its register.
▲ Show 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
unsigned MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const unsigned MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const
{ {
// Lane masks are only defined for vregs. // Lane masks are only defined for vregs.
assert(TargetRegisterInfo::isVirtualRegister(Reg)); assert(TargetRegisterInfo::isVirtualRegister(Reg));
const TargetRegisterClass &TRC = *getRegClass(Reg); const TargetRegisterClass &TRC = *getRegClass(Reg);
return TRC.getLaneMask(); return TRC.getLaneMask();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void MachineRegisterInfo::dumpUses(unsigned Reg) const { void MachineRegisterInfo::dumpUses(unsigned Reg) const {
for (MachineInstr &I : use_instructions(Reg)) for (MachineInstr &I : use_instructions(Reg))
I.dump(); I.dump();
} }
#endif #endif
void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

lib/CodeGen/MachineScheduler.cpp

Show All 39 Linescl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
cl::desc("Force top-down list scheduling")); cl::desc("Force top-down list scheduling"));
cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden, cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
cl::desc("Force bottom-up list scheduling")); cl::desc("Force bottom-up list scheduling"));
cl::opt<bool> cl::opt<bool>
DumpCriticalPathLength("misched-dcpl", cl::Hidden, DumpCriticalPathLength("misched-dcpl", cl::Hidden,
cl::desc("Print critical path length to stdout")); cl::desc("Print critical path length to stdout"));
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden, static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
cl::desc("Pop up a window to show MISched dags after they are processed")); cl::desc("Pop up a window to show MISched dags after they are processed"));
static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden, static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
cl::desc("Stop scheduling after N instructions"), cl::init(~0U)); cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden, static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
cl::desc("Only schedule this function")); cl::desc("Only schedule this function"));
static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden, static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
cl::desc("Only schedule this MBB#")); cl::desc("Only schedule this MBB#"));
#else #else
static bool ViewMISchedDAGs = false; static bool ViewMISchedDAGs = false;
#endif // NDEBUG #endif // LLVM_NDEBUG
static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden, static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
cl::desc("Enable register pressure scheduling."), cl::init(true)); cl::desc("Enable register pressure scheduling."), cl::init(true));
static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden, static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
cl::desc("Enable cyclic critical path analysis."), cl::init(true)); cl::desc("Enable cyclic critical path analysis."), cl::init(true));
static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden, static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
▲ Show 20 Lines • Show All 327 Lines • ▼ Show 20 Linesvoid MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
// //
// TODO: Visit blocks in global postorder or postorder within the bottom-up // TODO: Visit blocks in global postorder or postorder within the bottom-up
// loop tree. Then we can optionally compute global RegPressure. // loop tree. Then we can optionally compute global RegPressure.
for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end(); for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
MBB != MBBEnd; ++MBB) { MBB != MBBEnd; ++MBB) {
Scheduler.startBlock(MBB); Scheduler.startBlock(MBB);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName()) if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName())
continue; continue;
if (SchedOnlyBlock.getNumOccurrences() if (SchedOnlyBlock.getNumOccurrences()
&& (int)SchedOnlyBlock != MBB->getNumber()) && (int)SchedOnlyBlock != MBB->getNumber())
continue; continue;
#endif #endif
// Break the block into scheduling regions [I, RegionEnd), and schedule each // Break the block into scheduling regions [I, RegionEnd), and schedule each
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Linesvoid ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
SUnit *SuccSU = SuccEdge->getSUnit(); SUnit *SuccSU = SuccEdge->getSUnit();
if (SuccEdge->isWeak()) { if (SuccEdge->isWeak()) {
--SuccSU->WeakPredsLeft; --SuccSU->WeakPredsLeft;
if (SuccEdge->isCluster()) if (SuccEdge->isCluster())
NextClusterSucc = SuccSU; NextClusterSucc = SuccSU;
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (SuccSU->NumPredsLeft == 0) { if (SuccSU->NumPredsLeft == 0) {
dbgs() << "*** Scheduling failed! ***\n"; dbgs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this); SuccSU->dump(this);
dbgs() << " has been released too many times!\n"; dbgs() << " has been released too many times!\n";
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
#endif #endif
// SU->TopReadyCycle was set to CurrCycle when it was scheduled. However, // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
Show All 22 Linesvoid ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
SUnit *PredSU = PredEdge->getSUnit(); SUnit *PredSU = PredEdge->getSUnit();
if (PredEdge->isWeak()) { if (PredEdge->isWeak()) {
--PredSU->WeakSuccsLeft; --PredSU->WeakSuccsLeft;
if (PredEdge->isCluster()) if (PredEdge->isCluster())
NextClusterPred = PredSU; NextClusterPred = PredSU;
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (PredSU->NumSuccsLeft == 0) { if (PredSU->NumSuccsLeft == 0) {
dbgs() << "*** Scheduling failed! ***\n"; dbgs() << "*** Scheduling failed! ***\n";
PredSU->dump(this); PredSU->dump(this);
dbgs() << " has been released too many times!\n"; dbgs() << " has been released too many times!\n";
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
#endif #endif
// SU->BotReadyCycle was set to CurrCycle when it was scheduled. However, // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines if (LIS)
LIS->handleMove(MI, /*UpdateFlags=*/true); LIS->handleMove(MI, /*UpdateFlags=*/true);
// Recede RegionBegin if an instruction moves above the first. // Recede RegionBegin if an instruction moves above the first.
if (RegionBegin == InsertPos) if (RegionBegin == InsertPos)
RegionBegin = MI; RegionBegin = MI;
} }
bool ScheduleDAGMI::checkSchedLimit() { bool ScheduleDAGMI::checkSchedLimit() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) { if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
CurrentTop = CurrentBottom; CurrentTop = CurrentBottom;
return false; return false;
} }
++NumInstrsScheduled; ++NumInstrsScheduled;
#endif #endif
return true; return true;
} }
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
BB->splice(++OrigPrevMI, BB, DbgValue); BB->splice(++OrigPrevMI, BB, DbgValue);
if (OrigPrevMI == std::prev(RegionEnd)) if (OrigPrevMI == std::prev(RegionEnd))
RegionEnd = DbgValue; RegionEnd = DbgValue;
} }
DbgValues.clear(); DbgValues.clear();
FirstDbgValue = nullptr; FirstDbgValue = nullptr;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void ScheduleDAGMI::dumpSchedule() const { void ScheduleDAGMI::dumpSchedule() const {
for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) { for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
if (SUnit *SU = getSUnit(&(*MI))) if (SUnit *SU = getSUnit(&(*MI)))
SU->dump(this); SU->dump(this);
else else
dbgs() << "Missing SUnit\n"; dbgs() << "Missing SUnit\n";
} }
} }
▲ Show 20 Lines • Show All 791 Lines • ▼ Show 20 Linesvoid SchedBoundary::reset() {
MinReadyCycle = UINT_MAX; MinReadyCycle = UINT_MAX;
ExpectedLatency = 0; ExpectedLatency = 0;
DependentLatency = 0; DependentLatency = 0;
RetiredMOps = 0; RetiredMOps = 0;
MaxExecutedResCount = 0; MaxExecutedResCount = 0;
ZoneCritResIdx = 0; ZoneCritResIdx = 0;
IsResourceLimited = false; IsResourceLimited = false;
ReservedCycles.clear(); ReservedCycles.clear();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Track the maximum number of stall cycles that could arise either from the // Track the maximum number of stall cycles that could arise either from the
// latency of a DAG edge or the number of cycles that a processor resource is // latency of a DAG edge or the number of cycles that a processor resource is
// reserved (SchedBoundary::ReservedCycles). // reserved (SchedBoundary::ReservedCycles).
MaxObservedStall = 0; MaxObservedStall = 0;
#endif #endif
// Reserve a zero-count for invalid CritResIdx. // Reserve a zero-count for invalid CritResIdx.
ExecutedResCounts.resize(1); ExecutedResCounts.resize(1);
assert(!ExecutedResCounts[0] && "nonzero count for bad resource"); assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Linesbool SchedBoundary::checkHazard(SUnit *SU) {
} }
if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) { if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
const MCSchedClassDesc *SC = DAG->getSchedClass(SU); const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
for (TargetSchedModel::ProcResIter for (TargetSchedModel::ProcResIter
PI = SchedModel->getWriteProcResBegin(SC), PI = SchedModel->getWriteProcResBegin(SC),
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles); unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles);
if (NRCycle > CurrCycle) { if (NRCycle > CurrCycle) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
MaxObservedStall = std::max(PI->Cycles, MaxObservedStall); MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
#endif #endif
DEBUG(dbgs() << " SU(" << SU->NodeNum << ") " DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
<< SchedModel->getResourceName(PI->ProcResourceIdx) << SchedModel->getResourceName(PI->ProcResourceIdx)
<< "=" << NRCycle << "c\n"); << "=" << NRCycle << "c\n");
return true; return true;
} }
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
<< " " << SchedModel->getResourceName(OtherCritIdx) << "\n"); << " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
} }
return OtherCritCount; return OtherCritCount;
} }
void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) { void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
assert(SU->getInstr() && "Scheduled SUnit must have instr"); assert(SU->getInstr() && "Scheduled SUnit must have instr");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// ReadyCycle was been bumped up to the CurrCycle when this node was // ReadyCycle was been bumped up to the CurrCycle when this node was
// scheduled, but CurrCycle may have been eagerly advanced immediately after // scheduled, but CurrCycle may have been eagerly advanced immediately after
// scheduling, so may now be greater than ReadyCycle. // scheduling, so may now be greater than ReadyCycle.
if (ReadyCycle > CurrCycle) if (ReadyCycle > CurrCycle)
MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall); MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall);
#endif #endif
if (ReadyCycle < MinReadyCycle) if (ReadyCycle < MinReadyCycle)
▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Lines// "permanent hazard");
bumpCycle(CurrCycle + 1); bumpCycle(CurrCycle + 1);
releasePending(); releasePending();
} }
if (Available.size() == 1) if (Available.size() == 1)
return *Available.begin(); return *Available.begin();
return nullptr; return nullptr;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// This is useful information to dump after bumpNode. // This is useful information to dump after bumpNode.
// Note that the Queue contents are more useful before pickNodeFromQueue. // Note that the Queue contents are more useful before pickNodeFromQueue.
void SchedBoundary::dumpScheduledState() { void SchedBoundary::dumpScheduledState() {
unsigned ResFactor; unsigned ResFactor;
unsigned ResCount; unsigned ResCount;
if (ZoneCritResIdx) { if (ZoneCritResIdx) {
ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx); ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
ResCount = getResourceCount(ZoneCritResIdx); ResCount = getResourceCount(ZoneCritResIdx);
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Linesvoid GenericSchedulerBase::setPolicy(CandPolicy &Policy,
if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx) if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
Policy.ReduceResIdx = CurrZone.getZoneCritResIdx(); Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
if (OtherResLimited) if (OtherResLimited)
Policy.DemandResIdx = OtherCritIdx; Policy.DemandResIdx = OtherCritIdx;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const char *GenericSchedulerBase::getReasonStr( const char *GenericSchedulerBase::getReasonStr(
GenericSchedulerBase::CandReason Reason) { GenericSchedulerBase::CandReason Reason) {
switch (Reason) { switch (Reason) {
case NoCand: return "NOCAND "; case NoCand: return "NOCAND ";
case PhysRegCopy: return "PREG-COPY"; case PhysRegCopy: return "PREG-COPY";
case RegExcess: return "REG-EXCESS"; case RegExcess: return "REG-EXCESS";
case RegCritical: return "REG-CRIT "; case RegCritical: return "REG-CRIT ";
case Stall: return "STALL "; case Stall: return "STALL ";
▲ Show 20 Lines • Show All 910 Lines • ▼ Show 20 Linesstatic MachineSchedRegistry ILPMaxRegistry(
"ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler); "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
static MachineSchedRegistry ILPMinRegistry( static MachineSchedRegistry ILPMinRegistry(
"ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler); "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Machine Instruction Shuffler for Correctness Testing // Machine Instruction Shuffler for Correctness Testing
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef NDEBUG #ifndef LLVM_NDEBUG
namespace { namespace {
/// Apply a less-than relation on the node order, which corresponds to the /// Apply a less-than relation on the node order, which corresponds to the
/// instruction order prior to scheduling. IsReverse implements greater-than. /// instruction order prior to scheduling. IsReverse implements greater-than.
template<bool IsReverse> template<bool IsReverse>
struct SUnitOrder { struct SUnitOrder {
bool operator()(SUnit *A, SUnit *B) const { bool operator()(SUnit *A, SUnit *B) const {
if (IsReverse) if (IsReverse)
return A->NodeNum > B->NodeNum; return A->NodeNum > B->NodeNum;
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesstatic ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
bool TopDown = !ForceBottomUp; bool TopDown = !ForceBottomUp;
assert((TopDown || !ForceTopDown) && assert((TopDown || !ForceTopDown) &&
"-misched-topdown incompatible with -misched-bottomup"); "-misched-topdown incompatible with -misched-bottomup");
return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown)); return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
} }
static MachineSchedRegistry ShufflerRegistry( static MachineSchedRegistry ShufflerRegistry(
"shuffle", "Shuffle machine instructions alternating directions", "shuffle", "Shuffle machine instructions alternating directions",
createInstructionShuffler); createInstructionShuffler);
#endif // !NDEBUG #endif // !LLVM_NDEBUG
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GraphWriter support for ScheduleDAGMILive. // GraphWriter support for ScheduleDAGMILive.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef NDEBUG #ifndef LLVM_NDEBUG
namespace llvm { namespace llvm {
template<> struct GraphTraits< template<> struct GraphTraits<
ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {}; ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
template<> template<>
struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits { struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines if (DFS) {
Str += ",style=filled,fillcolor=\"#"; Str += ",style=filled,fillcolor=\"#";
Str += DOT::getColorString(DFS->getSubtreeID(N)); Str += DOT::getColorString(DFS->getSubtreeID(N));
Str += '"'; Str += '"';
} }
return Str; return Str;
} }
}; };
} // namespace llvm } // namespace llvm
#endif // NDEBUG #endif // LLVM_NDEBUG
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
/// rendered using 'dot'. /// rendered using 'dot'.
/// ///
void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) { void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ViewGraph(this, Name, false, Title); ViewGraph(this, Name, false, Title);
#else #else
errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on " errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
<< "systems with Graphviz or gv!\n"; << "systems with Graphviz or gv!\n";
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
/// Out-of-line implementation with no arguments is handy for gdb. /// Out-of-line implementation with no arguments is handy for gdb.
void ScheduleDAGMI::viewGraph() { void ScheduleDAGMI::viewGraph() {
viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName()); viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());
} }

lib/CodeGen/MachineTraceMetrics.cpp

Show First 20 Lines • Show All 382 Lines • ▼ Show 20 Linesvoid MachineTraceMetrics::invalidate(const MachineBasicBlock *MBB) {
for (unsigned i = 0; i != TS_NumStrategies; ++i) for (unsigned i = 0; i != TS_NumStrategies; ++i)
if (Ensembles[i]) if (Ensembles[i])
Ensembles[i]->invalidate(MBB); Ensembles[i]->invalidate(MBB);
} }
void MachineTraceMetrics::verifyAnalysis() const { void MachineTraceMetrics::verifyAnalysis() const {
if (!MF) if (!MF)
return; return;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(BlockInfo.size() == MF->getNumBlockIDs() && "Outdated BlockInfo size"); assert(BlockInfo.size() == MF->getNumBlockIDs() && "Outdated BlockInfo size");
for (unsigned i = 0; i != TS_NumStrategies; ++i) for (unsigned i = 0; i != TS_NumStrategies; ++i)
if (Ensembles[i]) if (Ensembles[i])
Ensembles[i]->verify(); Ensembles[i]->verify();
#endif #endif
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 LinesMachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) {
// invalidated, but their instructions will stay the same, so there is no // invalidated, but their instructions will stay the same, so there is no
// need to erase the Cycle entries. They will be overwritten when we // need to erase the Cycle entries. They will be overwritten when we
// recompute. // recompute.
for (const auto &I : *BadMBB) for (const auto &I : *BadMBB)
Cycles.erase(&I); Cycles.erase(&I);
} }
void MachineTraceMetrics::Ensemble::verify() const { void MachineTraceMetrics::Ensemble::verify() const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(BlockInfo.size() == MTM.MF->getNumBlockIDs() && assert(BlockInfo.size() == MTM.MF->getNumBlockIDs() &&
"Outdated BlockInfo size"); "Outdated BlockInfo size");
for (unsigned Num = 0, e = BlockInfo.size(); Num != e; ++Num) { for (unsigned Num = 0, e = BlockInfo.size(); Num != e; ++Num) {
const TraceBlockInfo &TBI = BlockInfo[Num]; const TraceBlockInfo &TBI = BlockInfo[Num];
if (TBI.hasValidDepth() && TBI.Pred) { if (TBI.hasValidDepth() && TBI.Pred) {
const MachineBasicBlock *MBB = MTM.MF->getBlockNumbered(Num); const MachineBasicBlock *MBB = MTM.MF->getBlockNumbered(Num);
assert(MBB->isPredecessor(TBI.Pred) && "CFG doesn't match trace"); assert(MBB->isPredecessor(TBI.Pred) && "CFG doesn't match trace");
assert(BlockInfo[TBI.Pred->getNumber()].hasValidDepth() && assert(BlockInfo[TBI.Pred->getNumber()].hasValidDepth() &&
▲ Show 20 Lines • Show All 757 Lines • Show Last 20 Lines

lib/CodeGen/PostRASchedulerList.cpp

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Linesvoid SchedulePostRATDList::exitRegion() {
DEBUG({ DEBUG({
dbgs() << "*** Final schedule ***\n"; dbgs() << "*** Final schedule ***\n";
dumpSchedule(); dumpSchedule();
dbgs() << '\n'; dbgs() << '\n';
}); });
ScheduleDAGInstrs::exitRegion(); ScheduleDAGInstrs::exitRegion();
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dumpSchedule - dump the scheduled Sequence. /// dumpSchedule - dump the scheduled Sequence.
void SchedulePostRATDList::dumpSchedule() const { void SchedulePostRATDList::dumpSchedule() const {
for (unsigned i = 0, e = Sequence.size(); i != e; i++) { for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) if (SUnit *SU = Sequence[i])
SU->dump(this); SU->dump(this);
else else
dbgs() << "**** NOOP ****\n"; dbgs() << "**** NOOP ****\n";
} }
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesbool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
DEBUG(dbgs() << "PostRAScheduler\n"); DEBUG(dbgs() << "PostRAScheduler\n");
SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
CriticalPathRCs); CriticalPathRCs);
// Loop over all of the basic blocks // Loop over all of the basic blocks
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) { MBB != MBBe; ++MBB) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
if (DebugDiv > 0) { if (DebugDiv > 0) {
static int bbcnt = 0; static int bbcnt = 0;
if (bbcnt++ % DebugDiv != DebugMod) if (bbcnt++ % DebugDiv != DebugMod)
continue; continue;
dbgs() << "*** DEBUG scheduling " << Fn.getName() dbgs() << "*** DEBUG scheduling " << Fn.getName()
<< ":BB#" << MBB->getNumber() << " ***\n"; << ":BB#" << MBB->getNumber() << " ***\n";
} }
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
/// the PendingQueue if the count reaches zero. /// the PendingQueue if the count reaches zero.
void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
SUnit *SuccSU = SuccEdge->getSUnit(); SUnit *SuccSU = SuccEdge->getSUnit();
if (SuccEdge->isWeak()) { if (SuccEdge->isWeak()) {
--SuccSU->WeakPredsLeft; --SuccSU->WeakPredsLeft;
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (SuccSU->NumPredsLeft == 0) { if (SuccSU->NumPredsLeft == 0) {
dbgs() << "*** Scheduling failed! ***\n"; dbgs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this); SuccSU->dump(this);
dbgs() << " has been released too many times!\n"; dbgs() << " has been released too many times!\n";
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
#endif #endif
--SuccSU->NumPredsLeft; --SuccSU->NumPredsLeft;
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines if (FoundSUnit) {
emitNoop(CurCycle); emitNoop(CurCycle);
} }
++CurCycle; ++CurCycle;
CycleHasInsts = false; CycleHasInsts = false;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false); unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false);
unsigned Noops = 0; unsigned Noops = 0;
for (unsigned i = 0, e = Sequence.size(); i != e; ++i) for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
if (!Sequence[i]) if (!Sequence[i])
++Noops; ++Noops;
assert(Sequence.size() - Noops == ScheduledNodes && assert(Sequence.size() - Noops == ScheduledNodes &&
"The number of nodes scheduled doesn't match the expected number!"); "The number of nodes scheduled doesn't match the expected number!");
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
// EmitSchedule - Emit the machine code in scheduled order. // EmitSchedule - Emit the machine code in scheduled order.
void SchedulePostRATDList::EmitSchedule() { void SchedulePostRATDList::EmitSchedule() {
RegionBegin = RegionEnd; RegionBegin = RegionEnd;
// If first instruction was a DBG_VALUE then put it back. // If first instruction was a DBG_VALUE then put it back.
if (FirstDbgValue) if (FirstDbgValue)
Show All 27 Lines

lib/CodeGen/RegAllocBase.cpp

Show All 16 Lines
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveRangeEdit.h" #include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveRegMatrix.h" #include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h" #include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
#include "llvm/ADT/SparseBitVector.h" #include "llvm/ADT/SparseBitVector.h"
#endif #endif
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Timer.h" #include "llvm/Support/Timer.h"
▲ Show 20 Lines • Show All 122 Lines • Show Last 20 Lines

lib/CodeGen/RegAllocGreedy.cpp

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines enum CutOffStage {
CO_Depth = 1, CO_Depth = 1,
// lcr-max-interf cutoff encountered // lcr-max-interf cutoff encountered
CO_Interf = 2 CO_Interf = 2
}; };
uint8_t CutOffInfo; uint8_t CutOffInfo;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static const char *const StageName[]; static const char *const StageName[];
#endif #endif
// RegInfo - Keep additional information about each live range. // RegInfo - Keep additional information about each live range.
struct RegInfo { struct RegInfo {
LiveRangeStage Stage; LiveRangeStage Stage;
// Cascade - Eviction loop prevention. See canEvictInterference(). // Cascade - Eviction loop prevention. See canEvictInterference().
▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Linesprivate:
void collectHintInfo(unsigned, HintsInfo &); void collectHintInfo(unsigned, HintsInfo &);
bool isUnusedCalleeSavedReg(unsigned PhysReg) const; bool isUnusedCalleeSavedReg(unsigned PhysReg) const;
}; };
} // end anonymous namespace } // end anonymous namespace
char RAGreedy::ID = 0; char RAGreedy::ID = 0;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const char *const RAGreedy::StageName[] = { const char *const RAGreedy::StageName[] = {
"RS_New", "RS_New",
"RS_Assign", "RS_Assign",
"RS_Split", "RS_Split",
"RS_Split2", "RS_Split2",
"RS_Spill", "RS_Spill",
"RS_Memory", "RS_Memory",
"RS_Done" "RS_Done"
▲ Show 20 Lines • Show All 601 Lines • ▼ Show 20 Linesvoid RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
SpillPlacer->addLinks(makeArrayRef(TBS, T)); SpillPlacer->addLinks(makeArrayRef(TBS, T));
} }
void RAGreedy::growRegion(GlobalSplitCandidate &Cand) { void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
// Keep track of through blocks that have not been added to SpillPlacer. // Keep track of through blocks that have not been added to SpillPlacer.
BitVector Todo = SA->getThroughBlocks(); BitVector Todo = SA->getThroughBlocks();
SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks; SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
unsigned AddedTo = 0; unsigned AddedTo = 0;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned Visited = 0; unsigned Visited = 0;
#endif #endif
for (;;) { for (;;) {
ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive(); ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
// Find new through blocks in the periphery of PrefRegBundles. // Find new through blocks in the periphery of PrefRegBundles.
for (int i = 0, e = NewBundles.size(); i != e; ++i) { for (int i = 0, e = NewBundles.size(); i != e; ++i) {
unsigned Bundle = NewBundles[i]; unsigned Bundle = NewBundles[i];
// Look at all blocks connected to Bundle in the full graph. // Look at all blocks connected to Bundle in the full graph.
ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle); ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end(); for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
I != E; ++I) { I != E; ++I) {
unsigned Block = *I; unsigned Block = *I;
if (!Todo.test(Block)) if (!Todo.test(Block))
continue; continue;
Todo.reset(Block); Todo.reset(Block);
// This is a new through block. Add it to SpillPlacer later. // This is a new through block. Add it to SpillPlacer later.
ActiveBlocks.push_back(Block); ActiveBlocks.push_back(Block);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
++Visited; ++Visited;
#endif #endif
} }
} }
// Any new blocks to add? // Any new blocks to add?
if (ActiveBlocks.size() == AddedTo) if (ActiveBlocks.size() == AddedTo)
break; break;
▲ Show 20 Lines • Show All 1,538 Lines • Show Last 20 Lines

lib/CodeGen/RegAllocPBQP.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
RegisterPBQPRepAlloc("pbqp", "PBQP register allocator", RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
createDefaultPBQPRegisterAllocator); createDefaultPBQPRegisterAllocator);
static cl::opt<bool> static cl::opt<bool>
PBQPCoalescing("pbqp-coalescing", PBQPCoalescing("pbqp-coalescing",
cl::desc("Attempt coalescing during PBQP register allocation."), cl::desc("Attempt coalescing during PBQP register allocation."),
cl::init(false), cl::Hidden); cl::init(false), cl::Hidden);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<bool> static cl::opt<bool>
PBQPDumpGraphs("pbqp-dump-graphs", PBQPDumpGraphs("pbqp-dump-graphs",
cl::desc("Dump graphs for each function/round in the compilation unit."), cl::desc("Dump graphs for each function/round in the compilation unit."),
cl::init(false), cl::Hidden); cl::init(false), cl::Hidden);
#endif #endif
namespace { namespace {
▲ Show 20 Lines • Show All 660 Lines • ▼ Show 20 Linesbool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
// * Map the solution back to a register allocation // * Map the solution back to a register allocation
// * Spill if necessary // * Spill if necessary
// //
// This process is continued till no more spills are generated. // This process is continued till no more spills are generated.
// Find the vreg intervals in need of allocation. // Find the vreg intervals in need of allocation.
findVRegIntervalsToAlloc(MF, LIS); findVRegIntervalsToAlloc(MF, LIS);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const Function &F = *MF.getFunction(); const Function &F = *MF.getFunction();
std::string FullyQualifiedName = std::string FullyQualifiedName =
F.getParent()->getModuleIdentifier() + "." + F.getName().str(); F.getParent()->getModuleIdentifier() + "." + F.getName().str();
#endif #endif
// If there are non-empty intervals allocate them using pbqp. // If there are non-empty intervals allocate them using pbqp.
if (!VRegsToAlloc.empty()) { if (!VRegsToAlloc.empty()) {
Show All 11 Lines if (!VRegsToAlloc.empty()) {
while (!PBQPAllocComplete) { while (!PBQPAllocComplete) {
DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n"); DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI)); PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
initializeGraph(G, VRM, *VRegSpiller); initializeGraph(G, VRM, *VRegSpiller);
ConstraintsRoot->apply(G); ConstraintsRoot->apply(G);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (PBQPDumpGraphs) { if (PBQPDumpGraphs) {
std::ostringstream RS; std::ostringstream RS;
RS << Round; RS << Round;
std::string GraphFileName = FullyQualifiedName + "." + RS.str() + std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
".pbqpgraph"; ".pbqpgraph";
std::error_code EC; std::error_code EC;
raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text); raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
DEBUG(dbgs() << "Dumping graph for round " << Round << " to \"" DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

lib/CodeGen/RegisterCoalescer.cpp

Show First 20 Lines • Show All 2,982 Lines • ▼ Show 20 Lines if (MRI->recomputeRegClass(Reg)) {
<< TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
LiveInterval &LI = LIS->getInterval(Reg); LiveInterval &LI = LIS->getInterval(Reg);
unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg); unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
if (MaxMask == 0) { if (MaxMask == 0) {
// If the inflated register class does not support subregisters anymore // If the inflated register class does not support subregisters anymore
// remove the subranges. // remove the subranges.
LI.clearSubRanges(); LI.clearSubRanges();
} else { } else {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If subranges are still supported, then the same subregs should still // If subranges are still supported, then the same subregs should still
// be supported. // be supported.
for (LiveInterval::SubRange &S : LI.subranges()) { for (LiveInterval::SubRange &S : LI.subranges()) {
assert ((S.LaneMask & ~MaxMask) == 0); assert ((S.LaneMask & ~MaxMask) == 0);
} }
#endif #endif
} }
++NumInflated; ++NumInflated;
Show All 12 Lines

lib/CodeGen/RegisterPressure.cpp

Show First 20 Lines • Show All 783 Lines • ▼ Show 20 Lines computeMaxPressureDelta(SavedMaxPressure, P.MaxSetPressure, CriticalPSets,
MaxPressureLimit, Delta); MaxPressureLimit, Delta);
assert(Delta.CriticalMax.getUnitInc() >= 0 && assert(Delta.CriticalMax.getUnitInc() >= 0 &&
Delta.CurrentMax.getUnitInc() >= 0 && "cannot decrease max pressure"); Delta.CurrentMax.getUnitInc() >= 0 && "cannot decrease max pressure");
// Restore the tracker's state. // Restore the tracker's state.
P.MaxSetPressure.swap(SavedMaxPressure); P.MaxSetPressure.swap(SavedMaxPressure);
CurrSetPressure.swap(SavedPressure); CurrSetPressure.swap(SavedPressure);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (!PDiff) if (!PDiff)
return; return;
// Check if the alternate algorithm yields the same result. // Check if the alternate algorithm yields the same result.
RegPressureDelta Delta2; RegPressureDelta Delta2;
getUpwardPressureDelta(MI, *PDiff, Delta2, CriticalPSets, MaxPressureLimit); getUpwardPressureDelta(MI, *PDiff, Delta2, CriticalPSets, MaxPressureLimit);
if (Delta != Delta2) { if (Delta != Delta2) {
dbgs() << "PDiff: "; dbgs() << "PDiff: ";
▲ Show 20 Lines • Show All 222 Lines • Show Last 20 Lines

lib/CodeGen/RegisterScavenging.cpp

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Linesvoid RegScavenger::forward() {
} }
if (MI->isDebugValue()) if (MI->isDebugValue())
return; return;
determineKillsAndDefs(); determineKillsAndDefs();
// Verify uses and defs. // Verify uses and defs.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg)) if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg))
continue; continue;
if (MO.isUse()) { if (MO.isUse()) {
Show All 34 Lines#if 0
// FIXME: Enable this once we've figured out how to correctly transfer // FIXME: Enable this once we've figured out how to correctly transfer
// implicit kills during codegen passes like the coalescer. // implicit kills during codegen passes like the coalescer.
assert((KillRegs.test(Reg) || isUnused(Reg) || assert((KillRegs.test(Reg) || isUnused(Reg) ||
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!"); "Re-defining a live register!");
#endif #endif
} }
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
// Commit the changes. // Commit the changes.
setUnused(KillRegUnits); setUnused(KillRegUnits);
setUsed(DefRegUnits); setUsed(DefRegUnits);
} }
bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const { bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
if (includeReserved && isReserved(Reg)) if (includeReserved && isReserved(Reg))
▲ Show 20 Lines • Show All 189 Lines • Show Last 20 Lines

lib/CodeGen/ScheduleDAG.cpp

Show All 21 Lines
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Target/TargetSubtargetInfo.h"
#include <climits> #include <climits>
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "pre-RA-sched" #define DEBUG_TYPE "pre-RA-sched"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<bool> StressSchedOpt( static cl::opt<bool> StressSchedOpt(
"stress-sched", cl::Hidden, cl::init(false), "stress-sched", cl::Hidden, cl::init(false),
cl::desc("Stress test instruction scheduling")); cl::desc("Stress test instruction scheduling"));
#endif #endif
void SchedulingPriorityQueue::anchor() { } void SchedulingPriorityQueue::anchor() { }
ScheduleDAG::ScheduleDAG(MachineFunction &mf) ScheduleDAG::ScheduleDAG(MachineFunction &mf)
: TM(mf.getTarget()), TII(mf.getSubtarget().getInstrInfo()), : TM(mf.getTarget()), TII(mf.getSubtarget().getInstrInfo()),
TRI(mf.getSubtarget().getRegisterInfo()), MF(mf), TRI(mf.getSubtarget().getRegisterInfo()), MF(mf),
MRI(mf.getRegInfo()), EntrySU(), ExitSU() { MRI(mf.getRegInfo()), EntrySU(), ExitSU() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
StressSched = StressSchedOpt; StressSched = StressSchedOpt;
#endif #endif
} }
ScheduleDAG::~ScheduleDAG() {} ScheduleDAG::~ScheduleDAG() {}
/// Clear the DAG state (e.g. between scheduling regions). /// Clear the DAG state (e.g. between scheduling regions).
void ScheduleDAG::clearDAG() { void ScheduleDAG::clearDAG() {
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines for (SUnit::pred_iterator I = std::next(BestI), E = Preds.end(); I != E;
++I) { ++I) {
if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth) if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth)
BestI = I; BestI = I;
} }
if (BestI != Preds.begin()) if (BestI != Preds.begin())
std::swap(*Preds.begin(), *BestI); std::swap(*Preds.begin(), *BestI);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
/// a group of nodes flagged together. /// a group of nodes flagged together.
void SUnit::dump(const ScheduleDAG *G) const { void SUnit::dump(const ScheduleDAG *G) const {
dbgs() << "SU(" << NodeNum << "): "; dbgs() << "SU(" << NodeNum << "): ";
G->dumpNode(this); G->dumpNode(this);
} }
void SUnit::dumpAll(const ScheduleDAG *G) const { void SUnit::dumpAll(const ScheduleDAG *G) const {
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI); dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
dbgs() << "\n"; dbgs() << "\n";
} }
} }
dbgs() << "\n"; dbgs() << "\n";
} }
#endif #endif
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// VerifyScheduledDAG - Verify that all SUnits were scheduled and that /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
/// their state is consistent. Return the number of scheduled nodes. /// their state is consistent. Return the number of scheduled nodes.
/// ///
unsigned ScheduleDAG::VerifyScheduledDAG(bool isBottomUp) { unsigned ScheduleDAG::VerifyScheduledDAG(bool isBottomUp) {
bool AnyNotSched = false; bool AnyNotSched = false;
unsigned DeadNodes = 0; unsigned DeadNodes = 0;
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
if (!SUnits[i].isScheduled) { if (!SUnits[i].isScheduled) {
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
// If all dependencies of the node are processed already, // If all dependencies of the node are processed already,
// then the node can be computed now. // then the node can be computed now.
WorkList.push_back(SU); WorkList.push_back(SU);
} }
} }
Visited.resize(DAGSize); Visited.resize(DAGSize);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Check correctness of the ordering // Check correctness of the ordering
for (unsigned i = 0, e = DAGSize; i != e; ++i) { for (unsigned i = 0, e = DAGSize; i != e; ++i) {
SUnit *SU = &SUnits[i]; SUnit *SU = &SUnits[i];
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) { I != E; ++I) {
assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] && assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] &&
"Wrong topological sorting"); "Wrong topological sorting");
} }
▲ Show 20 Lines • Show All 130 Lines • Show Last 20 Lines

lib/CodeGen/ScheduleDAGInstrs.cpp

Show First 20 Lines • Show All 1,257 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs) SubRegs.isValid(); ++SubRegs)
LiveRegs.set(*SubRegs); LiveRegs.set(*SubRegs);
} }
} }
} }
void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
SU->getInstr()->dump(); SU->getInstr()->dump();
#endif #endif
} }
std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
std::string s; std::string s;
raw_string_ostream oss(s); raw_string_ostream oss(s);
if (SU == &EntrySU) if (SU == &EntrySU)
▲ Show 20 Lines • Show All 331 Lines • Show Last 20 Lines

lib/CodeGen/ScheduleDAGPrinter.cpp

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesstd::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
return G->getGraphNodeLabel(SU); return G->getGraphNodeLabel(SU);
} }
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
/// rendered using 'dot'. /// rendered using 'dot'.
/// ///
void ScheduleDAG::viewGraph(const Twine &Name, const Twine &Title) { void ScheduleDAG::viewGraph(const Twine &Name, const Twine &Title) {
// This code is only for debugging! // This code is only for debugging!
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ViewGraph(this, Name, false, Title); ViewGraph(this, Name, false, Title);
#else #else
errs() << "ScheduleDAG::viewGraph is only available in debug builds on " errs() << "ScheduleDAG::viewGraph is only available in debug builds on "
<< "systems with Graphviz or gv!\n"; << "systems with Graphviz or gv!\n";
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
/// Out-of-line implementation with no arguments is handy for gdb. /// Out-of-line implementation with no arguments is handy for gdb.
void ScheduleDAG::viewGraph() { void ScheduleDAG::viewGraph() {
viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName()); viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());
} }

lib/CodeGen/ScoreboardHazardRecognizer.cpp

Show All 19 Lines
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE ::llvm::ScoreboardHazardRecognizer::DebugType #define DEBUG_TYPE ::llvm::ScoreboardHazardRecognizer::DebugType
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const char *ScoreboardHazardRecognizer::DebugType = ""; const char *ScoreboardHazardRecognizer::DebugType = "";
#endif #endif
ScoreboardHazardRecognizer:: ScoreboardHazardRecognizer::
ScoreboardHazardRecognizer(const InstrItineraryData *II, ScoreboardHazardRecognizer(const InstrItineraryData *II,
const ScheduleDAG *SchedDAG, const ScheduleDAG *SchedDAG,
const char *ParentDebugType) : const char *ParentDebugType) :
ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0), ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0),
IssueCount(0) { IssueCount(0) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DebugType = ParentDebugType; DebugType = ParentDebugType;
#endif #endif
// Determine the maximum depth of any itinerary. This determines the depth of // Determine the maximum depth of any itinerary. This determines the depth of
// the scoreboard. We always make the scoreboard at least 1 cycle deep to // the scoreboard. We always make the scoreboard at least 1 cycle deep to
// avoid dealing with the boundary condition. // avoid dealing with the boundary condition.
unsigned ScoreboardDepth = 1; unsigned ScoreboardDepth = 1;
if (ItinData && !ItinData->isEmpty()) { if (ItinData && !ItinData->isEmpty()) {
Show All 37 Lines
} }
void ScoreboardHazardRecognizer::Reset() { void ScoreboardHazardRecognizer::Reset() {
IssueCount = 0; IssueCount = 0;
RequiredScoreboard.reset(); RequiredScoreboard.reset();
ReservedScoreboard.reset(); ReservedScoreboard.reset();
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void ScoreboardHazardRecognizer::Scoreboard::dump() const { void ScoreboardHazardRecognizer::Scoreboard::dump() const {
dbgs() << "Scoreboard:\n"; dbgs() << "Scoreboard:\n";
unsigned last = Depth - 1; unsigned last = Depth - 1;
while ((last > 0) && ((*this)[last] == 0)) while ((last > 0) && ((*this)[last] == 0))
last--; last--;
for (unsigned i = 0; i <= last; i++) { for (unsigned i = 0; i <= last; i++) {
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Linesnamespace {
static cl::opt<bool> static cl::opt<bool>
CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
cl::desc("Enable DAG combiner's use of IR alias analysis")); cl::desc("Enable DAG combiner's use of IR alias analysis"));
static cl::opt<bool> static cl::opt<bool>
UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true), UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
cl::desc("Enable DAG combiner's use of TBAA")); cl::desc("Enable DAG combiner's use of TBAA"));
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<std::string> static cl::opt<std::string>
CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden, CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
cl::desc("Only use DAG-combiner alias analysis in this" cl::desc("Only use DAG-combiner alias analysis in this"
" function")); " function"));
#endif #endif
/// Hidden option to stress test load slicing, i.e., when this option /// Hidden option to stress test load slicing, i.e., when this option
/// is enabled, load slicing bypasses most of its profitability guards. /// is enabled, load slicing bypasses most of its profitability guards.
▲ Show 20 Lines • Show All 9,539 Lines • ▼ Show 20 Lines if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
if (NewLoad.getNode() != N) if (NewLoad.getNode() != N)
return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true); return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
} }
} }
} }
bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
: DAG.getSubtarget().useAA(); : DAG.getSubtarget().useAA();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (CombinerAAOnlyFunc.getNumOccurrences() && if (CombinerAAOnlyFunc.getNumOccurrences() &&
CombinerAAOnlyFunc != DAG.getMachineFunction().getName()) CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
UseAA = false; UseAA = false;
#endif #endif
if (UseAA && LD->isUnindexed()) { if (UseAA && LD->isUnindexed()) {
// Walk up chain skipping non-aliasing memory nodes. // Walk up chain skipping non-aliasing memory nodes.
SDValue BetterChain = FindBetterChain(N, Chain); SDValue BetterChain = FindBetterChain(N, Chain);
▲ Show 20 Lines • Show All 1,678 Lines • ▼ Show 20 LinesSDValue DAGCombiner::visitSTORE(SDNode *N) {
// Try transforming a pair floating point load / store ops to integer // Try transforming a pair floating point load / store ops to integer
// load / store ops. // load / store ops.
if (SDValue NewST = TransformFPLoadStorePair(N)) if (SDValue NewST = TransformFPLoadStorePair(N))
return NewST; return NewST;
bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
: DAG.getSubtarget().useAA(); : DAG.getSubtarget().useAA();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (CombinerAAOnlyFunc.getNumOccurrences() && if (CombinerAAOnlyFunc.getNumOccurrences() &&
CombinerAAOnlyFunc != DAG.getMachineFunction().getName()) CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
UseAA = false; UseAA = false;
#endif #endif
if (UseAA && ST->isUnindexed()) { if (UseAA && ST->isUnindexed()) {
// Walk up chain skipping non-aliasing memory nodes. // Walk up chain skipping non-aliasing memory nodes.
SDValue BetterChain = FindBetterChain(N, Chain); SDValue BetterChain = FindBetterChain(N, Chain);
▲ Show 20 Lines • Show All 2,608 Lines • ▼ Show 20 Lines if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 || if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
(OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1) (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
return false; return false;
} }
bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
? CombinerGlobalAA ? CombinerGlobalAA
: DAG.getSubtarget().useAA(); : DAG.getSubtarget().useAA();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (CombinerAAOnlyFunc.getNumOccurrences() && if (CombinerAAOnlyFunc.getNumOccurrences() &&
CombinerAAOnlyFunc != DAG.getMachineFunction().getName()) CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
UseAA = false; UseAA = false;
#endif #endif
if (UseAA && if (UseAA &&
Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) { Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
// Use alias analysis information. // Use alias analysis information.
int64_t MinOffset = std::min(Op0->getSrcValueOffset(), int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
▲ Show 20 Lines • Show All 184 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

Show First 20 Lines • Show All 330 Lines • ▼ Show 20 Lines
/// different function. /// different function.
void FunctionLoweringInfo::clear() { void FunctionLoweringInfo::clear() {
assert(CatchInfoFound.size() == CatchInfoLost.size() && assert(CatchInfoFound.size() == CatchInfoLost.size() &&
"Not all catch info was assigned to a landing pad!"); "Not all catch info was assigned to a landing pad!");
MBBMap.clear(); MBBMap.clear();
ValueMap.clear(); ValueMap.clear();
StaticAllocaMap.clear(); StaticAllocaMap.clear();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
CatchInfoLost.clear(); CatchInfoLost.clear();
CatchInfoFound.clear(); CatchInfoFound.clear();
#endif #endif
LiveOutRegInfo.clear(); LiveOutRegInfo.clear();
VisitedBBs.clear(); VisitedBBs.clear();
ArgDbgValues.clear(); ArgDbgValues.clear();
ByValArgFrameIndexMap.clear(); ByValArgFrameIndexMap.clear();
RegFixups.clear(); RegFixups.clear();
▲ Show 20 Lines • Show All 230 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Show First 20 Lines • Show All 762 Lines • ▼ Show 20 Lines if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
} }
ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC); ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
} }
unsigned NumImpUses = 0; unsigned NumImpUses = 0;
unsigned NodeOperands = unsigned NodeOperands =
countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses); countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned NumMIOperands = NodeOperands + NumResults; unsigned NumMIOperands = NodeOperands + NumResults;
if (II.isVariadic()) if (II.isVariadic())
assert(NumMIOperands >= II.getNumOperands() && assert(NumMIOperands >= II.getNumOperands() &&
"Too few operands for a variadic node!"); "Too few operands for a variadic node!");
else else
assert(NumMIOperands >= II.getNumOperands() && assert(NumMIOperands >= II.getNumOperands() &&
NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
NumImpUses && NumImpUses &&
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
/// EmitSpecialNode - Generate machine code for a target-independent node and /// EmitSpecialNode - Generate machine code for a target-independent node and
/// needed dependencies. /// needed dependencies.
void InstrEmitter:: void InstrEmitter::
EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, unsigned> &VRBaseMap) {
switch (Node->getOpcode()) { switch (Node->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Node->dump(); Node->dump();
#endif #endif
llvm_unreachable("This target-independent node should have been selected!"); llvm_unreachable("This target-independent node should have been selected!");
case ISD::EntryToken: case ISD::EntryToken:
llvm_unreachable("EntryToken should have been excluded from the schedule!"); llvm_unreachable("EntryToken should have been excluded from the schedule!");
case ISD::MERGE_VALUES: case ISD::MERGE_VALUES:
case ISD::TokenFactor: // fall thru case ISD::TokenFactor: // fall thru
break; break;
▲ Show 20 Lines • Show All 154 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Show First 20 Lines • Show All 1,159 Lines • ▼ Show 20 Lines
/// Return a legal replacement for the given operation, with all legal operands. /// Return a legal replacement for the given operation, with all legal operands.
void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG)); DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
return; return;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) == assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
TargetLowering::TypeLegal && TargetLowering::TypeLegal &&
"Unexpected illegal type!"); "Unexpected illegal type!");
for (const SDValue &Op : Node->op_values()) for (const SDValue &Op : Node->op_values())
assert((TLI.getTypeAction(*DAG.getContext(), assert((TLI.getTypeAction(*DAG.getContext(),
Op.getValueType()) == TargetLowering::TypeLegal || Op.getValueType()) == TargetLowering::TypeLegal ||
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines if (SimpleFinishLegalizing) {
case TargetLowering::Promote: case TargetLowering::Promote:
PromoteNode(Node); PromoteNode(Node);
return; return;
} }
} }
switch (Node->getOpcode()) { switch (Node->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "NODE: "; dbgs() << "NODE: ";
Node->dump( &DAG); Node->dump( &DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to legalize this operator!"); llvm_unreachable("Do not know how to legalize this operator!");
case ISD::CALLSEQ_START: case ISD::CALLSEQ_START:
case ISD::CALLSEQ_END: case ISD::CALLSEQ_END:
▲ Show 20 Lines • Show All 2,996 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG); DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG);
dbgs() << "\n"); dbgs() << "\n");
SDValue R = SDValue(); SDValue R = SDValue();
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "SoftenFloatResult #" << ResNo << ": "; dbgs() << "SoftenFloatResult #" << ResNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to soften the result of this operator!"); llvm_unreachable("Do not know how to soften the result of this operator!");
case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
▲ Show 20 Lines • Show All 610 Lines • ▼ Show 20 Lines
bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) { bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG); DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
dbgs() << "\n"); dbgs() << "\n");
SDValue Res = SDValue(); SDValue Res = SDValue();
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "SoftenFloatOperand Op #" << OpNo << ": "; dbgs() << "SoftenFloatOperand Op #" << OpNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to soften this operator's operand!"); llvm_unreachable("Do not know how to soften this operator's operand!");
case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break; case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break;
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Linesvoid DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
Lo = Hi = SDValue(); Lo = Hi = SDValue();
// See if the target wants to custom expand this node. // See if the target wants to custom expand this node.
if (CustomLowerNode(N, N->getValueType(ResNo), true)) if (CustomLowerNode(N, N->getValueType(ResNo), true))
return; return;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "ExpandFloatResult #" << ResNo << ": "; dbgs() << "ExpandFloatResult #" << ResNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to expand the result of this operator!"); llvm_unreachable("Do not know how to expand the result of this operator!");
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
▲ Show 20 Lines • Show All 480 Lines • ▼ Show 20 Linesbool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
SDValue Res = SDValue(); SDValue Res = SDValue();
// See if the target wants to custom expand this node. // See if the target wants to custom expand this node.
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
return false; return false;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "ExpandFloatOperand Op #" << OpNo << ": "; dbgs() << "ExpandFloatOperand Op #" << OpNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to expand this operator's operand!"); llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
▲ Show 20 Lines • Show All 628 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Show All 38 Linesvoid DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
SDValue Res = SDValue(); SDValue Res = SDValue();
// See if the target wants to custom expand this node. // See if the target wants to custom expand this node.
if (CustomLowerNode(N, N->getValueType(ResNo), true)) if (CustomLowerNode(N, N->getValueType(ResNo), true))
return; return;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "PromoteIntegerResult #" << ResNo << ": "; dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to promote this operator!"); llvm_unreachable("Do not know how to promote this operator!");
case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
▲ Show 20 Lines • Show All 783 Lines • ▼ Show 20 Linesbool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
SDValue Res = SDValue(); SDValue Res = SDValue();
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
return false; return false;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to promote this operator's operand!"); llvm_unreachable("Do not know how to promote this operator's operand!");
case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
case ISD::ATOMIC_STORE: case ISD::ATOMIC_STORE:
Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N)); Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
▲ Show 20 Lines • Show All 382 Lines • ▼ Show 20 Linesvoid DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
Lo = Hi = SDValue(); Lo = Hi = SDValue();
// See if the target wants to custom expand this node. // See if the target wants to custom expand this node.
if (CustomLowerNode(N, N->getValueType(ResNo), true)) if (CustomLowerNode(N, N->getValueType(ResNo), true))
return; return;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "ExpandIntegerResult #" << ResNo << ": "; dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to expand the result of this operator!"); llvm_unreachable("Do not know how to expand the result of this operator!");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
▲ Show 20 Lines • Show All 1,335 Lines • ▼ Show 20 Linesbool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
SDValue Res = SDValue(); SDValue Res = SDValue();
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
return false; return false;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
N->dump(&DAG); dbgs() << "\n"; N->dump(&DAG); dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to expand this operator's operand!"); llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
▲ Show 20 Lines • Show All 597 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

Show First 20 Lines • Show All 400 Lines • ▼ Show 20 Lines#endif
// Remove dead nodes. This is important to do for cleanliness but also before // Remove dead nodes. This is important to do for cleanliness but also before
// the checking loop below. Implicit folding by the DAG.getNode operators and // the checking loop below. Implicit folding by the DAG.getNode operators and
// node morphing can cause unreachable nodes to be around with their flags set // node morphing can cause unreachable nodes to be around with their flags set
// to new. // to new.
DAG.RemoveDeadNodes(); DAG.RemoveDeadNodes();
// In a debug build, scan all the nodes to make sure we found them all. This // In a debug build, scan all the nodes to make sure we found them all. This
// ensures that there are no cycles and that everything got processed. // ensures that there are no cycles and that everything got processed.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (SDNode &Node : DAG.allnodes()) { for (SDNode &Node : DAG.allnodes()) {
bool Failed = false; bool Failed = false;
// Check that all result types are legal. // Check that all result types are legal.
if (!IgnoreNodeResults(&Node)) if (!IgnoreNodeResults(&Node))
for (unsigned i = 0, NumVals = Node.getNumValues(); i < NumVals; ++i) for (unsigned i = 0, NumVals = Node.getNumValues(); i < NumVals; ++i)
if (!isTypeLegal(Node.getValueType(i))) { if (!isTypeLegal(Node.getValueType(i))) {
dbgs() << "Result type " << i << " illegal!\n"; dbgs() << "Result type " << i << " illegal!\n";
▲ Show 20 Lines • Show All 726 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Show All 34 Lines
void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"); dbgs() << "\n");
SDValue R = SDValue(); SDValue R = SDValue();
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
report_fatal_error("Do not know how to scalarize the result of this " report_fatal_error("Do not know how to scalarize the result of this "
"operator!\n"); "operator!\n");
case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
▲ Show 20 Lines • Show All 360 Lines • ▼ Show 20 Linesbool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"); dbgs() << "\n");
SDValue Res = SDValue(); SDValue Res = SDValue();
if (!Res.getNode()) { if (!Res.getNode()) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to scalarize this operator's operand!"); llvm_unreachable("Do not know how to scalarize this operator's operand!");
case ISD::BITCAST: case ISD::BITCAST:
Res = ScalarizeVecOp_BITCAST(N); Res = ScalarizeVecOp_BITCAST(N);
break; break;
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Linesvoid DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
SDValue Lo, Hi; SDValue Lo, Hi;
// See if the target wants to custom expand this node. // See if the target wants to custom expand this node.
if (CustomLowerNode(N, N->getValueType(ResNo), true)) if (CustomLowerNode(N, N->getValueType(ResNo), true))
return; return;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "SplitVectorResult #" << ResNo << ": "; dbgs() << "SplitVectorResult #" << ResNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
report_fatal_error("Do not know how to split the result of this " report_fatal_error("Do not know how to split the result of this "
"operator!\n"); "operator!\n");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
▲ Show 20 Lines • Show All 770 Lines • ▼ Show 20 Linesbool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
// See if the target wants to custom split this node. // See if the target wants to custom split this node.
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
return false; return false;
if (!Res.getNode()) { if (!Res.getNode()) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
report_fatal_error("Do not know how to split this operator's " report_fatal_error("Do not know how to split this operator's "
"operand!\n"); "operand!\n");
case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
▲ Show 20 Lines • Show All 542 Lines • ▼ Show 20 Linesvoid DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
// See if the target wants to custom widen this node. // See if the target wants to custom widen this node.
if (CustomWidenLowerNode(N, N->getValueType(ResNo))) if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
return; return;
SDValue Res = SDValue(); SDValue Res = SDValue();
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "WidenVectorResult #" << ResNo << ": "; dbgs() << "WidenVectorResult #" << ResNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to widen the result of this operator!"); llvm_unreachable("Do not know how to widen the result of this operator!");
case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
▲ Show 20 Lines • Show All 906 Lines • ▼ Show 20 Linesbool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
SDValue Res = SDValue(); SDValue Res = SDValue();
// See if the target wants to custom widen this node. // See if the target wants to custom widen this node.
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
return false; return false;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "WidenVectorOperand op #" << OpNo << ": "; dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
N->dump(&DAG); N->dump(&DAG);
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to widen this operator's operand!"); llvm_unreachable("Do not know how to widen this operator's operand!");
case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
▲ Show 20 Lines • Show All 759 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
// Bottom-Up Scheduling // Bottom-Up Scheduling
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
/// the AvailableQueue if the count reaches zero. Also update its cycle bound. /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
SUnit *PredSU = PredEdge->getSUnit(); SUnit *PredSU = PredEdge->getSUnit();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (PredSU->NumSuccsLeft == 0) { if (PredSU->NumSuccsLeft == 0) {
dbgs() << "*** Scheduling failed! ***\n"; dbgs() << "*** Scheduling failed! ***\n";
PredSU->dump(this); PredSU->dump(this);
dbgs() << " has been released too many times!\n"; dbgs() << " has been released too many times!\n";
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
#endif #endif
--PredSU->NumSuccsLeft; --PredSU->NumSuccsLeft;
▲ Show 20 Lines • Show All 479 Lines • ▼ Show 20 Lines while (!AvailableQueue.empty()) {
if (CurSU) if (CurSU)
ScheduleNodeBottomUp(CurSU, CurCycle); ScheduleNodeBottomUp(CurSU, CurCycle);
++CurCycle; ++CurCycle;
} }
// Reverse the order since it is bottom up. // Reverse the order since it is bottom up.
std::reverse(Sequence.begin(), Sequence.end()); std::reverse(Sequence.begin(), Sequence.end());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VerifyScheduledSequence(/*isBottomUp=*/true); VerifyScheduledSequence(/*isBottomUp=*/true);
#endif #endif
} }
namespace { namespace {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ScheduleDAGLinearize - No scheduling scheduler, it simply linearize the // ScheduleDAGLinearize - No scheduling scheduler, it simply linearize the
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Show First 20 Lines • Show All 359 Lines • ▼ Show 20 Lines
// Bottom-Up Scheduling // Bottom-Up Scheduling
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
/// the AvailableQueue if the count reaches zero. Also update its cycle bound. /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
SUnit *PredSU = PredEdge->getSUnit(); SUnit *PredSU = PredEdge->getSUnit();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (PredSU->NumSuccsLeft == 0) { if (PredSU->NumSuccsLeft == 0) {
dbgs() << "*** Scheduling failed! ***\n"; dbgs() << "*** Scheduling failed! ***\n";
PredSU->dump(this); PredSU->dump(this);
dbgs() << " has been released too many times!\n"; dbgs() << " has been released too many times!\n";
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
#endif #endif
--PredSU->NumSuccsLeft; --PredSU->NumSuccsLeft;
▲ Show 20 Lines • Show All 325 Lines • ▼ Show 20 Lines
/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
/// count of its predecessors. If a predecessor pending count is zero, add it to /// count of its predecessors. If a predecessor pending count is zero, add it to
/// the Available queue. /// the Available queue.
void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: "); DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: ");
DEBUG(SU->dump(this)); DEBUG(SU->dump(this));
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (CurCycle < SU->getHeight()) if (CurCycle < SU->getHeight())
DEBUG(dbgs() << " Height [" << SU->getHeight() DEBUG(dbgs() << " Height [" << SU->getHeight()
<< "] pipeline stall!\n"); << "] pipeline stall!\n");
#endif #endif
// FIXME: Do not modify node height. It may interfere with // FIXME: Do not modify node height. It may interfere with
// backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the // backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the
// node its ready cycle can aid heuristics, and after scheduling it can // node its ready cycle can aid heuristics, and after scheduling it can
▲ Show 20 Lines • Show All 807 Lines • ▼ Show 20 Lines while (AvailableQueue->empty() && !PendingQueue.empty()) {
assert(MinAvailableCycle < UINT_MAX && "MinAvailableCycle uninitialized"); assert(MinAvailableCycle < UINT_MAX && "MinAvailableCycle uninitialized");
AdvanceToCycle(std::max(CurCycle + 1, MinAvailableCycle)); AdvanceToCycle(std::max(CurCycle + 1, MinAvailableCycle));
} }
} }
// Reverse the order if it is bottom up. // Reverse the order if it is bottom up.
std::reverse(Sequence.begin(), Sequence.end()); std::reverse(Sequence.begin(), Sequence.end());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VerifyScheduledSequence(/*isBottomUp=*/true); VerifyScheduledSequence(/*isBottomUp=*/true);
#endif #endif
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// RegReductionPriorityQueue Definition // RegReductionPriorityQueue Definition
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
// to reduce register pressure. // to reduce register pressure.
// //
namespace { namespace {
class RegReductionPQBase; class RegReductionPQBase;
struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> { struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
}; };
#ifndef NDEBUG #ifndef LLVM_NDEBUG
template<class SF> template<class SF>
struct reverse_sort : public queue_sort { struct reverse_sort : public queue_sort {
SF &SortFunc; SF &SortFunc;
reverse_sort(SF &sf) : SortFunc(sf) {} reverse_sort(SF &sf) : SortFunc(sf) {}
bool operator()(SUnit* left, SUnit* right) const { bool operator()(SUnit* left, SUnit* right) const {
// reverse left/right rather than simply !SortFunc(left, right) // reverse left/right rather than simply !SortFunc(left, right)
// to expose different paths in the comparison logic. // to expose different paths in the comparison logic.
return SortFunc(right, left); return SortFunc(right, left);
} }
}; };
#endif // NDEBUG #endif // LLVM_NDEBUG
/// bu_ls_rr_sort - Priority function for bottom up register pressure /// bu_ls_rr_sort - Priority function for bottom up register pressure
// reduction scheduler. // reduction scheduler.
struct bu_ls_rr_sort : public queue_sort { struct bu_ls_rr_sort : public queue_sort {
enum { enum {
IsBottomUp = true, IsBottomUp = true,
HasReadyFilter = false HasReadyFilter = false
}; };
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Linesstatic SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) {
if (Best != std::prev(Q.end())) if (Best != std::prev(Q.end()))
std::swap(*Best, Q.back()); std::swap(*Best, Q.back());
Q.pop_back(); Q.pop_back();
return V; return V;
} }
template<class SF> template<class SF>
SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) { SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (DAG->StressSched) { if (DAG->StressSched) {
reverse_sort<SF> RPicker(Picker); reverse_sort<SF> RPicker(Picker);
return popFromQueueImpl(Q, RPicker); return popFromQueueImpl(Q, RPicker);
} }
#endif #endif
(void)DAG; (void)DAG;
return popFromQueueImpl(Q, Picker); return popFromQueueImpl(Q, Picker);
} }
Show All 22 Linespublic:
SUnit *pop() override { SUnit *pop() override {
if (Queue.empty()) return nullptr; if (Queue.empty()) return nullptr;
SUnit *V = popFromQueue(Queue, Picker, scheduleDAG); SUnit *V = popFromQueue(Queue, Picker, scheduleDAG);
V->NodeQueueId = 0; V->NodeQueueId = 0;
return V; return V;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dump(ScheduleDAG *DAG) const override { void dump(ScheduleDAG *DAG) const override {
// Emulate pop() without clobbering NodeQueueIds. // Emulate pop() without clobbering NodeQueueIds.
std::vector<SUnit*> DumpQueue = Queue; std::vector<SUnit*> DumpQueue = Queue;
SF DumpPicker = Picker; SF DumpPicker = Picker;
while (!DumpQueue.empty()) { while (!DumpQueue.empty()) {
SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
dbgs() << "Height " << SU->getHeight() << ": "; dbgs() << "Height " << SU->getHeight() << ": ";
SU->dump(DAG); SU->dump(DAG);
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
#endif #endif
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register Pressure Tracking // Register Pressure Tracking
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void RegReductionPQBase::dumpRegPressure() const { void RegReductionPQBase::dumpRegPressure() const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I) { E = TRI->regclass_end(); I != E; ++I) {
const TargetRegisterClass *RC = *I; const TargetRegisterClass *RC = *I;
unsigned Id = RC->getID(); unsigned Id = RC->getID();
unsigned RP = RegPressure[Id]; unsigned RP = RegPressure[Id];
if (!RP) continue; if (!RP) continue;
DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / " DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / "
<< RegLimit[Id] << '\n'); << RegLimit[Id] << '\n');
▲ Show 20 Lines • Show All 454 Lines • ▼ Show 20 Linesstatic bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
// Schedule physical register definitions close to their use. This is // Schedule physical register definitions close to their use. This is
// motivated by microarchitectures that can fuse cmp+jump macro-ops. But as // motivated by microarchitectures that can fuse cmp+jump macro-ops. But as
// long as shortening physreg live ranges is generally good, we can defer // long as shortening physreg live ranges is generally good, we can defer
// creating a subtarget hook. // creating a subtarget hook.
if (!DisableSchedPhysRegJoin) { if (!DisableSchedPhysRegJoin) {
bool LHasPhysReg = left->hasPhysRegDefs; bool LHasPhysReg = left->hasPhysRegDefs;
bool RHasPhysReg = right->hasPhysRegDefs; bool RHasPhysReg = right->hasPhysRegDefs;
if (LHasPhysReg != RHasPhysReg) { if (LHasPhysReg != RHasPhysReg) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static const char *const PhysRegMsg[] = { " has no physreg", static const char *const PhysRegMsg[] = { " has no physreg",
" defines a physreg" }; " defines a physreg" };
#endif #endif
DEBUG(dbgs() << " SU (" << left->NodeNum << ") " DEBUG(dbgs() << " SU (" << left->NodeNum << ") "
<< PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") " << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "
<< PhysRegMsg[RHasPhysReg] << "\n"); << PhysRegMsg[RHasPhysReg] << "\n");
return LHasPhysReg < RHasPhysReg; return LHasPhysReg < RHasPhysReg;
} }
▲ Show 20 Lines • Show All 629 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linesvoid ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
// Invoke the target's selection of scheduler. // Invoke the target's selection of scheduler.
Schedule(); Schedule();
} }
/// NewSUnit - Creates a new SUnit and return a ptr to it. /// NewSUnit - Creates a new SUnit and return a ptr to it.
/// ///
SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) { SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const SUnit *Addr = nullptr; const SUnit *Addr = nullptr;
if (!SUnits.empty()) if (!SUnits.empty())
Addr = &SUnits[0]; Addr = &SUnits[0];
#endif #endif
SUnits.emplace_back(N, (unsigned)SUnits.size()); SUnits.emplace_back(N, (unsigned)SUnits.size());
assert((Addr == nullptr || Addr == &SUnits[0]) && assert((Addr == nullptr || Addr == &SUnits[0]) &&
"SUnits std::vector reallocated on the fly!"); "SUnits std::vector reallocated on the fly!");
SUnits.back().OrigNode = &SUnits.back(); SUnits.back().OrigNode = &SUnits.back();
▲ Show 20 Lines • Show All 567 Lines • ▼ Show 20 Lines if (TargetRegisterInfo::isVirtualRegister(Reg))
// FIXME: need target specific adjustment here? // FIXME: need target specific adjustment here?
Latency = (Latency > 1) ? Latency - 1 : 1; Latency = (Latency > 1) ? Latency - 1 : 1;
} }
if (Latency >= 0) if (Latency >= 0)
dep.setLatency(Latency); dep.setLatency(Latency);
} }
void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
if (!SU->getNode()) { if (!SU->getNode()) {
dbgs() << "PHYS REG COPY\n"; dbgs() << "PHYS REG COPY\n";
return; return;
} }
SU->getNode()->dump(DAG); SU->getNode()->dump(DAG);
dbgs() << "\n"; dbgs() << "\n";
SmallVector<SDNode *, 4> GluedNodes; SmallVector<SDNode *, 4> GluedNodes;
for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode()) for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
GluedNodes.push_back(N); GluedNodes.push_back(N);
while (!GluedNodes.empty()) { while (!GluedNodes.empty()) {
dbgs() << " "; dbgs() << " ";
GluedNodes.back()->dump(DAG); GluedNodes.back()->dump(DAG);
dbgs() << "\n"; dbgs() << "\n";
GluedNodes.pop_back(); GluedNodes.pop_back();
} }
#endif #endif
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void ScheduleDAGSDNodes::dumpSchedule() const { void ScheduleDAGSDNodes::dumpSchedule() const {
for (unsigned i = 0, e = Sequence.size(); i != e; i++) { for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) if (SUnit *SU = Sequence[i])
SU->dump(this); SU->dump(this);
else else
dbgs() << "**** NOOP ****\n"; dbgs() << "**** NOOP ****\n";
} }
} }
#endif #endif
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// VerifyScheduledSequence - Verify that all SUnits were scheduled and that /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
/// their state is consistent with the nodes listed in Sequence. /// their state is consistent with the nodes listed in Sequence.
/// ///
void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) { void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp); unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
unsigned Noops = 0; unsigned Noops = 0;
for (unsigned i = 0, e = Sequence.size(); i != e; ++i) for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
if (!Sequence[i]) if (!Sequence[i])
++Noops; ++Noops;
assert(Sequence.size() - Noops == ScheduledNodes && assert(Sequence.size() - Noops == ScheduledNodes &&
"The number of nodes scheduled doesn't match the expected number!"); "The number of nodes scheduled doesn't match the expected number!");
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
/// ProcessSDDbgValues - Process SDDbgValues associated with this node. /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
static void static void
ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) { DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
if (!N->getHasDebugValue()) if (!N->getHasDebugValue())
return; return;
▲ Show 20 Lines • Show All 208 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
// Top-Down Scheduling // Top-Down Scheduling
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// releaseSucc - Decrement the NumPredsLeft count of a successor. Add it to /// releaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
/// the PendingQueue if the count reaches zero. Also update its cycle bound. /// the PendingQueue if the count reaches zero. Also update its cycle bound.
void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
SUnit *SuccSU = D.getSUnit(); SUnit *SuccSU = D.getSUnit();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (SuccSU->NumPredsLeft == 0) { if (SuccSU->NumPredsLeft == 0) {
dbgs() << "*** Scheduling failed! ***\n"; dbgs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this); SuccSU->dump(this);
dbgs() << " has been released too many times!\n"; dbgs() << " has been released too many times!\n";
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
#endif #endif
assert(!D.isWeak() && "unexpected artificial DAG edge"); assert(!D.isWeak() && "unexpected artificial DAG edge");
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines if (FoundSUnit) {
DEBUG(dbgs() << "*** Emitting noop\n"); DEBUG(dbgs() << "*** Emitting noop\n");
HazardRec->EmitNoop(); HazardRec->EmitNoop();
Sequence.push_back(nullptr); // NULL here means noop Sequence.push_back(nullptr); // NULL here means noop
++NumNoops; ++NumNoops;
++CurCycle; ++CurCycle;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VerifyScheduledSequence(/*isBottomUp=*/false); VerifyScheduledSequence(/*isBottomUp=*/false);
#endif #endif
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Public Constructor Functions // Public Constructor Functions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// createVLIWDAGScheduler - This creates a top-down list scheduler. /// createVLIWDAGScheduler - This creates a top-down list scheduler.
ScheduleDAGSDNodes * ScheduleDAGSDNodes *
llvm::createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) { llvm::createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
return new ScheduleDAGVLIW(*IS->MF, IS->AA, new ResourcePriorityQueue(IS)); return new ScheduleDAGVLIW(*IS->MF, IS->AA, new ResourcePriorityQueue(IS));
} }

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 713 Lines • ▼ Show 20 Linesvoid SelectionDAG::DeallocateNode(SDNode *N) {
NodeAllocator.Deallocate(AllNodes.remove(N)); NodeAllocator.Deallocate(AllNodes.remove(N));
// If any of the SDDbgValue nodes refer to this SDNode, invalidate // If any of the SDDbgValue nodes refer to this SDNode, invalidate
// them and forget about that node. // them and forget about that node.
DbgInfo->erase(N); DbgInfo->erase(N);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// VerifySDNode - Sanity check the given SDNode. Aborts if it is invalid. /// VerifySDNode - Sanity check the given SDNode. Aborts if it is invalid.
static void VerifySDNode(SDNode *N) { static void VerifySDNode(SDNode *N) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
break; break;
case ISD::BUILD_PAIR: { case ISD::BUILD_PAIR: {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
assert(N->getNumValues() == 1 && "Too many results!"); assert(N->getNumValues() == 1 && "Too many results!");
Show All 21 Lines for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
"Wrong operand type!"); "Wrong operand type!");
assert(I->getValueType() == N->getOperand(0).getValueType() && assert(I->getValueType() == N->getOperand(0).getValueType() &&
"Operands must all have the same type"); "Operands must all have the same type");
} }
break; break;
} }
} }
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
/// \brief Insert a newly allocated node into the DAG. /// \brief Insert a newly allocated node into the DAG.
/// ///
/// Handles insertion into the all nodes list and CSE map, as well as /// Handles insertion into the all nodes list and CSE map, as well as
/// verification and other common operations when a new node is allocated. /// verification and other common operations when a new node is allocated.
void SelectionDAG::InsertNode(SDNode *N) { void SelectionDAG::InsertNode(SDNode *N) {
AllNodes.push_back(N); AllNodes.push_back(N);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VerifySDNode(N); VerifySDNode(N);
#endif #endif
} }
/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
/// correspond to it. This is useful when we're about to delete or repurpose /// correspond to it. This is useful when we're about to delete or repurpose
/// the node. We don't want future request for structurally identical nodes /// the node. We don't want future request for structurally identical nodes
/// to return N anymore. /// to return N anymore.
Show All 34 Linesbool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
} }
default: default:
// Remove it from the CSE Map. // Remove it from the CSE Map.
assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!"); assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!");
assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!"); assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!");
Erased = CSEMap.RemoveNode(N); Erased = CSEMap.RemoveNode(N);
break; break;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify that the node was actually in one of the CSE maps, unless it has a // Verify that the node was actually in one of the CSE maps, unless it has a
// flag result (which cannot be CSE'd) or is one of the special cases that are // flag result (which cannot be CSE'd) or is one of the special cases that are
// not subject to CSE. // not subject to CSE.
if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Glue && if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Glue &&
!N->isMachineOpcode() && !doNotCSE(N)) { !N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this); N->dump(this);
dbgs() << "\n"; dbgs() << "\n";
llvm_unreachable("Node is not in map!"); llvm_unreachable("Node is not in map!");
▲ Show 20 Lines • Show All 5,389 Lines • ▼ Show 20 Lines
/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
/// This can cause recursive merging of nodes in the DAG. /// This can cause recursive merging of nodes in the DAG.
/// ///
/// This version assumes that for each value of From, there is a /// This version assumes that for each value of From, there is a
/// corresponding value in To in the same position with the same type. /// corresponding value in To in the same position with the same type.
/// ///
void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) { void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) for (unsigned i = 0, e = From->getNumValues(); i != e; ++i)
assert((!From->hasAnyUseOfValue(i) || assert((!From->hasAnyUseOfValue(i) ||
From->getValueType(i) == To->getValueType(i)) && From->getValueType(i) == To->getValueType(i)) &&
"Cannot use this version of ReplaceAllUsesWith!"); "Cannot use this version of ReplaceAllUsesWith!");
#endif #endif
// Handle the trivial case. // Handle the trivial case.
if (From == To) if (From == To)
▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Lines for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
assert(SortedPos != AllNodes.end() && "Overran node list"); assert(SortedPos != AllNodes.end() && "Overran node list");
++SortedPos; ++SortedPos;
} else { } else {
// Update P's outstanding operand count. // Update P's outstanding operand count.
P->setNodeId(Degree); P->setNodeId(Degree);
} }
} }
if (&Node == SortedPos) { if (&Node == SortedPos) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
allnodes_iterator I = N; allnodes_iterator I = N;
SDNode *S = ++I; SDNode *S = ++I;
dbgs() << "Overran sorted position:\n"; dbgs() << "Overran sorted position:\n";
S->dumprFull(this); dbgs() << "\n"; S->dumprFull(this); dbgs() << "\n";
dbgs() << "Checking if this is due to cycles\n"; dbgs() << "Checking if this is due to cycles\n";
checkForCycles(this, true); checkForCycles(this, true);
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
▲ Show 20 Lines • Show All 616 Lines • ▼ Show 20 Linesbool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) {
// Make sure all remaining elements are either undef or the same as the first // Make sure all remaining elements are either undef or the same as the first
// non-undef value. // non-undef value.
for (int Idx = Mask[i]; i != e; ++i) for (int Idx = Mask[i]; i != e; ++i)
if (Mask[i] >= 0 && Mask[i] != Idx) if (Mask[i] >= 0 && Mask[i] != Idx)
return false; return false;
return true; return true;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static void checkForCyclesHelper(const SDNode *N, static void checkForCyclesHelper(const SDNode *N,
SmallPtrSetImpl<const SDNode*> &Visited, SmallPtrSetImpl<const SDNode*> &Visited,
SmallPtrSetImpl<const SDNode*> &Checked, SmallPtrSetImpl<const SDNode*> &Checked,
const llvm::SelectionDAG *DAG) { const llvm::SelectionDAG *DAG) {
// If this node has already been checked, don't check it again. // If this node has already been checked, don't check it again.
if (Checked.count(N)) if (Checked.count(N))
return; return;
Show All 12 Linesstatic void checkForCyclesHelper(const SDNode *N,
Checked.insert(N); Checked.insert(N);
Visited.erase(N); Visited.erase(N);
} }
#endif #endif
void llvm::checkForCycles(const llvm::SDNode *N, void llvm::checkForCycles(const llvm::SDNode *N,
const llvm::SelectionDAG *DAG, const llvm::SelectionDAG *DAG,
bool force) { bool force) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool check = force; bool check = force;
#ifdef XDEBUG #ifdef XDEBUG
check = true; check = true;
#endif // XDEBUG #endif // XDEBUG
if (check) { if (check) {
assert(N && "Checking nonexistent SDNode"); assert(N && "Checking nonexistent SDNode");
SmallPtrSet<const SDNode*, 32> visited; SmallPtrSet<const SDNode*, 32> visited;
SmallPtrSet<const SDNode*, 32> checked; SmallPtrSet<const SDNode*, 32> checked;
checkForCyclesHelper(N, visited, checked, DAG); checkForCyclesHelper(N, visited, checked, DAG);
} }
#endif // !NDEBUG #endif // !LLVM_NDEBUG
} }
void llvm::checkForCycles(const llvm::SelectionDAG *DAG, bool force) { void llvm::checkForCycles(const llvm::SelectionDAG *DAG, bool force) {
checkForCycles(DAG->getRoot().getNode(), DAG, force); checkForCycles(DAG->getRoot().getNode(), DAG, force);
} }

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,058 Lines • ▼ Show 20 Linesvoid SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
// Merge into one. // Merge into one.
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
DAG.getVTList(ValueVTs), Ops); DAG.getVTList(ValueVTs), Ops);
setValue(&LP, Res); setValue(&LP, Res);
} }
void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) { void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (const CaseCluster &CC : Clusters) for (const CaseCluster &CC : Clusters)
assert(CC.Low == CC.High && "Input clusters must be single-case"); assert(CC.Low == CC.High && "Input clusters must be single-case");
#endif #endif
std::sort(Clusters.begin(), Clusters.end(), std::sort(Clusters.begin(), Clusters.end(),
[](const CaseCluster &a, const CaseCluster &b) { [](const CaseCluster &a, const CaseCluster &b) {
return a.Low->getValue().slt(b.Low->getValue()); return a.Low->getValue().slt(b.Low->getValue());
}); });
▲ Show 20 Lines • Show All 5,487 Lines • ▼ Show 20 Linesbool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High, JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
JTCases.size() - 1, Weight); JTCases.size() - 1, Weight);
return true; return true;
} }
void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters, void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
const SwitchInst *SI, const SwitchInst *SI,
MachineBasicBlock *DefaultMBB) { MachineBasicBlock *DefaultMBB) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Clusters must be non-empty, sorted, and only contain Range clusters. // Clusters must be non-empty, sorted, and only contain Range clusters.
assert(!Clusters.empty()); assert(!Clusters.empty());
for (CaseCluster &C : Clusters) for (CaseCluster &C : Clusters)
assert(C.Kind == CC_Range); assert(C.Kind == CC_Range);
for (unsigned i = 1, e = Clusters.size(); i < e; ++i) for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue())); assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
#endif #endif
▲ Show 20 Lines • Show All 215 Lines • ▼ Show 20 Linesbool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
return true; return true;
} }
void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters, void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
const SwitchInst *SI) { const SwitchInst *SI) {
// Partition Clusters into as few subsets as possible, where each subset has a // Partition Clusters into as few subsets as possible, where each subset has a
// range that fits in a machine word and has <= 3 unique destinations. // range that fits in a machine word and has <= 3 unique destinations.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Clusters must be sorted and contain Range or JumpTable clusters. // Clusters must be sorted and contain Range or JumpTable clusters.
assert(!Clusters.empty()); assert(!Clusters.empty());
assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable); assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
for (const CaseCluster &C : Clusters) for (const CaseCluster &C : Clusters)
assert(C.Kind == CC_Range || C.Kind == CC_JumpTable); assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
for (unsigned i = 1; i < Clusters.size(); ++i) for (unsigned i = 1; i < Clusters.size(); ++i)
assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue())); assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
#endif #endif
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lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines default:
if (G) { if (G) {
const TargetLowering &TLI = G->getTargetLoweringInfo(); const TargetLowering &TLI = G->getTargetLoweringInfo();
const char *Name = TLI.getTargetNodeName(getOpcode()); const char *Name = TLI.getTargetNodeName(getOpcode());
if (Name) return Name; if (Name) return Name;
return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>"; return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>";
} }
return "<<Unknown Node #" + utostr(getOpcode()) + ">>"; return "<<Unknown Node #" + utostr(getOpcode()) + ">>";
#ifndef NDEBUG #ifndef LLVM_NDEBUG
case ISD::DELETED_NODE: return "<<Deleted Node!>>"; case ISD::DELETED_NODE: return "<<Deleted Node!>>";
#endif #endif
case ISD::PREFETCH: return "Prefetch"; case ISD::PREFETCH: return "Prefetch";
case ISD::ATOMIC_FENCE: return "AtomicFence"; case ISD::ATOMIC_FENCE: return "AtomicFence";
case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
case ISD::ATOMIC_SWAP: return "AtomicSwap"; case ISD::ATOMIC_SWAP: return "AtomicSwap";
case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
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lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
STATISTIC(NumFastIselFailLowerArguments, STATISTIC(NumFastIselFailLowerArguments,
"Number of entry blocks where fast isel failed to lower arguments"); "Number of entry blocks where fast isel failed to lower arguments");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<bool> static cl::opt<bool>
EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
cl::desc("Enable extra verbose messages in the \"fast\" " cl::desc("Enable extra verbose messages in the \"fast\" "
"instruction selector")); "instruction selector"));
// Terminators // Terminators
STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines cl::desc("Enable abort calls when \"fast\" instruction selection "
"abort for argument lowering, and 3 will never fallback " "abort for argument lowering, and 3 will never fallback "
"to SelectionDAG.")); "to SelectionDAG."));
static cl::opt<bool> static cl::opt<bool>
UseMBPI("use-mbpi", UseMBPI("use-mbpi",
cl::desc("use Machine Branch Probability Info"), cl::desc("use Machine Branch Probability Info"),
cl::init(true), cl::Hidden); cl::init(true), cl::Hidden);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<std::string> static cl::opt<std::string>
FilterDAGBasicBlockName("filter-view-dags", cl::Hidden, FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
cl::desc("Only display the basic block whose name " cl::desc("Only display the basic block whose name "
"matches this for all view-*-dags options")); "matches this for all view-*-dags options"));
static cl::opt<bool> static cl::opt<bool>
ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before the first " cl::desc("Pop up a window to show dags before the first "
"dag combine pass")); "dag combine pass"));
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// basic blocks, and this method is called to expand it into a sequence of // basic blocks, and this method is called to expand it into a sequence of
// instructions, potentially also creating new basic blocks and control flow. // instructions, potentially also creating new basic blocks and control flow.
// When new basic blocks are inserted and the edges from MBB to its successors // When new basic blocks are inserted and the edges from MBB to its successors
// are modified, the method should insert pairs of <OldSucc, NewSucc> into the // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
// DenseMap. // DenseMap.
MachineBasicBlock * MachineBasicBlock *
TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const { MachineBasicBlock *MBB) const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "If a target marks an instruction with " dbgs() << "If a target marks an instruction with "
"'usesCustomInserter', it must implement " "'usesCustomInserter', it must implement "
"TargetLowering::EmitInstrWithCustomInserter!"; "TargetLowering::EmitInstrWithCustomInserter!";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
void SelectionDAGISel::CodeGenAndEmitDAG() { void SelectionDAGISel::CodeGenAndEmitDAG() {
std::string GroupName; std::string GroupName;
if (TimePassesIsEnabled) if (TimePassesIsEnabled)
GroupName = "Instruction Selection and Scheduling"; GroupName = "Instruction Selection and Scheduling";
std::string BlockName; std::string BlockName;
int BlockNumber = -1; int BlockNumber = -1;
(void)BlockNumber; (void)BlockNumber;
bool MatchFilterBB = false; (void)MatchFilterBB; bool MatchFilterBB = false; (void)MatchFilterBB;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
MatchFilterBB = (FilterDAGBasicBlockName.empty() || MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
FilterDAGBasicBlockName == FilterDAGBasicBlockName ==
FuncInfo->MBB->getBasicBlock()->getName().str()); FuncInfo->MBB->getBasicBlock()->getName().str());
#endif #endif
#ifdef NDEBUG #ifdef LLVM_NDEBUG
if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
ViewSUnitDAGs) ViewSUnitDAGs)
#endif #endif
{ {
BlockNumber = FuncInfo->MBB->getNumber(); BlockNumber = FuncInfo->MBB->getNumber();
BlockName = BlockName =
(MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str(); (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
▲ Show 20 Lines • Show All 307 Lines • ▼ Show 20 Linesstatic bool isFoldedOrDeadInstruction(const Instruction *I,
FunctionLoweringInfo *FuncInfo) { FunctionLoweringInfo *FuncInfo) {
return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
!isa<TerminatorInst>(I) && // Terminators aren't folded. !isa<TerminatorInst>(I) && // Terminators aren't folded.
!isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
!isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
!FuncInfo->isExportedInst(I); // Exported instrs must be computed. !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Collect per Instruction statistics for fast-isel misses. Only those // Collect per Instruction statistics for fast-isel misses. Only those
// instructions that cause the bail are accounted for. It does not account for // instructions that cause the bail are accounted for. It does not account for
// instructions higher in the block. Thus, summing the per instructions stats // instructions higher in the block. Thus, summing the per instructions stats
// will not add up to what is reported by NumFastIselFailures. // will not add up to what is reported by NumFastIselFailures.
static void collectFailStats(const Instruction *I) { static void collectFailStats(const Instruction *I) {
switch (I->getOpcode()) { switch (I->getOpcode()) {
default: assert (0 && "<Invalid operator> "); default: assert (0 && "<Invalid operator> ");
▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines if (FastIS) {
// If we succeeded, don't re-select the load. // If we succeeded, don't re-select the load.
BI = std::next(BasicBlock::const_iterator(BeforeInst)); BI = std::next(BasicBlock::const_iterator(BeforeInst));
--NumFastIselRemaining; --NumFastIselRemaining;
++NumFastIselSuccess; ++NumFastIselSuccess;
} }
continue; continue;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (EnableFastISelVerbose2) if (EnableFastISelVerbose2)
collectFailStats(Inst); collectFailStats(Inst);
#endif #endif
// Then handle certain instructions as single-LLVM-Instruction blocks. // Then handle certain instructions as single-LLVM-Instruction blocks.
if (isa<CallInst>(Inst)) { if (isa<CallInst>(Inst)) {
if (EnableFastISelVerbose || EnableFastISelAbort) { if (EnableFastISelVerbose || EnableFastISelAbort) {
▲ Show 20 Lines • Show All 1,417 Lines • ▼ Show 20 Lines if (!OpcodeOffset.empty()) {
// Okay, do the lookup for the first opcode. // Okay, do the lookup for the first opcode.
if (N.getOpcode() < OpcodeOffset.size()) if (N.getOpcode() < OpcodeOffset.size())
MatcherIndex = OpcodeOffset[N.getOpcode()]; MatcherIndex = OpcodeOffset[N.getOpcode()];
} }
while (1) { while (1) {
assert(MatcherIndex < TableSize && "Invalid index"); assert(MatcherIndex < TableSize && "Invalid index");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned CurrentOpcodeIndex = MatcherIndex; unsigned CurrentOpcodeIndex = MatcherIndex;
#endif #endif
BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
switch (Opcode) { switch (Opcode) {
case OPC_Scope: { case OPC_Scope: {
// Okay, the semantics of this operation are that we should push a scope // Okay, the semantics of this operation are that we should push a scope
// then evaluate the first child. However, pushing a scope only to have // then evaluate the first child. However, pushing a scope only to have
// the first check fail (which then pops it) is inefficient. If we can // the first check fail (which then pops it) is inefficient. If we can
▲ Show 20 Lines • Show All 718 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines static std::string getSimpleNodeLabel(const SDNode *Node,
raw_string_ostream OS(Result); raw_string_ostream OS(Result);
Node->print_details(OS, G); Node->print_details(OS, G);
} }
return Result; return Result;
} }
std::string getNodeLabel(const SDNode *Node, const SelectionDAG *Graph); std::string getNodeLabel(const SDNode *Node, const SelectionDAG *Graph);
static std::string getNodeAttributes(const SDNode *N, static std::string getNodeAttributes(const SDNode *N,
const SelectionDAG *Graph) { const SelectionDAG *Graph) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const std::string &Attrs = Graph->getGraphAttrs(N); const std::string &Attrs = Graph->getGraphAttrs(N);
if (!Attrs.empty()) { if (!Attrs.empty()) {
if (Attrs.find("shape=") == std::string::npos) if (Attrs.find("shape=") == std::string::npos)
return std::string("shape=Mrecord,") + Attrs; return std::string("shape=Mrecord,") + Attrs;
else else
return Attrs; return Attrs;
} }
#endif #endif
Show All 16 Lines
} }
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
/// rendered using 'dot'. /// rendered using 'dot'.
/// ///
void SelectionDAG::viewGraph(const std::string &Title) { void SelectionDAG::viewGraph(const std::string &Title) {
// This code is only for debugging! // This code is only for debugging!
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ViewGraph(this, "dag." + getMachineFunction().getName(), ViewGraph(this, "dag." + getMachineFunction().getName(),
false, Title); false, Title);
#else #else
errs() << "SelectionDAG::viewGraph is only available in debug builds on " errs() << "SelectionDAG::viewGraph is only available in debug builds on "
<< "systems with Graphviz or gv!\n"; << "systems with Graphviz or gv!\n";
#endif // NDEBUG #endif // LLVM_NDEBUG
} }
// This overload is defined out-of-line here instead of just using a // This overload is defined out-of-line here instead of just using a
// default parameter because this is easiest for gdb to call. // default parameter because this is easiest for gdb to call.
void SelectionDAG::viewGraph() { void SelectionDAG::viewGraph() {
viewGraph(""); viewGraph("");
} }
/// clearGraphAttrs - Clear all previously defined node graph attributes. /// clearGraphAttrs - Clear all previously defined node graph attributes.
/// Intended to be used from a debugging tool (eg. gdb). /// Intended to be used from a debugging tool (eg. gdb).
void SelectionDAG::clearGraphAttrs() { void SelectionDAG::clearGraphAttrs() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
NodeGraphAttrs.clear(); NodeGraphAttrs.clear();
#else #else
errs() << "SelectionDAG::clearGraphAttrs is only available in debug builds" errs() << "SelectionDAG::clearGraphAttrs is only available in debug builds"
<< " on systems with Graphviz or gv!\n"; << " on systems with Graphviz or gv!\n";
#endif #endif
} }
/// setGraphAttrs - Set graph attributes for a node. (eg. "color=red".) /// setGraphAttrs - Set graph attributes for a node. (eg. "color=red".)
/// ///
void SelectionDAG::setGraphAttrs(const SDNode *N, const char *Attrs) { void SelectionDAG::setGraphAttrs(const SDNode *N, const char *Attrs) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
NodeGraphAttrs[N] = Attrs; NodeGraphAttrs[N] = Attrs;
#else #else
errs() << "SelectionDAG::setGraphAttrs is only available in debug builds" errs() << "SelectionDAG::setGraphAttrs is only available in debug builds"
<< " on systems with Graphviz or gv!\n"; << " on systems with Graphviz or gv!\n";
#endif #endif
} }
/// getGraphAttrs - Get graph attributes for a node. (eg. "color=red".) /// getGraphAttrs - Get graph attributes for a node. (eg. "color=red".)
/// Used from getNodeAttributes. /// Used from getNodeAttributes.
const std::string SelectionDAG::getGraphAttrs(const SDNode *N) const { const std::string SelectionDAG::getGraphAttrs(const SDNode *N) const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
std::map<const SDNode *, std::string>::const_iterator I = std::map<const SDNode *, std::string>::const_iterator I =
NodeGraphAttrs.find(N); NodeGraphAttrs.find(N);
if (I != NodeGraphAttrs.end()) if (I != NodeGraphAttrs.end())
return I->second; return I->second;
else else
return ""; return "";
#else #else
errs() << "SelectionDAG::getGraphAttrs is only available in debug builds" errs() << "SelectionDAG::getGraphAttrs is only available in debug builds"
<< " on systems with Graphviz or gv!\n"; << " on systems with Graphviz or gv!\n";
return std::string(); return std::string();
#endif #endif
} }
/// setGraphColor - Convenience for setting node color attribute. /// setGraphColor - Convenience for setting node color attribute.
/// ///
void SelectionDAG::setGraphColor(const SDNode *N, const char *Color) { void SelectionDAG::setGraphColor(const SDNode *N, const char *Color) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
NodeGraphAttrs[N] = std::string("color=") + Color; NodeGraphAttrs[N] = std::string("color=") + Color;
#else #else
errs() << "SelectionDAG::setGraphColor is only available in debug builds" errs() << "SelectionDAG::setGraphColor is only available in debug builds"
<< " on systems with Graphviz or gv!\n"; << " on systems with Graphviz or gv!\n";
#endif #endif
} }
/// setSubgraphColorHelper - Implement setSubgraphColor. Return /// setSubgraphColorHelper - Implement setSubgraphColor. Return
/// whether we truncated the search. /// whether we truncated the search.
/// ///
bool SelectionDAG::setSubgraphColorHelper(SDNode *N, const char *Color, DenseSet<SDNode *> &visited, bool SelectionDAG::setSubgraphColorHelper(SDNode *N, const char *Color, DenseSet<SDNode *> &visited,
int level, bool &printed) { int level, bool &printed) {
bool hit_limit = false; bool hit_limit = false;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (level >= 20) { if (level >= 20) {
if (!printed) { if (!printed) {
printed = true; printed = true;
DEBUG(dbgs() << "setSubgraphColor hit max level\n"); DEBUG(dbgs() << "setSubgraphColor hit max level\n");
} }
return true; return true;
} }
Show All 12 Lines errs() << "SelectionDAG::setSubgraphColor is only available in debug builds"
<< " on systems with Graphviz or gv!\n"; << " on systems with Graphviz or gv!\n";
#endif #endif
return hit_limit; return hit_limit;
} }
/// setSubgraphColor - Convenience for setting subgraph color attribute. /// setSubgraphColor - Convenience for setting subgraph color attribute.
/// ///
void SelectionDAG::setSubgraphColor(SDNode *N, const char *Color) { void SelectionDAG::setSubgraphColor(SDNode *N, const char *Color) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DenseSet<SDNode *> visited; DenseSet<SDNode *> visited;
bool printed = false; bool printed = false;
if (setSubgraphColorHelper(N, Color, visited, 0, printed)) { if (setSubgraphColorHelper(N, Color, visited, 0, printed)) {
// Visually mark that we hit the limit // Visually mark that we hit the limit
if (strcmp(Color, "red") == 0) { if (strcmp(Color, "red") == 0) {
setSubgraphColorHelper(N, "blue", visited, 0, printed); setSubgraphColorHelper(N, "blue", visited, 0, printed);
} else if (strcmp(Color, "yellow") == 0) { } else if (strcmp(Color, "yellow") == 0) {
setSubgraphColorHelper(N, "green", visited, 0, printed); setSubgraphColorHelper(N, "green", visited, 0, printed);
Show All 40 Lines

lib/CodeGen/SelectionDAG/StatepointLowering.cpp

Show First 20 Lines • Show All 485 Lines • ▼ Show 20 Linesstatic void lowerStatepointMetaArgs(SmallVectorImpl<SDValue> &Ops,
// Lower the deopt and gc arguments for this statepoint. Layout will // Lower the deopt and gc arguments for this statepoint. Layout will
// be: deopt argument length, deopt arguments.., gc arguments... // be: deopt argument length, deopt arguments.., gc arguments...
SmallVector<const Value *, 64> Bases, Ptrs, Relocations; SmallVector<const Value *, 64> Bases, Ptrs, Relocations;
getIncomingStatepointGCValues(Bases, Ptrs, Relocations, StatepointSite, getIncomingStatepointGCValues(Bases, Ptrs, Relocations, StatepointSite,
Builder); Builder);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Check that each of the gc pointer and bases we've gotten out of the // Check that each of the gc pointer and bases we've gotten out of the
// safepoint is something the strategy thinks might be a pointer into the GC // safepoint is something the strategy thinks might be a pointer into the GC
// heap. This is basically just here to help catch errors during statepoint // heap. This is basically just here to help catch errors during statepoint
// insertion. TODO: This should actually be in the Verifier, but we can't get // insertion. TODO: This should actually be in the Verifier, but we can't get
// to the GCStrategy from there (yet). // to the GCStrategy from there (yet).
GCStrategy &S = Builder.GFI->getStrategy(); GCStrategy &S = Builder.GFI->getStrategy();
for (const Value *V : Bases) { for (const Value *V : Bases) {
auto Opt = S.isGCManagedPointer(V); auto Opt = S.isGCManagedPointer(V);
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Linesvoid SelectionDAGBuilder::LowerStatepoint(
// lower it, then reverse engineer the calling sequence. // lower it, then reverse engineer the calling sequence.
NumOfStatepoints++; NumOfStatepoints++;
// Clear state // Clear state
StatepointLowering.startNewStatepoint(*this); StatepointLowering.startNewStatepoint(*this);
ImmutableCallSite CS(ISP.getCallSite()); ImmutableCallSite CS(ISP.getCallSite());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Consistency check. Don't do this for invokes. It would be too // Consistency check. Don't do this for invokes. It would be too
// expensive to preserve this information across different basic blocks // expensive to preserve this information across different basic blocks
if (!CS.isInvoke()) { if (!CS.isInvoke()) {
for (const User *U : CS->users()) { for (const User *U : CS->users()) {
const CallInst *Call = cast<CallInst>(U); const CallInst *Call = cast<CallInst>(U);
if (isGCRelocate(Call)) if (isGCRelocate(Call))
StatepointLowering.scheduleRelocCall(*Call); StatepointLowering.scheduleRelocCall(*Call);
} }
} }
#endif #endif
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If this is a malformed statepoint, report it early to simplify debugging. // If this is a malformed statepoint, report it early to simplify debugging.
// This should catch any IR level mistake that's made when constructing or // This should catch any IR level mistake that's made when constructing or
// transforming statepoints. // transforming statepoints.
ISP.verify(); ISP.verify();
// Check that the associated GCStrategy expects to encounter statepoints. // Check that the associated GCStrategy expects to encounter statepoints.
assert(GFI->getStrategy().useStatepoints() && assert(GFI->getStrategy().useStatepoints() &&
"GCStrategy does not expect to encounter statepoints"); "GCStrategy does not expect to encounter statepoints");
▲ Show 20 Lines • Show All 183 Lines • ▼ Show 20 Linesvoid SelectionDAGBuilder::visitGCResult(const CallInst &CI) {
} else { } else {
setValue(&CI, getValue(I)); setValue(&CI, getValue(I));
} }
} }
void SelectionDAGBuilder::visitGCRelocate(const CallInst &CI) { void SelectionDAGBuilder::visitGCRelocate(const CallInst &CI) {
GCRelocateOperands RelocateOpers(&CI); GCRelocateOperands RelocateOpers(&CI);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Consistency check // Consistency check
// We skip this check for invoke statepoints. It would be too expensive to // We skip this check for invoke statepoints. It would be too expensive to
// preserve validation info through different basic blocks. // preserve validation info through different basic blocks.
if (!RelocateOpers.isTiedToInvoke()) { if (!RelocateOpers.isTiedToInvoke()) {
StatepointLowering.relocCallVisited(CI); StatepointLowering.relocCallVisited(CI);
} }
#endif #endif
Show All 36 Lines

lib/CodeGen/SlotIndexes.cpp

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Linesvoid SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
for (MachineBasicBlock::iterator I = End; I != Begin;) { for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I; --I;
MachineInstr *MI = I; MachineInstr *MI = I;
if (!MI->isDebugValue() && mi2iMap.find(MI) == mi2iMap.end()) if (!MI->isDebugValue() && mi2iMap.find(MI) == mi2iMap.end())
insertMachineInstrInMaps(MI); insertMachineInstrInMaps(MI);
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void SlotIndexes::dump() const { void SlotIndexes::dump() const {
for (IndexList::const_iterator itr = indexList.begin(); for (IndexList::const_iterator itr = indexList.begin();
itr != indexList.end(); ++itr) { itr != indexList.end(); ++itr) {
dbgs() << itr->getIndex() << " "; dbgs() << itr->getIndex() << " ";
if (itr->getInstr()) { if (itr->getInstr()) {
dbgs() << *itr->getInstr(); dbgs() << *itr->getInstr();
} else { } else {
Show All 10 Lines
// Print a SlotIndex to a raw_ostream. // Print a SlotIndex to a raw_ostream.
void SlotIndex::print(raw_ostream &os) const { void SlotIndex::print(raw_ostream &os) const {
if (isValid()) if (isValid())
os << listEntry()->getIndex() << "Berd"[getSlot()]; os << listEntry()->getIndex() << "Berd"[getSlot()];
else else
os << "invalid"; os << "invalid";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
// Dump a SlotIndex to stderr. // Dump a SlotIndex to stderr.
void SlotIndex::dump() const { void SlotIndex::dump() const {
print(dbgs()); print(dbgs());
dbgs() << "\n"; dbgs() << "\n";
} }
#endif #endif

lib/CodeGen/SplitKit.cpp

Show First 20 Lines • Show All 337 Lines • ▼ Show 20 Lines if (SpillMode)
LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
&LIS.getVNInfoAllocator()); &LIS.getVNInfoAllocator());
// We don't need an AliasAnalysis since we will only be performing // We don't need an AliasAnalysis since we will only be performing
// cheap-as-a-copy remats anyway. // cheap-as-a-copy remats anyway.
Edit->anyRematerializable(nullptr); Edit->anyRematerializable(nullptr);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void SplitEditor::dump() const { void SplitEditor::dump() const {
if (RegAssign.empty()) { if (RegAssign.empty()) {
dbgs() << " empty\n"; dbgs() << " empty\n";
return; return;
} }
for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I) for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value(); dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
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lib/CodeGen/StackColoring.cpp

Show First 20 Lines • Show All 545 Lines • ▼ Show 20 Lines for (MachineInstr &I : BB) {
// In a debug build, check that the instruction that we are modifying is // In a debug build, check that the instruction that we are modifying is
// inside the expected live range. If the instruction is not inside // inside the expected live range. If the instruction is not inside
// the calculated range then it means that the alloca usage moved // the calculated range then it means that the alloca usage moved
// outside of the lifetime markers, or that the user has a bug. // outside of the lifetime markers, or that the user has a bug.
// NOTE: Alloca address calculations which happen outside the lifetime // NOTE: Alloca address calculations which happen outside the lifetime
// zone are are okay, despite the fact that we don't have a good way // zone are are okay, despite the fact that we don't have a good way
// for validating all of the usages of the calculation. // for validating all of the usages of the calculation.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool TouchesMemory = I.mayLoad() || I.mayStore(); bool TouchesMemory = I.mayLoad() || I.mayStore();
// If we *don't* protect the user from escaped allocas, don't bother // If we *don't* protect the user from escaped allocas, don't bother
// validating the instructions. // validating the instructions.
if (!I.isDebugValue() && TouchesMemory && ProtectFromEscapedAllocas) { if (!I.isDebugValue() && TouchesMemory && ProtectFromEscapedAllocas) {
SlotIndex Index = Indexes->getInstructionIndex(&I); SlotIndex Index = Indexes->getInstructionIndex(&I);
const LiveInterval *Interval = &*Intervals[FromSlot]; const LiveInterval *Interval = &*Intervals[FromSlot];
assert(Interval->find(Index) != Interval->end() && assert(Interval->find(Index) != Interval->end() &&
"Found instruction usage outside of live range."); "Found instruction usage outside of live range.");
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lib/CodeGen/StackMaps.cpp

Show All 34 Lines
const char *StackMaps::WSMP = "Stack Maps: "; const char *StackMaps::WSMP = "Stack Maps: ";
PatchPointOpers::PatchPointOpers(const MachineInstr *MI) PatchPointOpers::PatchPointOpers(const MachineInstr *MI)
: MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
!MI->getOperand(0).isImplicit()), !MI->getOperand(0).isImplicit()),
IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() ==
CallingConv::AnyReg) { CallingConv::AnyReg) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned CheckStartIdx = 0, e = MI->getNumOperands(); unsigned CheckStartIdx = 0, e = MI->getNumOperands();
while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() && while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
MI->getOperand(CheckStartIdx).isDef() && MI->getOperand(CheckStartIdx).isDef() &&
!MI->getOperand(CheckStartIdx).isImplicit()) !MI->getOperand(CheckStartIdx).isImplicit())
++CheckStartIdx; ++CheckStartIdx;
assert(getMetaIdx() == CheckStartIdx && assert(getMetaIdx() == CheckStartIdx &&
"Unexpected additional definition in Patchpoint intrinsic."); "Unexpected additional definition in Patchpoint intrinsic.");
▲ Show 20 Lines • Show All 302 Lines • ▼ Show 20 Linesvoid StackMaps::recordPatchPoint(const MachineInstr &MI) {
PatchPointOpers opers(&MI); PatchPointOpers opers(&MI);
int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm(); int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
auto MOI = std::next(MI.operands_begin(), opers.getStackMapStartIdx()); auto MOI = std::next(MI.operands_begin(), opers.getStackMapStartIdx());
recordStackMapOpers(MI, ID, MOI, MI.operands_end(), recordStackMapOpers(MI, ID, MOI, MI.operands_end(),
opers.isAnyReg() && opers.hasDef()); opers.isAnyReg() && opers.hasDef());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// verify anyregcc // verify anyregcc
auto &Locations = CSInfos.back().Locations; auto &Locations = CSInfos.back().Locations;
if (opers.isAnyReg()) { if (opers.isAnyReg()) {
unsigned NArgs = opers.getMetaOper(PatchPointOpers::NArgPos).getImm(); unsigned NArgs = opers.getMetaOper(PatchPointOpers::NArgPos).getImm();
for (unsigned i = 0, e = (opers.hasDef() ? NArgs + 1 : NArgs); i != e; ++i) for (unsigned i = 0, e = (opers.hasDef() ? NArgs + 1 : NArgs); i != e; ++i)
assert(Locations[i].Type == Location::Register && assert(Locations[i].Type == Location::Register &&
"anyreg arg must be in reg."); "anyreg arg must be in reg.");
} }
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lib/CodeGen/StackSlotColoring.cpp

Show First 20 Lines • Show All 297 Lines • ▼ Show 20 Linesbool StackSlotColoring::ColorSlots(MachineFunction &MF) {
for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) { for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
LiveInterval *li = SSIntervals[i]; LiveInterval *li = SSIntervals[i];
int SS = TargetRegisterInfo::stackSlot2Index(li->reg); int SS = TargetRegisterInfo::stackSlot2Index(li->reg);
li->weight = SlotWeights[SS]; li->weight = SlotWeights[SS];
} }
// Sort them by new weight. // Sort them by new weight.
std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter()); std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i)
DEBUG(SSIntervals[i]->dump()); DEBUG(SSIntervals[i]->dump());
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
#endif #endif
if (!Changed) if (!Changed)
return false; return false;
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lib/CodeGen/TargetInstrInfo.cpp

Show First 20 Lines • Show All 513 Lines • ▼ Show 20 Lines
/// foldMemoryOperand - Same as the previous version except it allows folding /// foldMemoryOperand - Same as the previous version except it allows folding
/// of any load and store from / to any address, not just from a specific /// of any load and store from / to any address, not just from a specific
/// stack slot. /// stack slot.
MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
ArrayRef<unsigned> Ops, ArrayRef<unsigned> Ops,
MachineInstr *LoadMI) const { MachineInstr *LoadMI) const {
assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!"); assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = Ops.size(); i != e; ++i) for (unsigned i = 0, e = Ops.size(); i != e; ++i)
assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
#endif #endif
MachineBasicBlock &MBB = *MI->getParent(); MachineBasicBlock &MBB = *MI->getParent();
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
// Ask the target to do the actual folding. // Ask the target to do the actual folding.
MachineInstr *NewMI = nullptr; MachineInstr *NewMI = nullptr;
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lib/CodeGen/TargetRegisterInfo.cpp

Show First 20 Lines • Show All 323 Lines • ▼ Show 20 Linesbool TargetRegisterInfo::needsStackRealignment(
if (ForceStackAlign || requiresRealignment) { if (ForceStackAlign || requiresRealignment) {
if (canRealignStack(MF)) if (canRealignStack(MF))
return true; return true;
DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n"); DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n");
} }
return false; return false;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void void
TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n";
} }
#endif #endif

lib/CodeGen/TargetSchedule.cpp

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
resolveSchedClass(const MachineInstr *MI) const { resolveSchedClass(const MachineInstr *MI) const {
// Get the definition's scheduling class descriptor from this machine model. // Get the definition's scheduling class descriptor from this machine model.
unsigned SchedClass = MI->getDesc().getSchedClass(); unsigned SchedClass = MI->getDesc().getSchedClass();
const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
if (!SCDesc->isValid()) if (!SCDesc->isValid())
return SCDesc; return SCDesc;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned NIter = 0; unsigned NIter = 0;
#endif #endif
while (SCDesc->isVariant()) { while (SCDesc->isVariant()) {
assert(++NIter < 6 && "Variants are nested deeper than the magic number"); assert(++NIter < 6 && "Variants are nested deeper than the magic number");
SchedClass = STI->resolveSchedClass(SchedClass, MI, this); SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
SCDesc = SchedModel.getSchedClassDesc(SchedClass); SCDesc = SchedModel.getSchedClassDesc(SchedClass);
} }
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines if (DefIdx < SCDesc->NumWriteLatencyEntries) {
unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
return 0; return 0;
return Latency - Advance; return Latency - Advance;
} }
// If DefIdx does not exist in the model (e.g. implicit defs), then return // If DefIdx does not exist in the model (e.g. implicit defs), then return
// unit latency (defaultDefLatency may be too conservative). // unit latency (defaultDefLatency may be too conservative).
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
&& !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
&& SchedModel.isComplete()) { && SchedModel.isComplete()) {
errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
<< *DefMI; << *DefMI;
llvm_unreachable("incomplete machine model"); llvm_unreachable("incomplete machine model");
} }
#endif #endif
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lib/CodeGen/TwoAddressInstructionPass.cpp

Show First 20 Lines • Show All 1,457 Lines • ▼ Show 20 Lines if (RegA == RegB) {
AllUsesCopied = false; AllUsesCopied = false;
continue; continue;
} }
LastCopiedReg = RegA; LastCopiedReg = RegA;
assert(TargetRegisterInfo::isVirtualRegister(RegB) && assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
"cannot make instruction into two-address form"); "cannot make instruction into two-address form");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// First, verify that we don't have a use of "a" in the instruction // First, verify that we don't have a use of "a" in the instruction
// (a = b + a for example) because our transformation will not // (a = b + a for example) because our transformation will not
// work. This should never occur because we are in SSA form. // work. This should never occur because we are in SSA form.
for (unsigned i = 0; i != MI->getNumOperands(); ++i) for (unsigned i = 0; i != MI->getNumOperands(); ++i)
assert(i == DstIdx || assert(i == DstIdx ||
!MI->getOperand(i).isReg() || !MI->getOperand(i).isReg() ||
MI->getOperand(i).getReg() != RegA); MI->getOperand(i).getReg() != RegA);
#endif #endif
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lib/CodeGen/VirtRegMap.cpp

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
<< "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
} }
} }
OS << '\n'; OS << '\n';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void VirtRegMap::dump() const { void VirtRegMap::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VirtRegRewriter // VirtRegRewriter
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 276 Lines • Show Last 20 Lines

lib/CodeGen/WinEHPrepare.cpp

Show First 20 Lines • Show All 565 Lines • ▼ Show 20 Linesvoid WinEHPrepare::identifyEHBlocks(Function &F,
DEBUG({ DEBUG({
dbgs() << "identified the following blocks as EH return points:\n"; dbgs() << "identified the following blocks as EH return points:\n";
for (BasicBlock *BB : EHReturnBlocks) for (BasicBlock *BB : EHReturnBlocks)
dbgs() << " " << BB->getName() << '\n'; dbgs() << " " << BB->getName() << '\n';
}); });
// Join points should not have phis at this point, unless they are a // Join points should not have phis at this point, unless they are a
// landingpad, in which case we will demote their phis later. // landingpad, in which case we will demote their phis later.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (BasicBlock *BB : EHReturnBlocks) for (BasicBlock *BB : EHReturnBlocks)
assert((BB->isLandingPad() || !isa<PHINode>(BB->begin())) && assert((BB->isLandingPad() || !isa<PHINode>(BB->begin())) &&
"non-lpad EH return block has phi"); "non-lpad EH return block has phi");
#endif #endif
// Normal blocks are the blocks reachable from the entry block and all EH // Normal blocks are the blocks reachable from the entry block and all EH
// return points. // return points.
SetVector<BasicBlock *> Worklist; SetVector<BasicBlock *> Worklist;
▲ Show 20 Lines • Show All 2,039 Lines • ▼ Show 20 Lines for (CatchHandler *CH : Handlers) {
HT.Handler = cast<Function>(CH->getHandlerBlockOrFunc()); HT.Handler = cast<Function>(CH->getHandlerBlockOrFunc());
HT.CatchObjRecoverIdx = CH->getExceptionVarIndex(); HT.CatchObjRecoverIdx = CH->getExceptionVarIndex();
TBME.HandlerArray.push_back(HT); TBME.HandlerArray.push_back(HT);
} }
FuncInfo.TryBlockMap.push_back(TBME); FuncInfo.TryBlockMap.push_back(TBME);
} }
static void print_name(const Value *V) { static void print_name(const Value *V) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (!V) { if (!V) {
DEBUG(dbgs() << "null"); DEBUG(dbgs() << "null");
return; return;
} }
if (const auto *F = dyn_cast<Function>(V)) if (const auto *F = dyn_cast<Function>(V))
DEBUG(dbgs() << F->getName()); DEBUG(dbgs() << F->getName());
else else
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lib/ExecutionEngine/ExecutionEngine.cpp

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
void ExecutionEngine::Init(std::unique_ptr<Module> M) { void ExecutionEngine::Init(std::unique_ptr<Module> M) {
CompilingLazily = false; CompilingLazily = false;
GVCompilationDisabled = false; GVCompilationDisabled = false;
SymbolSearchingDisabled = false; SymbolSearchingDisabled = false;
// IR module verification is enabled by default in debug builds, and disabled // IR module verification is enabled by default in debug builds, and disabled
// by default in release builds. // by default in release builds.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VerifyModules = true; VerifyModules = true;
#else #else
VerifyModules = false; VerifyModules = false;
#endif #endif
assert(M && "Module is null?"); assert(M && "Module is null?");
Modules.push_back(std::move(M)); Modules.push_back(std::move(M));
} }
▲ Show 20 Lines • Show All 329 Lines • ▼ Show 20 Lines
} }
void ExecutionEngine::runStaticConstructorsDestructors(bool isDtors) { void ExecutionEngine::runStaticConstructorsDestructors(bool isDtors) {
// Execute global ctors/dtors for each module in the program. // Execute global ctors/dtors for each module in the program.
for (std::unique_ptr<Module> &M : Modules) for (std::unique_ptr<Module> &M : Modules)
runStaticConstructorsDestructors(*M, isDtors); runStaticConstructorsDestructors(*M, isDtors);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// isTargetNullPtr - Return whether the target pointer stored at Loc is null. /// isTargetNullPtr - Return whether the target pointer stored at Loc is null.
static bool isTargetNullPtr(ExecutionEngine *EE, void *Loc) { static bool isTargetNullPtr(ExecutionEngine *EE, void *Loc) {
unsigned PtrSize = EE->getDataLayout().getPointerSize(); unsigned PtrSize = EE->getDataLayout().getPointerSize();
for (unsigned i = 0; i < PtrSize; ++i) for (unsigned i = 0; i < PtrSize; ++i)
if (*(i + (uint8_t*)Loc)) if (*(i + (uint8_t*)Loc))
return false; return false;
return true; return true;
} }
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EngineBuilder::EngineBuilder(std::unique_ptr<Module> M) EngineBuilder::EngineBuilder(std::unique_ptr<Module> M)
: M(std::move(M)), WhichEngine(EngineKind::Either), ErrorStr(nullptr), : M(std::move(M)), WhichEngine(EngineKind::Either), ErrorStr(nullptr),
OptLevel(CodeGenOpt::Default), MemMgr(nullptr), Resolver(nullptr), OptLevel(CodeGenOpt::Default), MemMgr(nullptr), Resolver(nullptr),
RelocModel(Reloc::Default), CMModel(CodeModel::JITDefault), RelocModel(Reloc::Default), CMModel(CodeModel::JITDefault),
UseOrcMCJITReplacement(false) { UseOrcMCJITReplacement(false) {
// IR module verification is enabled by default in debug builds, and disabled // IR module verification is enabled by default in debug builds, and disabled
// by default in release builds. // by default in release builds.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VerifyModules = true; VerifyModules = true;
#else #else
VerifyModules = false; VerifyModules = false;
#endif #endif
} }
EngineBuilder::~EngineBuilder() = default; EngineBuilder::~EngineBuilder() = default;
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lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp

Show All 33 Lines
void RuntimeDyld::LoadedObjectInfo::anchor() {} void RuntimeDyld::LoadedObjectInfo::anchor() {}
namespace llvm { namespace llvm {
void RuntimeDyldImpl::registerEHFrames() {} void RuntimeDyldImpl::registerEHFrames() {}
void RuntimeDyldImpl::deregisterEHFrames() {} void RuntimeDyldImpl::deregisterEHFrames() {}
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static void dumpSectionMemory(const SectionEntry &S, StringRef State) { static void dumpSectionMemory(const SectionEntry &S, StringRef State) {
dbgs() << "----- Contents of section " << S.Name << " " << State << " -----"; dbgs() << "----- Contents of section " << S.Name << " " << State << " -----";
if (S.Address == nullptr) { if (S.Address == nullptr) {
dbgs() << "\n <section not emitted>\n"; dbgs() << "\n <section not emitted>\n";
return; return;
} }
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lib/IR/AttributeImpl.h

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Linesprivate:
// AttributesSet is uniqued, these should not be publicly available. // AttributesSet is uniqued, these should not be publicly available.
void operator=(const AttributeSetImpl &) = delete; void operator=(const AttributeSetImpl &) = delete;
AttributeSetImpl(const AttributeSetImpl &) = delete; AttributeSetImpl(const AttributeSetImpl &) = delete;
public: public:
AttributeSetImpl(LLVMContext &C, AttributeSetImpl(LLVMContext &C,
ArrayRef<std::pair<unsigned, AttributeSetNode *> > Attrs) ArrayRef<std::pair<unsigned, AttributeSetNode *> > Attrs)
: Context(C), NumAttrs(Attrs.size()) { : Context(C), NumAttrs(Attrs.size()) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (Attrs.size() >= 2) { if (Attrs.size() >= 2) {
for (const std::pair<unsigned, AttributeSetNode *> *i = Attrs.begin() + 1, for (const std::pair<unsigned, AttributeSetNode *> *i = Attrs.begin() + 1,
*e = Attrs.end(); *e = Attrs.end();
i != e; ++i) { i != e; ++i) {
assert((i-1)->first <= i->first && "Attribute set not ordered!"); assert((i-1)->first <= i->first && "Attribute set not ordered!");
} }
} }
#endif #endif
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lib/IR/Attributes.cpp

Show First 20 Lines • Show All 626 Lines • ▼ Show 20 Lines
} }
AttributeSet AttributeSet::get(LLVMContext &C, AttributeSet AttributeSet::get(LLVMContext &C,
ArrayRef<std::pair<unsigned, Attribute> > Attrs){ ArrayRef<std::pair<unsigned, Attribute> > Attrs){
// If there are no attributes then return a null AttributesList pointer. // If there are no attributes then return a null AttributesList pointer.
if (Attrs.empty()) if (Attrs.empty())
return AttributeSet(); return AttributeSet();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned i = 0, e = Attrs.size(); i != e; ++i) { for (unsigned i = 0, e = Attrs.size(); i != e; ++i) {
assert((!i || Attrs[i-1].first <= Attrs[i].first) && assert((!i || Attrs[i-1].first <= Attrs[i].first) &&
"Misordered Attributes list!"); "Misordered Attributes list!");
assert(!Attrs[i].second.hasAttribute(Attribute::None) && assert(!Attrs[i].second.hasAttribute(Attribute::None) &&
"Pointless attribute!"); "Pointless attribute!");
} }
#endif #endif
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 LinesAttributeSet AttributeSet::addAttribute(LLVMContext &C, unsigned Index,
return addAttributes(C, Index, AttributeSet::get(C, Index, B)); return addAttributes(C, Index, AttributeSet::get(C, Index, B));
} }
AttributeSet AttributeSet::addAttributes(LLVMContext &C, unsigned Index, AttributeSet AttributeSet::addAttributes(LLVMContext &C, unsigned Index,
AttributeSet Attrs) const { AttributeSet Attrs) const {
if (!pImpl) return Attrs; if (!pImpl) return Attrs;
if (!Attrs.pImpl) return *this; if (!Attrs.pImpl) return *this;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// FIXME it is not obvious how this should work for alignment. For now, say // FIXME it is not obvious how this should work for alignment. For now, say
// we can't change a known alignment. // we can't change a known alignment.
unsigned OldAlign = getParamAlignment(Index); unsigned OldAlign = getParamAlignment(Index);
unsigned NewAlign = Attrs.getParamAlignment(Index); unsigned NewAlign = Attrs.getParamAlignment(Index);
assert((!OldAlign || !NewAlign || OldAlign == NewAlign) && assert((!OldAlign || !NewAlign || OldAlign == NewAlign) &&
"Attempt to change alignment!"); "Attempt to change alignment!");
#endif #endif
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lib/IR/Constants.cpp

Show First 20 Lines • Show All 292 Lines • ▼ Show 20 Lines#include "llvm/IR/Value.def"
// references to the constant by other constants in the constant pool. These // references to the constant by other constants in the constant pool. These
// constants are implicitly dependent on the module that is being deleted, // constants are implicitly dependent on the module that is being deleted,
// but they don't know that. Because we only find out when the CPV is // but they don't know that. Because we only find out when the CPV is
// deleted, we must now notify all of our users (that should only be // deleted, we must now notify all of our users (that should only be
// Constants) that they are, in fact, invalid now and should be deleted. // Constants) that they are, in fact, invalid now and should be deleted.
// //
while (!use_empty()) { while (!use_empty()) {
Value *V = user_back(); Value *V = user_back();
#ifndef NDEBUG // Only in -g mode... #ifndef LLVM_NDEBUG // Only in -g mode...
if (!isa<Constant>(V)) { if (!isa<Constant>(V)) {
dbgs() << "While deleting: " << *this dbgs() << "While deleting: " << *this
<< "\n\nUse still stuck around after Def is destroyed: " << *V << "\n\nUse still stuck around after Def is destroyed: " << *V
<< "\n\n"; << "\n\n";
} }
#endif #endif
assert(isa<Constant>(V) && "References remain to Constant being destroyed"); assert(isa<Constant>(V) && "References remain to Constant being destroyed");
cast<Constant>(V)->destroyConstant(); cast<Constant>(V)->destroyConstant();
▲ Show 20 Lines • Show All 1,382 Lines • ▼ Show 20 LinesConstant *ConstantExpr::getFPCast(Constant *C, Type *Ty) {
if (SrcBits == DstBits) if (SrcBits == DstBits)
return C; // Avoid a useless cast return C; // Avoid a useless cast
Instruction::CastOps opcode = Instruction::CastOps opcode =
(SrcBits > DstBits ? Instruction::FPTrunc : Instruction::FPExt); (SrcBits > DstBits ? Instruction::FPTrunc : Instruction::FPExt);
return getCast(opcode, C, Ty); return getCast(opcode, C, Ty);
} }
Constant *ConstantExpr::getTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isIntOrIntVectorTy() && "Trunc operand must be integer"); assert(C->getType()->isIntOrIntVectorTy() && "Trunc operand must be integer");
assert(Ty->isIntOrIntVectorTy() && "Trunc produces only integral"); assert(Ty->isIntOrIntVectorTy() && "Trunc produces only integral");
assert(C->getType()->getScalarSizeInBits() > Ty->getScalarSizeInBits()&& assert(C->getType()->getScalarSizeInBits() > Ty->getScalarSizeInBits()&&
"SrcTy must be larger than DestTy for Trunc!"); "SrcTy must be larger than DestTy for Trunc!");
return getFoldedCast(Instruction::Trunc, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::Trunc, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getSExt(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getSExt(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isIntOrIntVectorTy() && "SExt operand must be integral"); assert(C->getType()->isIntOrIntVectorTy() && "SExt operand must be integral");
assert(Ty->isIntOrIntVectorTy() && "SExt produces only integer"); assert(Ty->isIntOrIntVectorTy() && "SExt produces only integer");
assert(C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&& assert(C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&&
"SrcTy must be smaller than DestTy for SExt!"); "SrcTy must be smaller than DestTy for SExt!");
return getFoldedCast(Instruction::SExt, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::SExt, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getZExt(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getZExt(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isIntOrIntVectorTy() && "ZEXt operand must be integral"); assert(C->getType()->isIntOrIntVectorTy() && "ZEXt operand must be integral");
assert(Ty->isIntOrIntVectorTy() && "ZExt produces only integer"); assert(Ty->isIntOrIntVectorTy() && "ZExt produces only integer");
assert(C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&& assert(C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&&
"SrcTy must be smaller than DestTy for ZExt!"); "SrcTy must be smaller than DestTy for ZExt!");
return getFoldedCast(Instruction::ZExt, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::ZExt, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isFPOrFPVectorTy() && Ty->isFPOrFPVectorTy() && assert(C->getType()->isFPOrFPVectorTy() && Ty->isFPOrFPVectorTy() &&
C->getType()->getScalarSizeInBits() > Ty->getScalarSizeInBits()&& C->getType()->getScalarSizeInBits() > Ty->getScalarSizeInBits()&&
"This is an illegal floating point truncation!"); "This is an illegal floating point truncation!");
return getFoldedCast(Instruction::FPTrunc, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::FPTrunc, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getFPExtend(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPExtend(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isFPOrFPVectorTy() && Ty->isFPOrFPVectorTy() && assert(C->getType()->isFPOrFPVectorTy() && Ty->isFPOrFPVectorTy() &&
C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&& C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&&
"This is an illegal floating point extension!"); "This is an illegal floating point extension!");
return getFoldedCast(Instruction::FPExt, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::FPExt, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getUIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getUIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isIntOrIntVectorTy() && Ty->isFPOrFPVectorTy() && assert(C->getType()->isIntOrIntVectorTy() && Ty->isFPOrFPVectorTy() &&
"This is an illegal uint to floating point cast!"); "This is an illegal uint to floating point cast!");
return getFoldedCast(Instruction::UIToFP, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::UIToFP, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getSIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getSIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isIntOrIntVectorTy() && Ty->isFPOrFPVectorTy() && assert(C->getType()->isIntOrIntVectorTy() && Ty->isFPOrFPVectorTy() &&
"This is an illegal sint to floating point cast!"); "This is an illegal sint to floating point cast!");
return getFoldedCast(Instruction::SIToFP, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::SIToFP, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getFPToUI(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPToUI(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isFPOrFPVectorTy() && Ty->isIntOrIntVectorTy() && assert(C->getType()->isFPOrFPVectorTy() && Ty->isIntOrIntVectorTy() &&
"This is an illegal floating point to uint cast!"); "This is an illegal floating point to uint cast!");
return getFoldedCast(Instruction::FPToUI, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::FPToUI, C, Ty, OnlyIfReduced);
} }
Constant *ConstantExpr::getFPToSI(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPToSI(Constant *C, Type *Ty, bool OnlyIfReduced) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; bool fromVec = C->getType()->getTypeID() == Type::VectorTyID;
bool toVec = Ty->getTypeID() == Type::VectorTyID; bool toVec = Ty->getTypeID() == Type::VectorTyID;
#endif #endif
assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
assert(C->getType()->isFPOrFPVectorTy() && Ty->isIntOrIntVectorTy() && assert(C->getType()->isFPOrFPVectorTy() && Ty->isIntOrIntVectorTy() &&
"This is an illegal floating point to sint cast!"); "This is an illegal floating point to sint cast!");
return getFoldedCast(Instruction::FPToSI, C, Ty, OnlyIfReduced); return getFoldedCast(Instruction::FPToSI, C, Ty, OnlyIfReduced);
} }
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 LinesConstant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2,
unsigned Flags, Type *OnlyIfReducedTy) { unsigned Flags, Type *OnlyIfReducedTy) {
// Check the operands for consistency first. // Check the operands for consistency first.
assert(Opcode >= Instruction::BinaryOpsBegin && assert(Opcode >= Instruction::BinaryOpsBegin &&
Opcode < Instruction::BinaryOpsEnd && Opcode < Instruction::BinaryOpsEnd &&
"Invalid opcode in binary constant expression"); "Invalid opcode in binary constant expression");
assert(C1->getType() == C2->getType() && assert(C1->getType() == C2->getType() &&
"Operand types in binary constant expression should match"); "Operand types in binary constant expression should match");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
switch (Opcode) { switch (Opcode) {
case Instruction::Add: case Instruction::Add:
case Instruction::Sub: case Instruction::Sub:
case Instruction::Mul: case Instruction::Mul:
assert(C1->getType() == C2->getType() && "Op types should be identical!"); assert(C1->getType() == C2->getType() && "Op types should be identical!");
assert(C1->getType()->isIntOrIntVectorTy() && assert(C1->getType()->isIntOrIntVectorTy() &&
"Tried to create an integer operation on a non-integer type!"); "Tried to create an integer operation on a non-integer type!");
break; break;
▲ Show 20 Lines • Show All 1,205 Lines • Show Last 20 Lines

lib/IR/DIBuilder.cpp

Show First 20 Lines • Show All 561 Lines • ▼ Show 20 LinesDITypeRefArray DIBuilder::getOrCreateTypeArray(ArrayRef<Metadata *> Elements) {
return DITypeRefArray(MDNode::get(VMContext, Elts)); return DITypeRefArray(MDNode::get(VMContext, Elts));
} }
DISubrange *DIBuilder::getOrCreateSubrange(int64_t Lo, int64_t Count) { DISubrange *DIBuilder::getOrCreateSubrange(int64_t Lo, int64_t Count) {
return DISubrange::get(VMContext, Count, Lo); return DISubrange::get(VMContext, Count, Lo);
} }
static void checkGlobalVariableScope(DIScope *Context) { static void checkGlobalVariableScope(DIScope *Context) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (auto *CT = if (auto *CT =
dyn_cast_or_null<DICompositeType>(getNonCompileUnitScope(Context))) dyn_cast_or_null<DICompositeType>(getNonCompileUnitScope(Context)))
assert(CT->getIdentifier().empty() && assert(CT->getIdentifier().empty() &&
"Context of a global variable should not be a type with identifier"); "Context of a global variable should not be a type with identifier");
#endif #endif
} }
DIGlobalVariable *DIBuilder::createGlobalVariable( DIGlobalVariable *DIBuilder::createGlobalVariable(
▲ Show 20 Lines • Show All 330 Lines • Show Last 20 Lines

lib/IR/DebugInfoMetadata.cpp

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
} }
static StringRef getString(const MDString *S) { static StringRef getString(const MDString *S) {
if (S) if (S)
return S->getString(); return S->getString();
return StringRef(); return StringRef();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static bool isCanonical(const MDString *S) { static bool isCanonical(const MDString *S) {
return !S || !S->getString().empty(); return !S || !S->getString().empty();
} }
#endif #endif
GenericDINode *GenericDINode::getImpl(LLVMContext &Context, unsigned Tag, GenericDINode *GenericDINode::getImpl(LLVMContext &Context, unsigned Tag,
MDString *Header, MDString *Header,
ArrayRef<Metadata *> DwarfOps, ArrayRef<Metadata *> DwarfOps,
▲ Show 20 Lines • Show All 387 Lines • Show Last 20 Lines

lib/IR/DebugLoc.cpp

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines if (!Scope)
return DebugLoc(); return DebugLoc();
return DILocation::get(Scope->getContext(), Line, Col, return DILocation::get(Scope->getContext(), Line, Col,
const_cast<MDNode *>(Scope), const_cast<MDNode *>(Scope),
const_cast<MDNode *>(InlinedAt)); const_cast<MDNode *>(InlinedAt));
} }
void DebugLoc::dump() const { void DebugLoc::dump() const {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (!Loc) if (!Loc)
return; return;
dbgs() << getLine(); dbgs() << getLine();
if (getCol() != 0) if (getCol() != 0)
dbgs() << ',' << getCol(); dbgs() << ',' << getCol();
if (DebugLoc InlinedAtDL = DebugLoc(getInlinedAt())) { if (DebugLoc InlinedAtDL = DebugLoc(getInlinedAt())) {
dbgs() << " @ "; dbgs() << " @ ";
Show All 23 Lines

lib/IR/Instructions.cpp

Show First 20 Lines • Show All 222 Lines • ▼ Show 20 Lines
} }
void CallInst::init(FunctionType *FTy, Value *Func, ArrayRef<Value *> Args, void CallInst::init(FunctionType *FTy, Value *Func, ArrayRef<Value *> Args,
const Twine &NameStr) { const Twine &NameStr) {
this->FTy = FTy; this->FTy = FTy;
assert(getNumOperands() == Args.size() + 1 && "NumOperands not set up?"); assert(getNumOperands() == Args.size() + 1 && "NumOperands not set up?");
Op<-1>() = Func; Op<-1>() = Func;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert((Args.size() == FTy->getNumParams() || assert((Args.size() == FTy->getNumParams() ||
(FTy->isVarArg() && Args.size() > FTy->getNumParams())) && (FTy->isVarArg() && Args.size() > FTy->getNumParams())) &&
"Calling a function with bad signature!"); "Calling a function with bad signature!");
for (unsigned i = 0; i != Args.size(); ++i) for (unsigned i = 0; i != Args.size(); ++i)
assert((i >= FTy->getNumParams() || assert((i >= FTy->getNumParams() ||
FTy->getParamType(i) == Args[i]->getType()) && FTy->getParamType(i) == Args[i]->getType()) &&
"Calling a function with a bad signature!"); "Calling a function with a bad signature!");
▲ Show 20 Lines • Show All 259 Lines • ▼ Show 20 Linesvoid InvokeInst::init(FunctionType *FTy, Value *Fn, BasicBlock *IfNormal,
const Twine &NameStr) { const Twine &NameStr) {
this->FTy = FTy; this->FTy = FTy;
assert(getNumOperands() == 3 + Args.size() && "NumOperands not set up?"); assert(getNumOperands() == 3 + Args.size() && "NumOperands not set up?");
Op<-3>() = Fn; Op<-3>() = Fn;
Op<-2>() = IfNormal; Op<-2>() = IfNormal;
Op<-1>() = IfException; Op<-1>() = IfException;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(((Args.size() == FTy->getNumParams()) || assert(((Args.size() == FTy->getNumParams()) ||
(FTy->isVarArg() && Args.size() > FTy->getNumParams())) && (FTy->isVarArg() && Args.size() > FTy->getNumParams())) &&
"Invoking a function with bad signature"); "Invoking a function with bad signature");
for (unsigned i = 0, e = Args.size(); i != e; i++) for (unsigned i = 0, e = Args.size(); i != e; i++)
assert((i >= FTy->getNumParams() || assert((i >= FTy->getNumParams() ||
FTy->getParamType(i) == Args[i]->getType()) && FTy->getParamType(i) == Args[i]->getType()) &&
"Invoking a function with a bad signature!"); "Invoking a function with a bad signature!");
▲ Show 20 Lines • Show All 496 Lines • ▼ Show 20 Lines
BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond, BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
Instruction *InsertBefore) Instruction *InsertBefore)
: TerminatorInst(Type::getVoidTy(IfTrue->getContext()), Instruction::Br, : TerminatorInst(Type::getVoidTy(IfTrue->getContext()), Instruction::Br,
OperandTraits<BranchInst>::op_end(this) - 3, OperandTraits<BranchInst>::op_end(this) - 3,
3, InsertBefore) { 3, InsertBefore) {
Op<-1>() = IfTrue; Op<-1>() = IfTrue;
Op<-2>() = IfFalse; Op<-2>() = IfFalse;
Op<-3>() = Cond; Op<-3>() = Cond;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
AssertOK(); AssertOK();
#endif #endif
} }
BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *InsertAtEnd) BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *InsertAtEnd)
: TerminatorInst(Type::getVoidTy(IfTrue->getContext()), Instruction::Br, : TerminatorInst(Type::getVoidTy(IfTrue->getContext()), Instruction::Br,
OperandTraits<BranchInst>::op_end(this) - 1, OperandTraits<BranchInst>::op_end(this) - 1,
1, InsertAtEnd) { 1, InsertAtEnd) {
assert(IfTrue && "Branch destination may not be null!"); assert(IfTrue && "Branch destination may not be null!");
Op<-1>() = IfTrue; Op<-1>() = IfTrue;
} }
BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond, BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
BasicBlock *InsertAtEnd) BasicBlock *InsertAtEnd)
: TerminatorInst(Type::getVoidTy(IfTrue->getContext()), Instruction::Br, : TerminatorInst(Type::getVoidTy(IfTrue->getContext()), Instruction::Br,
OperandTraits<BranchInst>::op_end(this) - 3, OperandTraits<BranchInst>::op_end(this) - 3,
3, InsertAtEnd) { 3, InsertAtEnd) {
Op<-1>() = IfTrue; Op<-1>() = IfTrue;
Op<-2>() = IfFalse; Op<-2>() = IfFalse;
Op<-3>() = Cond; Op<-3>() = Cond;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
AssertOK(); AssertOK();
#endif #endif
} }
BranchInst::BranchInst(const BranchInst &BI) : BranchInst::BranchInst(const BranchInst &BI) :
TerminatorInst(Type::getVoidTy(BI.getContext()), Instruction::Br, TerminatorInst(Type::getVoidTy(BI.getContext()), Instruction::Br,
OperandTraits<BranchInst>::op_end(this) - BI.getNumOperands(), OperandTraits<BranchInst>::op_end(this) - BI.getNumOperands(),
▲ Show 20 Lines • Show All 864 Lines • ▼ Show 20 Lines
} }
void BinaryOperator::init(BinaryOps iType) { void BinaryOperator::init(BinaryOps iType) {
Value *LHS = getOperand(0), *RHS = getOperand(1); Value *LHS = getOperand(0), *RHS = getOperand(1);
(void)LHS; (void)RHS; // Silence warnings. (void)LHS; (void)RHS; // Silence warnings.
assert(LHS->getType() == RHS->getType() && assert(LHS->getType() == RHS->getType() &&
"Binary operator operand types must match!"); "Binary operator operand types must match!");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
switch (iType) { switch (iType) {
case Add: case Sub: case Add: case Sub:
case Mul: case Mul:
assert(getType() == LHS->getType() && assert(getType() == LHS->getType() &&
"Arithmetic operation should return same type as operands!"); "Arithmetic operation should return same type as operands!");
assert(getType()->isIntOrIntVectorTy() && assert(getType()->isIntOrIntVectorTy() &&
"Tried to create an integer operation on a non-integer type!"); "Tried to create an integer operation on a non-integer type!");
break; break;
▲ Show 20 Lines • Show All 2,014 Lines • Show Last 20 Lines

lib/IR/LLVMContextImpl.cpp

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
/// ///
/// does not cause MDOperand to be transparent. In particular, a bare pointer /// does not cause MDOperand to be transparent. In particular, a bare pointer
/// doesn't get hashed before it's combined, whereas \a MDOperand would. /// doesn't get hashed before it's combined, whereas \a MDOperand would.
static const Metadata *get_hashable_data(const MDOperand &X) { return X.get(); } static const Metadata *get_hashable_data(const MDOperand &X) { return X.get(); }
} }
unsigned MDNodeOpsKey::calculateHash(MDNode *N, unsigned Offset) { unsigned MDNodeOpsKey::calculateHash(MDNode *N, unsigned Offset) {
unsigned Hash = hash_combine_range(N->op_begin() + Offset, N->op_end()); unsigned Hash = hash_combine_range(N->op_begin() + Offset, N->op_end());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
{ {
SmallVector<Metadata *, 8> MDs(N->op_begin() + Offset, N->op_end()); SmallVector<Metadata *, 8> MDs(N->op_begin() + Offset, N->op_end());
unsigned RawHash = calculateHash(MDs); unsigned RawHash = calculateHash(MDs);
assert(Hash == RawHash && assert(Hash == RawHash &&
"Expected hash of MDOperand to equal hash of Metadata*"); "Expected hash of MDOperand to equal hash of Metadata*");
} }
#endif #endif
return Hash; return Hash;
Show All 27 Lines

lib/IR/LegacyPassManager.cpp

Show First 20 Lines • Show All 845 Lines • ▼ Show 20 Linesbool PMDataManager::preserveHigherLevelAnalysis(Pass *P) {
} }
return true; return true;
} }
/// verifyPreservedAnalysis -- Verify analysis preserved by pass P. /// verifyPreservedAnalysis -- Verify analysis preserved by pass P.
void PMDataManager::verifyPreservedAnalysis(Pass *P) { void PMDataManager::verifyPreservedAnalysis(Pass *P) {
// Don't do this unless assertions are enabled. // Don't do this unless assertions are enabled.
#ifdef NDEBUG #ifdef LLVM_NDEBUG
return; return;
#endif #endif
AnalysisUsage *AnUsage = TPM->findAnalysisUsage(P); AnalysisUsage *AnUsage = TPM->findAnalysisUsage(P);
const AnalysisUsage::VectorType &PreservedSet = AnUsage->getPreservedSet(); const AnalysisUsage::VectorType &PreservedSet = AnUsage->getPreservedSet();
// Verify preserved analysis // Verify preserved analysis
for (AnalysisUsage::VectorType::const_iterator I = PreservedSet.begin(), for (AnalysisUsage::VectorType::const_iterator I = PreservedSet.begin(),
E = PreservedSet.end(); I != E; ++I) { E = PreservedSet.end(); I != E; ++I) {
▲ Show 20 Lines • Show All 377 Lines • ▼ Show 20 Linesvoid PMDataManager::addLowerLevelRequiredPass(Pass *P, Pass *RequiredPass) {
// (e.g. dominator info). Pass manager uses on the fly function pass manager // (e.g. dominator info). Pass manager uses on the fly function pass manager
// to provide this on demand. In that case, in Pass manager terminology, // to provide this on demand. In that case, in Pass manager terminology,
// module level pass is requiring lower level analysis info managed by // module level pass is requiring lower level analysis info managed by
// lower level pass manager. // lower level pass manager.
// When Pass manager is not able to order required analysis info, Pass manager // When Pass manager is not able to order required analysis info, Pass manager
// checks whether any lower level manager will be able to provide this // checks whether any lower level manager will be able to provide this
// analysis info on demand or not. // analysis info on demand or not.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Unable to schedule '" << RequiredPass->getPassName(); dbgs() << "Unable to schedule '" << RequiredPass->getPassName();
dbgs() << "' required by '" << P->getPassName() << "'\n"; dbgs() << "' required by '" << P->getPassName() << "'\n";
#endif #endif
llvm_unreachable("Unable to schedule pass"); llvm_unreachable("Unable to schedule pass");
} }
Pass *PMDataManager::getOnTheFlyPass(Pass *P, AnalysisID PI, Function &F) { Pass *PMDataManager::getOnTheFlyPass(Pass *P, AnalysisID PI, Function &F) {
llvm_unreachable("Unable to find on the fly pass"); llvm_unreachable("Unable to find on the fly pass");
▲ Show 20 Lines • Show All 646 Lines • Show Last 20 Lines

lib/IR/Type.cpp

Show First 20 Lines • Show All 739 Lines • ▼ Show 20 LinesPointerType *PointerType::get(Type *EltTy, unsigned AddressSpace) {
if (!Entry) if (!Entry)
Entry = new (CImpl->TypeAllocator) PointerType(EltTy, AddressSpace); Entry = new (CImpl->TypeAllocator) PointerType(EltTy, AddressSpace);
return Entry; return Entry;
} }
PointerType::PointerType(Type *E, unsigned AddrSpace) PointerType::PointerType(Type *E, unsigned AddrSpace)
: SequentialType(PointerTyID, E) { : SequentialType(PointerTyID, E) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const unsigned oldNCT = NumContainedTys; const unsigned oldNCT = NumContainedTys;
#endif #endif
setSubclassData(AddrSpace); setSubclassData(AddrSpace);
// Check for miscompile. PR11652. // Check for miscompile. PR11652.
assert(oldNCT == NumContainedTys && "bitfield written out of bounds?"); assert(oldNCT == NumContainedTys && "bitfield written out of bounds?");
} }
PointerType *Type::getPointerTo(unsigned addrs) const { PointerType *Type::getPointerTo(unsigned addrs) const {
Show All 11 Lines

lib/IR/Value.cpp

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
Value::~Value() { Value::~Value() {
// Notify all ValueHandles (if present) that this value is going away. // Notify all ValueHandles (if present) that this value is going away.
if (HasValueHandle) if (HasValueHandle)
ValueHandleBase::ValueIsDeleted(this); ValueHandleBase::ValueIsDeleted(this);
if (isUsedByMetadata()) if (isUsedByMetadata())
ValueAsMetadata::handleDeletion(this); ValueAsMetadata::handleDeletion(this);
#ifndef NDEBUG // Only in -g mode... #ifndef LLVM_NDEBUG // Only in -g mode...
// Check to make sure that there are no uses of this value that are still // Check to make sure that there are no uses of this value that are still
// around when the value is destroyed. If there are, then we have a dangling // around when the value is destroyed. If there are, then we have a dangling
// reference and something is wrong. This code is here to print out where // reference and something is wrong. This code is here to print out where
// the value is still being referenced. // the value is still being referenced.
// //
if (!use_empty()) { if (!use_empty()) {
dbgs() << "While deleting: " << *VTy << " %" << getName() << "\n"; dbgs() << "While deleting: " << *VTy << " %" << getName() << "\n";
for (auto *U : users()) for (auto *U : users())
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Linesvoid Value::takeName(Value *V) {
setValueName(V->getValueName()); setValueName(V->getValueName());
V->setValueName(nullptr); V->setValueName(nullptr);
getValueName()->setValue(this); getValueName()->setValue(this);
if (ST) if (ST)
ST->reinsertValue(this); ST->reinsertValue(this);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static bool contains(SmallPtrSetImpl<ConstantExpr *> &Cache, ConstantExpr *Expr, static bool contains(SmallPtrSetImpl<ConstantExpr *> &Cache, ConstantExpr *Expr,
Constant *C) { Constant *C) {
if (!Cache.insert(Expr).second) if (!Cache.insert(Expr).second)
return false; return false;
for (auto &O : Expr->operands()) { for (auto &O : Expr->operands()) {
if (O == C) if (O == C)
return true; return true;
▲ Show 20 Lines • Show All 348 Lines • ▼ Show 20 Lines case Callback:
// Forward to the subclass's implementation. // Forward to the subclass's implementation.
static_cast<CallbackVH*>(Entry)->deleted(); static_cast<CallbackVH*>(Entry)->deleted();
break; break;
} }
} }
// All callbacks, weak references, and assertingVHs should be dropped by now. // All callbacks, weak references, and assertingVHs should be dropped by now.
if (V->HasValueHandle) { if (V->HasValueHandle) {
#ifndef NDEBUG // Only in +Asserts mode... #ifndef LLVM_NDEBUG // Only in +Asserts mode...
dbgs() << "While deleting: " << *V->getType() << " %" << V->getName() dbgs() << "While deleting: " << *V->getType() << " %" << V->getName()
<< "\n"; << "\n";
if (pImpl->ValueHandles[V]->getKind() == Assert) if (pImpl->ValueHandles[V]->getKind() == Assert)
llvm_unreachable("An asserting value handle still pointed to this" llvm_unreachable("An asserting value handle still pointed to this"
" value!"); " value!");
#endif #endif
llvm_unreachable("All references to V were not removed?"); llvm_unreachable("All references to V were not removed?");
Show All 40 Lines case Weak:
break; break;
case Callback: case Callback:
// Forward to the subclass's implementation. // Forward to the subclass's implementation.
static_cast<CallbackVH*>(Entry)->allUsesReplacedWith(New); static_cast<CallbackVH*>(Entry)->allUsesReplacedWith(New);
break; break;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If any new tracking or weak value handles were added while processing the // If any new tracking or weak value handles were added while processing the
// list, then complain about it now. // list, then complain about it now.
if (Old->HasValueHandle) if (Old->HasValueHandle)
for (Entry = pImpl->ValueHandles[Old]; Entry; Entry = Entry->Next) for (Entry = pImpl->ValueHandles[Old]; Entry; Entry = Entry->Next)
switch (Entry->getKind()) { switch (Entry->getKind()) {
case Tracking: case Tracking:
case Weak: case Weak:
dbgs() << "After RAUW from " << *Old->getType() << " %" dbgs() << "After RAUW from " << *Old->getType() << " %"
Show All 12 Lines

lib/IR/ValueSymbolTable.cpp

Show All 17 Lines
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "valuesymtab" #define DEBUG_TYPE "valuesymtab"
// Class destructor // Class destructor
ValueSymbolTable::~ValueSymbolTable() { ValueSymbolTable::~ValueSymbolTable() {
#ifndef NDEBUG // Only do this in -g mode... #ifndef LLVM_NDEBUG // Only do this in -g mode...
for (iterator VI = vmap.begin(), VE = vmap.end(); VI != VE; ++VI) for (iterator VI = vmap.begin(), VE = vmap.end(); VI != VE; ++VI)
dbgs() << "Value still in symbol table! Type = '" dbgs() << "Value still in symbol table! Type = '"
<< *VI->getValue()->getType() << "' Name = '" << *VI->getValue()->getType() << "' Name = '"
<< VI->getKeyData() << "'\n"; << VI->getKeyData() << "'\n";
assert(vmap.empty() && "Values remain in symbol table!"); assert(vmap.empty() && "Values remain in symbol table!");
#endif #endif
} }
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

lib/Linker/LinkModules.cpp

Show First 20 Lines • Show All 254 Lines • ▼ Show 20 LinesType *TypeMapTy::get(Type *Ty, SmallPtrSet<StructType *, 8> &Visited) {
// If we already have an entry for this type, return it. // If we already have an entry for this type, return it.
Type **Entry = &MappedTypes[Ty]; Type **Entry = &MappedTypes[Ty];
if (*Entry) if (*Entry)
return *Entry; return *Entry;
// These are types that LLVM itself will unique. // These are types that LLVM itself will unique.
bool IsUniqued = !isa<StructType>(Ty) || cast<StructType>(Ty)->isLiteral(); bool IsUniqued = !isa<StructType>(Ty) || cast<StructType>(Ty)->isLiteral();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (!IsUniqued) { if (!IsUniqued) {
for (auto &Pair : MappedTypes) { for (auto &Pair : MappedTypes) {
assert(!(Pair.first != Ty && Pair.second == Ty) && assert(!(Pair.first != Ty && Pair.second == Ty) &&
"mapping to a source type"); "mapping to a source type");
} }
} }
#endif #endif
▲ Show 20 Lines • Show All 1,545 Lines • Show Last 20 Lines

lib/MC/MCAsmStreamer.cpp

Show First 20 Lines • Show All 314 Lines • ▼ Show 20 Linesvoid MCAsmStreamer::EmitLabel(MCSymbol *Symbol) {
OS << MAI->getLabelSuffix(); OS << MAI->getLabelSuffix();
EmitEOL(); EmitEOL();
} }
void MCAsmStreamer::EmitLOHDirective(MCLOHType Kind, const MCLOHArgs &Args) { void MCAsmStreamer::EmitLOHDirective(MCLOHType Kind, const MCLOHArgs &Args) {
StringRef str = MCLOHIdToName(Kind); StringRef str = MCLOHIdToName(Kind);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
int NbArgs = MCLOHIdToNbArgs(Kind); int NbArgs = MCLOHIdToNbArgs(Kind);
assert(NbArgs != -1 && ((size_t)NbArgs) == Args.size() && "Malformed LOH!"); assert(NbArgs != -1 && ((size_t)NbArgs) == Args.size() && "Malformed LOH!");
assert(str != "" && "Invalid LOH name"); assert(str != "" && "Invalid LOH name");
#endif #endif
OS << "\t" << MCLOHDirectiveName() << " " << str << "\t"; OS << "\t" << MCLOHDirectiveName() << " " << str << "\t";
bool IsFirst = true; bool IsFirst = true;
for (MCLOHArgs::const_iterator It = Args.begin(), EndIt = Args.end(); for (MCLOHArgs::const_iterator It = Args.begin(), EndIt = Args.end();
▲ Show 20 Lines • Show All 1,052 Lines • Show Last 20 Lines

lib/MC/MCAssembler.cpp

Show First 20 Lines • Show All 1,116 Lines • ▼ Show 20 Linesraw_ostream &operator<<(raw_ostream &OS, const MCFixup &AF) {
OS << "<MCFixup" << " Offset:" << AF.getOffset() OS << "<MCFixup" << " Offset:" << AF.getOffset()
<< " Value:" << *AF.getValue() << " Value:" << *AF.getValue()
<< " Kind:" << AF.getKind() << ">"; << " Kind:" << AF.getKind() << ">";
return OS; return OS;
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCFragment::dump() { void MCFragment::dump() {
raw_ostream &OS = llvm::errs(); raw_ostream &OS = llvm::errs();
OS << "<"; OS << "<";
switch (getKind()) { switch (getKind()) {
case MCFragment::FT_Align: OS << "MCAlignFragment"; break; case MCFragment::FT_Align: OS << "MCAlignFragment"; break;
case MCFragment::FT_Data: OS << "MCDataFragment"; break; case MCFragment::FT_Data: OS << "MCDataFragment"; break;
case MCFragment::FT_CompactEncodedInst: case MCFragment::FT_CompactEncodedInst:
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lib/MC/MCExpr.cpp

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines case MCExpr::Binary: {
} }
return; return;
} }
} }
llvm_unreachable("Invalid expression kind!"); llvm_unreachable("Invalid expression kind!");
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCExpr::dump() const { void MCExpr::dump() const {
dbgs() << *this; dbgs() << *this;
dbgs() << '\n'; dbgs() << '\n';
} }
#endif #endif
/* *** */ /* *** */
▲ Show 20 Lines • Show All 672 Lines • Show Last 20 Lines

lib/MC/MCInst.cpp

Show All 26 Lines else if (isExpr()) {
OS << "Expr:(" << *getExpr() << ")"; OS << "Expr:(" << *getExpr() << ")";
} else if (isInst()) { } else if (isInst()) {
OS << "Inst:(" << *getInst() << ")"; OS << "Inst:(" << *getInst() << ")";
} else } else
OS << "UNDEFINED"; OS << "UNDEFINED";
OS << ">"; OS << ">";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCOperand::dump() const { void MCOperand::dump() const {
print(dbgs()); print(dbgs());
dbgs() << "\n"; dbgs() << "\n";
} }
#endif #endif
void MCInst::print(raw_ostream &OS) const { void MCInst::print(raw_ostream &OS) const {
OS << "<MCInst " << getOpcode(); OS << "<MCInst " << getOpcode();
Show All 14 Linesvoid MCInst::dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer,
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
OS << Separator; OS << Separator;
getOperand(i).print(OS); getOperand(i).print(OS);
} }
OS << ">"; OS << ">";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCInst::dump() const { void MCInst::dump() const {
print(dbgs()); print(dbgs());
dbgs() << "\n"; dbgs() << "\n";
} }
#endif #endif

lib/MC/MCLabel.cpp

Show All 10 Lines
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
void MCLabel::print(raw_ostream &OS) const { void MCLabel::print(raw_ostream &OS) const {
OS << '"' << getInstance() << '"'; OS << '"' << getInstance() << '"';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCLabel::dump() const { void MCLabel::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif

lib/MC/MCObjectStreamer.cpp

Show First 20 Lines • Show All 274 Lines • ▼ Show 20 Linesvoid MCObjectStreamer::EmitInstToFragment(const MCInst &Inst,
SmallString<128> Code; SmallString<128> Code;
raw_svector_ostream VecOS(Code); raw_svector_ostream VecOS(Code);
getAssembler().getEmitter().encodeInstruction(Inst, VecOS, IF->getFixups(), getAssembler().getEmitter().encodeInstruction(Inst, VecOS, IF->getFixups(),
STI); STI);
VecOS.flush(); VecOS.flush();
IF->getContents().append(Code.begin(), Code.end()); IF->getContents().append(Code.begin(), Code.end());
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static const char *const BundlingNotImplementedMsg = static const char *const BundlingNotImplementedMsg =
"Aligned bundling is not implemented for this object format"; "Aligned bundling is not implemented for this object format";
#endif #endif
void MCObjectStreamer::EmitBundleAlignMode(unsigned AlignPow2) { void MCObjectStreamer::EmitBundleAlignMode(unsigned AlignPow2) {
llvm_unreachable(BundlingNotImplementedMsg); llvm_unreachable(BundlingNotImplementedMsg);
} }
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

lib/MC/MCParser/MCAsmParser.cpp

Show All 38 Lines
} }
bool MCAsmParser::parseExpression(const MCExpr *&Res) { bool MCAsmParser::parseExpression(const MCExpr *&Res) {
SMLoc L; SMLoc L;
return parseExpression(Res, L); return parseExpression(Res, L);
} }
void MCParsedAsmOperand::dump() const { void MCParsedAsmOperand::dump() const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
dbgs() << " " << *this; dbgs() << " " << *this;
#endif #endif
} }

lib/MC/MCSection.cpp

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines if (!ExactMatch && Subsection != 0) {
SubsectionFragmentMap.insert(MI, std::make_pair(Subsection, F)); SubsectionFragmentMap.insert(MI, std::make_pair(Subsection, F));
getFragmentList().insert(IP, F); getFragmentList().insert(IP, F);
F->setParent(this); F->setParent(this);
} }
return IP; return IP;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCSection::dump() { void MCSection::dump() {
raw_ostream &OS = llvm::errs(); raw_ostream &OS = llvm::errs();
OS << "<MCSection"; OS << "<MCSection";
OS << " Fragments:[\n "; OS << " Fragments:[\n ";
for (auto it = begin(), ie = end(); it != ie; ++it) { for (auto it = begin(), ie = end(); it != ie; ++it) {
if (it != begin()) if (it != begin())
OS << ",\n "; OS << ",\n ";
Show All 13 Lines

lib/MC/MCSubtargetInfo.cpp

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 LinesFeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures); FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
return FeatureBits; return FeatureBits;
} }
const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
assert(ProcSchedModels && "Processor machine model not available!"); assert(ProcSchedModels && "Processor machine model not available!");
unsigned NumProcs = ProcDesc.size(); unsigned NumProcs = ProcDesc.size();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (size_t i = 1; i < NumProcs; i++) { for (size_t i = 1; i < NumProcs; i++) {
assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 && assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
"Processor machine model table is not sorted"); "Processor machine model table is not sorted");
} }
#endif #endif
// Find entry // Find entry
const SubtargetInfoKV *Found = const SubtargetInfoKV *Found =
Show All 23 Lines

lib/MC/MCSymbol.cpp

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines for (char C : Name) {
else if (C == '"') else if (C == '"')
OS << "\\\""; OS << "\\\"";
else else
OS << C; OS << C;
} }
OS << '"'; OS << '"';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCSymbol::dump() const { dbgs() << *this; } void MCSymbol::dump() const { dbgs() << *this; }
#endif #endif

lib/MC/MCValue.cpp

Show All 31 Lines if (getSymB()) {
OS << " - "; OS << " - ";
OS << *getSymB(); OS << *getSymB();
} }
if (getConstant()) if (getConstant())
OS << " + " << getConstant(); OS << " + " << getConstant();
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MCValue::dump() const { void MCValue::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
MCSymbolRefExpr::VariantKind MCValue::getAccessVariant() const { MCSymbolRefExpr::VariantKind MCValue::getAccessVariant() const {
const MCSymbolRefExpr *B = getSymB(); const MCSymbolRefExpr *B = getSymB();
if (B) { if (B) {
Show All 13 Lines

lib/MC/MachObjectWriter.cpp

Show First 20 Lines • Show All 894 Lines • ▼ Show 20 Lines DEBUG(dbgs() << "data in code region-- kind: " << Data->Kind
<< "\n"); << "\n");
write32(Start); write32(Start);
write16(End - Start); write16(End - Start);
write16(Data->Kind); write16(Data->Kind);
} }
// Write out the loh commands, if there is one. // Write out the loh commands, if there is one.
if (LOHSize) { if (LOHSize) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned Start = OS.tell(); unsigned Start = OS.tell();
#endif #endif
Asm.getLOHContainer().emit(*this, Layout); Asm.getLOHContainer().emit(*this, Layout);
// Pad to a multiple of the pointer size. // Pad to a multiple of the pointer size.
writeBytes("", OffsetToAlignment(LOHRawSize, is64Bit() ? 8 : 4)); writeBytes("", OffsetToAlignment(LOHRawSize, is64Bit() ? 8 : 4));
assert(OS.tell() - Start == LOHSize); assert(OS.tell() - Start == LOHSize);
} }
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

lib/MC/SubtargetFeature.cpp

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
FeatureBitset FeatureBitset
SubtargetFeatures::getFeatureBits(StringRef CPU, SubtargetFeatures::getFeatureBits(StringRef CPU,
ArrayRef<SubtargetFeatureKV> CPUTable, ArrayRef<SubtargetFeatureKV> CPUTable,
ArrayRef<SubtargetFeatureKV> FeatureTable) { ArrayRef<SubtargetFeatureKV> FeatureTable) {
if (CPUTable.empty() || FeatureTable.empty()) if (CPUTable.empty() || FeatureTable.empty())
return FeatureBitset(); return FeatureBitset();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (size_t i = 1, e = CPUTable.size(); i != e; ++i) { for (size_t i = 1, e = CPUTable.size(); i != e; ++i) {
assert(strcmp(CPUTable[i - 1].Key, CPUTable[i].Key) < 0 && assert(strcmp(CPUTable[i - 1].Key, CPUTable[i].Key) < 0 &&
"CPU table is not sorted"); "CPU table is not sorted");
} }
for (size_t i = 1, e = FeatureTable.size(); i != e; ++i) { for (size_t i = 1, e = FeatureTable.size(); i != e; ++i) {
assert(strcmp(FeatureTable[i - 1].Key, FeatureTable[i].Key) < 0 && assert(strcmp(FeatureTable[i - 1].Key, FeatureTable[i].Key) < 0 &&
"CPU features table is not sorted"); "CPU features table is not sorted");
} }
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
/// print - Print feature string. /// print - Print feature string.
/// ///
void SubtargetFeatures::print(raw_ostream &OS) const { void SubtargetFeatures::print(raw_ostream &OS) const {
for (auto &F : Features) for (auto &F : Features)
OS << F << " "; OS << F << " ";
OS << "\n"; OS << "\n";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dump - Dump feature info. /// dump - Dump feature info.
/// ///
void SubtargetFeatures::dump() const { void SubtargetFeatures::dump() const {
print(dbgs()); print(dbgs());
} }
#endif #endif
/// Adds the default features for the specified target triple. /// Adds the default features for the specified target triple.
Show All 17 Lines

lib/Object/COFFObjectFile.cpp

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
} }
template <typename coff_symbol_type> template <typename coff_symbol_type>
const coff_symbol_type *COFFObjectFile::toSymb(DataRefImpl Ref) const { const coff_symbol_type *COFFObjectFile::toSymb(DataRefImpl Ref) const {
const coff_symbol_type *Addr = const coff_symbol_type *Addr =
reinterpret_cast<const coff_symbol_type *>(Ref.p); reinterpret_cast<const coff_symbol_type *>(Ref.p);
assert(!checkOffset(Data, uintptr_t(Addr), sizeof(*Addr))); assert(!checkOffset(Data, uintptr_t(Addr), sizeof(*Addr)));
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify that the symbol points to a valid entry in the symbol table. // Verify that the symbol points to a valid entry in the symbol table.
uintptr_t Offset = uintptr_t(Addr) - uintptr_t(base()); uintptr_t Offset = uintptr_t(Addr) - uintptr_t(base());
assert((Offset - getPointerToSymbolTable()) % sizeof(coff_symbol_type) == 0 && assert((Offset - getPointerToSymbolTable()) % sizeof(coff_symbol_type) == 0 &&
"Symbol did not point to the beginning of a symbol"); "Symbol did not point to the beginning of a symbol");
#endif #endif
return Addr; return Addr;
} }
const coff_section *COFFObjectFile::toSec(DataRefImpl Ref) const { const coff_section *COFFObjectFile::toSec(DataRefImpl Ref) const {
const coff_section *Addr = reinterpret_cast<const coff_section*>(Ref.p); const coff_section *Addr = reinterpret_cast<const coff_section*>(Ref.p);
# ifndef NDEBUG # ifndef LLVM_NDEBUG
// Verify that the section points to a valid entry in the section table. // Verify that the section points to a valid entry in the section table.
if (Addr < SectionTable || Addr >= (SectionTable + getNumberOfSections())) if (Addr < SectionTable || Addr >= (SectionTable + getNumberOfSections()))
report_fatal_error("Section was outside of section table."); report_fatal_error("Section was outside of section table.");
uintptr_t Offset = uintptr_t(Addr) - uintptr_t(SectionTable); uintptr_t Offset = uintptr_t(Addr) - uintptr_t(SectionTable);
assert(Offset % sizeof(coff_section) == 0 && assert(Offset % sizeof(coff_section) == 0 &&
"Section did not point to the beginning of a section"); "Section did not point to the beginning of a section");
# endif # endif
▲ Show 20 Lines • Show All 753 Lines • ▼ Show 20 Lines
ArrayRef<uint8_t> ArrayRef<uint8_t>
COFFObjectFile::getSymbolAuxData(COFFSymbolRef Symbol) const { COFFObjectFile::getSymbolAuxData(COFFSymbolRef Symbol) const {
const uint8_t *Aux = nullptr; const uint8_t *Aux = nullptr;
size_t SymbolSize = getSymbolTableEntrySize(); size_t SymbolSize = getSymbolTableEntrySize();
if (Symbol.getNumberOfAuxSymbols() > 0) { if (Symbol.getNumberOfAuxSymbols() > 0) {
// AUX data comes immediately after the symbol in COFF // AUX data comes immediately after the symbol in COFF
Aux = reinterpret_cast<const uint8_t *>(Symbol.getRawPtr()) + SymbolSize; Aux = reinterpret_cast<const uint8_t *>(Symbol.getRawPtr()) + SymbolSize;
# ifndef NDEBUG # ifndef LLVM_NDEBUG
// Verify that the Aux symbol points to a valid entry in the symbol table. // Verify that the Aux symbol points to a valid entry in the symbol table.
uintptr_t Offset = uintptr_t(Aux) - uintptr_t(base()); uintptr_t Offset = uintptr_t(Aux) - uintptr_t(base());
if (Offset < getPointerToSymbolTable() || if (Offset < getPointerToSymbolTable() ||
Offset >= Offset >=
getPointerToSymbolTable() + (getNumberOfSymbols() * SymbolSize)) getPointerToSymbolTable() + (getNumberOfSymbols() * SymbolSize))
report_fatal_error("Aux Symbol data was outside of symbol table."); report_fatal_error("Aux Symbol data was outside of symbol table.");
assert((Offset - getPointerToSymbolTable()) % SymbolSize == 0 && assert((Offset - getPointerToSymbolTable()) % SymbolSize == 0 &&
▲ Show 20 Lines • Show All 537 Lines • Show Last 20 Lines

lib/Option/OptTable.cpp

Show All 40 Lines if (a == '\0') // A is a prefix of B.
return 1; return 1;
if (b == '\0') // B is a prefix of A. if (b == '\0') // B is a prefix of A.
return -1; return -1;
// Otherwise lexicographic. // Otherwise lexicographic.
return (a < b) ? -1 : 1; return (a < b) ? -1 : 1;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static int StrCmpOptionName(const char *A, const char *B) { static int StrCmpOptionName(const char *A, const char *B) {
if (int N = StrCmpOptionNameIgnoreCase(A, B)) if (int N = StrCmpOptionNameIgnoreCase(A, B))
return N; return N;
return strcmp(A, B); return strcmp(A, B);
} }
static inline bool operator<(const OptTable::Info &A, const OptTable::Info &B) { static inline bool operator<(const OptTable::Info &A, const OptTable::Info &B) {
if (&A == &B) if (&A == &B)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines if (Kind == Option::InputClass) {
TheUnknownOptionID = getInfo(i + 1).ID; TheUnknownOptionID = getInfo(i + 1).ID;
} else if (Kind != Option::GroupClass) { } else if (Kind != Option::GroupClass) {
FirstSearchableIndex = i; FirstSearchableIndex = i;
break; break;
} }
} }
assert(FirstSearchableIndex != 0 && "No searchable options?"); assert(FirstSearchableIndex != 0 && "No searchable options?");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Check that everything after the first searchable option is a // Check that everything after the first searchable option is a
// regular option class. // regular option class.
for (unsigned i = FirstSearchableIndex, e = getNumOptions(); i != e; ++i) { for (unsigned i = FirstSearchableIndex, e = getNumOptions(); i != e; ++i) {
Option::OptionClass Kind = (Option::OptionClass) getInfo(i + 1).Kind; Option::OptionClass Kind = (Option::OptionClass) getInfo(i + 1).Kind;
assert((Kind != Option::InputClass && Kind != Option::UnknownClass && assert((Kind != Option::InputClass && Kind != Option::UnknownClass &&
Kind != Option::GroupClass) && Kind != Option::GroupClass) &&
"Special options should be defined first!"); "Special options should be defined first!");
} }
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lib/Passes/PassBuilder.cpp

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
} }
void PassBuilder::registerFunctionAnalyses(FunctionAnalysisManager &FAM) { void PassBuilder::registerFunctionAnalyses(FunctionAnalysisManager &FAM) {
#define FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ #define FUNCTION_ANALYSIS(NAME, CREATE_PASS) \
FAM.registerPass(CREATE_PASS); FAM.registerPass(CREATE_PASS);
#include "PassRegistry.def" #include "PassRegistry.def"
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static bool isModulePassName(StringRef Name) { static bool isModulePassName(StringRef Name) {
#define MODULE_PASS(NAME, CREATE_PASS) if (Name == NAME) return true; #define MODULE_PASS(NAME, CREATE_PASS) if (Name == NAME) return true;
#define MODULE_ANALYSIS(NAME, CREATE_PASS) \ #define MODULE_ANALYSIS(NAME, CREATE_PASS) \
if (Name == "require<" NAME ">" || Name == "invalidate<" NAME ">") \ if (Name == "require<" NAME ">" || Name == "invalidate<" NAME ">") \
return true; return true;
#include "PassRegistry.def" #include "PassRegistry.def"
return false; return false;
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lib/Support/CommandLine.cpp

Show First 20 Lines • Show All 1,746 Lines • ▼ Show 20 Lines#ifdef LLVM_VERSION_INFO
OS << " " << LLVM_VERSION_INFO; OS << " " << LLVM_VERSION_INFO;
#endif #endif
OS << "\n "; OS << "\n ";
#ifndef __OPTIMIZE__ #ifndef __OPTIMIZE__
OS << "DEBUG build"; OS << "DEBUG build";
#else #else
OS << "Optimized build"; OS << "Optimized build";
#endif #endif
#ifndef NDEBUG #ifndef LLVM_NDEBUG
OS << " with assertions"; OS << " with assertions";
#endif #endif
std::string CPU = sys::getHostCPUName(); std::string CPU = sys::getHostCPUName();
if (CPU == "generic") if (CPU == "generic")
CPU = "(unknown)"; CPU = "(unknown)";
OS << ".\n" OS << ".\n"
#if (ENABLE_TIMESTAMPS == 1) #if (ENABLE_TIMESTAMPS == 1)
<< " Built " << __DATE__ << " (" << __TIME__ << ").\n" << " Built " << __DATE__ << " (" << __TIME__ << ").\n"
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lib/Support/Debug.cpp

Show All 29 Lines
#include "llvm/Support/circular_raw_ostream.h" #include "llvm/Support/circular_raw_ostream.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#undef isCurrentDebugType #undef isCurrentDebugType
#undef setCurrentDebugType #undef setCurrentDebugType
using namespace llvm; using namespace llvm;
// Even though LLVM might be built with NDEBUG, define symbols that the code // Even though LLVM might be built with LLVM_NDEBUG, define symbols that the code
// built without NDEBUG can depend on via the llvm/Support/Debug.h header. // built without LLVM_NDEBUG can depend on via the llvm/Support/Debug.h header.
namespace llvm { namespace llvm {
/// Exported boolean set by the -debug option. /// Exported boolean set by the -debug option.
bool DebugFlag = false; bool DebugFlag = false;
static ManagedStatic<std::vector<std::string>> CurrentDebugType; static ManagedStatic<std::vector<std::string>> CurrentDebugType;
/// Return true if the specified string is the debug type /// Return true if the specified string is the debug type
/// specified on the command line, or if none was specified on the command line /// specified on the command line, or if none was specified on the command line
Show All 16 Lines
/// ///
void setCurrentDebugType(const char *Type) { void setCurrentDebugType(const char *Type) {
CurrentDebugType->clear(); CurrentDebugType->clear();
CurrentDebugType->push_back(Type); CurrentDebugType->push_back(Type);
} }
} // namespace llvm } // namespace llvm
// All Debug.h functionality is a no-op in NDEBUG mode. // All Debug.h functionality is a no-op in LLVM_NDEBUG mode.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// -debug - Command line option to enable the DEBUG statements in the passes. // -debug - Command line option to enable the DEBUG statements in the passes.
// This flag may only be enabled in debug builds. // This flag may only be enabled in debug builds.
static cl::opt<bool, true> static cl::opt<bool, true>
Debug("debug", cl::desc("Enable debug output"), cl::Hidden, Debug("debug", cl::desc("Enable debug output"), cl::Hidden,
cl::location(DebugFlag)); cl::location(DebugFlag));
// -debug-buffer-size - Buffer the last N characters of debug output // -debug-buffer-size - Buffer the last N characters of debug output
Show All 23 Lines
static cl::opt<DebugOnlyOpt, true, cl::parser<std::string> > static cl::opt<DebugOnlyOpt, true, cl::parser<std::string> >
DebugOnly("debug-only", cl::desc("Enable a specific type of debug output"), DebugOnly("debug-only", cl::desc("Enable a specific type of debug output"),
cl::Hidden, cl::ZeroOrMore, cl::value_desc("debug string"), cl::Hidden, cl::ZeroOrMore, cl::value_desc("debug string"),
cl::location(DebugOnlyOptLoc), cl::ValueRequired); cl::location(DebugOnlyOptLoc), cl::ValueRequired);
// Signal handlers - dump debug output on termination. // Signal handlers - dump debug output on termination.
static void debug_user_sig_handler(void *Cookie) { static void debug_user_sig_handler(void *Cookie) {
// This is a bit sneaky. Since this is under #ifndef NDEBUG, we // This is a bit sneaky. Since this is under #ifndef LLVM_NDEBUG, we
// know that debug mode is enabled and dbgs() really is a // know that debug mode is enabled and dbgs() really is a
// circular_raw_ostream. If NDEBUG is defined, then dbgs() == // circular_raw_ostream. If LLVM_NDEBUG is defined, then dbgs() ==
// errs() but this will never be invoked. // errs() but this will never be invoked.
llvm::circular_raw_ostream &dbgout = llvm::circular_raw_ostream &dbgout =
static_cast<circular_raw_ostream &>(llvm::dbgs()); static_cast<circular_raw_ostream &>(llvm::dbgs());
dbgout.flushBufferWithBanner(); dbgout.flushBufferWithBanner();
} }
/// dbgs - Return a circular-buffered debug stream. /// dbgs - Return a circular-buffered debug stream.
raw_ostream &llvm::dbgs() { raw_ostream &llvm::dbgs() {
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lib/Support/IntervalMap.cpp

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 LinesIdxPair distribute(unsigned Nodes, unsigned Elements, unsigned Capacity,
// Subtract the Grow element that was added. // Subtract the Grow element that was added.
if (Grow) { if (Grow) {
assert(PosPair.first < Nodes && "Bad algebra"); assert(PosPair.first < Nodes && "Bad algebra");
assert(NewSize[PosPair.first] && "Too few elements to need Grow"); assert(NewSize[PosPair.first] && "Too few elements to need Grow");
--NewSize[PosPair.first]; --NewSize[PosPair.first];
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Sum = 0; Sum = 0;
for (unsigned n = 0; n != Nodes; ++n) { for (unsigned n = 0; n != Nodes; ++n) {
assert(NewSize[n] <= Capacity && "Overallocated node"); assert(NewSize[n] <= Capacity && "Overallocated node");
Sum += NewSize[n]; Sum += NewSize[n];
} }
assert(Sum == Elements && "Bad distribution sum"); assert(Sum == Elements && "Bad distribution sum");
#endif #endif
return PosPair; return PosPair;
} }
} // namespace IntervalMapImpl } // namespace IntervalMapImpl
} // namespace llvm } // namespace llvm

lib/Support/Statistic.cpp

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines OS << format("%*u %-*s - %s\n",
Stats.Stats[i]->getDesc()); Stats.Stats[i]->getDesc());
OS << '\n'; // Flush the output stream. OS << '\n'; // Flush the output stream.
OS.flush(); OS.flush();
} }
void llvm::PrintStatistics() { void llvm::PrintStatistics() {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_STATS) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_STATS)
StatisticInfo &Stats = *StatInfo; StatisticInfo &Stats = *StatInfo;
// Statistics not enabled? // Statistics not enabled?
if (Stats.Stats.empty()) return; if (Stats.Stats.empty()) return;
// Get the stream to write to. // Get the stream to write to.
raw_ostream &OutStream = *CreateInfoOutputFile(); raw_ostream &OutStream = *CreateInfoOutputFile();
PrintStatistics(OutStream); PrintStatistics(OutStream);
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lib/Support/raw_ostream.cpp

Show First 20 Lines • Show All 822 Lines • ▼ Show 20 LinesStringRef raw_svector_ostream::str() {
return StringRef(OS.begin(), OS.size()); return StringRef(OS.begin(), OS.size());
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// raw_null_ostream // raw_null_ostream
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
raw_null_ostream::~raw_null_ostream() { raw_null_ostream::~raw_null_ostream() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// ~raw_ostream asserts that the buffer is empty. This isn't necessary // ~raw_ostream asserts that the buffer is empty. This isn't necessary
// with raw_null_ostream, but it's better to have raw_null_ostream follow // with raw_null_ostream, but it's better to have raw_null_ostream follow
// the rules than to change the rules just for raw_null_ostream. // the rules than to change the rules just for raw_null_ostream.
flush(); flush();
#endif #endif
} }
void raw_null_ostream::write_impl(const char *Ptr, size_t Size) { void raw_null_ostream::write_impl(const char *Ptr, size_t Size) {
} }
uint64_t raw_null_ostream::current_pos() const { uint64_t raw_null_ostream::current_pos() const {
return 0; return 0;
} }
void raw_null_ostream::pwrite_impl(const char *Ptr, size_t Size, void raw_null_ostream::pwrite_impl(const char *Ptr, size_t Size,
uint64_t Offset) {} uint64_t Offset) {}

lib/Support/regengine.inc

Show First 20 Lines • Show All 238 Lines • ▼ Show 20 Lines for (;;) {
for (;;) { for (;;) {
if (dp != NULL || endp <= m->coldp) if (dp != NULL || endp <= m->coldp)
break; /* defeat */ break; /* defeat */
NOTE("backoff"); NOTE("backoff");
endp = slow(m, m->coldp, endp-1, gf, gl); endp = slow(m, m->coldp, endp-1, gf, gl);
if (endp == NULL) if (endp == NULL)
break; /* defeat */ break; /* defeat */
/* try it on a shorter possibility */ /* try it on a shorter possibility */
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (i = 1; i <= m->g->nsub; i++) { for (i = 1; i <= m->g->nsub; i++) {
assert(m->pmatch[i].rm_so == -1); assert(m->pmatch[i].rm_so == -1);
assert(m->pmatch[i].rm_eo == -1); assert(m->pmatch[i].rm_eo == -1);
} }
#endif #endif
NOTE("backoff dissect"); NOTE("backoff dissect");
dp = backref(m, m->coldp, endp, gf, gl, (sopno)0, 0); dp = backref(m, m->coldp, endp, gf, gl, (sopno)0, 0);
} }
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lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
namespace { namespace {
/// A "color", which is either even or odd. Yes, these aren't really colors /// A "color", which is either even or odd. Yes, these aren't really colors
/// but the algorithm is conceptually doing two-color graph coloring. /// but the algorithm is conceptually doing two-color graph coloring.
enum class Color { Even, Odd }; enum class Color { Even, Odd };
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static const char *ColorNames[2] = { "Even", "Odd" }; static const char *ColorNames[2] = { "Even", "Odd" };
#endif #endif
class Chain; class Chain;
class AArch64A57FPLoadBalancing : public MachineFunctionPass { class AArch64A57FPLoadBalancing : public MachineFunctionPass {
MachineRegisterInfo *MRI; MachineRegisterInfo *MRI;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
▲ Show 20 Lines • Show All 392 Lines • ▼ Show 20 Lines for (auto J : I->operands()) {
if (J.isRegMask()) if (J.isRegMask())
AvailableRegs.clearBitsNotInMask(J.getRegMask()); AvailableRegs.clearBitsNotInMask(J.getRegMask());
if (J.isReg() && J.isDef()) { if (J.isReg() && J.isDef()) {
MCRegAliasIterator AI(J.getReg(), TRI, /*IncludeSelf=*/true); MCRegAliasIterator AI(J.getReg(), TRI, /*IncludeSelf=*/true);
if (J.isDead()) if (J.isDead())
for (; AI.isValid(); ++AI) for (; AI.isValid(); ++AI)
AvailableRegs.reset(*AI); AvailableRegs.reset(*AI);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
else else
for (; AI.isValid(); ++AI) for (; AI.isValid(); ++AI)
assert(!AvailableRegs[*AI] && assert(!AvailableRegs[*AI] &&
"Non-dead def should have been removed by now!"); "Non-dead def should have been removed by now!");
#endif #endif
} }
} }
} }
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lib/Target/AArch64/AArch64BranchRelaxation.cpp

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
char AArch64BranchRelaxation::ID = 0; char AArch64BranchRelaxation::ID = 0;
} }
INITIALIZE_PASS(AArch64BranchRelaxation, "aarch64-branch-relax", INITIALIZE_PASS(AArch64BranchRelaxation, "aarch64-branch-relax",
AARCH64_BR_RELAX_NAME, false, false) AARCH64_BR_RELAX_NAME, false, false)
/// verify - check BBOffsets, BBSizes, alignment of islands /// verify - check BBOffsets, BBSizes, alignment of islands
void AArch64BranchRelaxation::verify() { void AArch64BranchRelaxation::verify() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned PrevNum = MF->begin()->getNumber(); unsigned PrevNum = MF->begin()->getNumber();
for (MachineBasicBlock &MBB : *MF) { for (MachineBasicBlock &MBB : *MF) {
unsigned Align = MBB.getAlignment(); unsigned Align = MBB.getAlignment();
unsigned Num = MBB.getNumber(); unsigned Num = MBB.getNumber();
assert(BlockInfo[Num].Offset % (1u << Align) == 0); assert(BlockInfo[Num].Offset % (1u << Align) == 0);
assert(!Num || BlockInfo[PrevNum].postOffset() <= BlockInfo[Num].Offset); assert(!Num || BlockInfo[PrevNum].postOffset() <= BlockInfo[Num].Offset);
PrevNum = Num; PrevNum = Num;
} }
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lib/Target/AArch64/AArch64CollectLOH.cpp

Show First 20 Lines • Show All 454 Lines • ▼ Show 20 Lines initReachingDef(MF, ColorOpToReachedUses, Gen, Kill, ReachableUses, RegToId,
DummyOp, ADRPMode); DummyOp, ADRPMode);
// Algo. // Algo.
if (!DummyOp) if (!DummyOp)
reachingDefAlgorithm(MF, ColorOpToReachedUses, In, Out, Gen, Kill, reachingDefAlgorithm(MF, ColorOpToReachedUses, In, Out, Gen, Kill,
ReachableUses, RegToId.size()); ReachableUses, RegToId.size());
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// print the result of the reaching definition algorithm. /// print the result of the reaching definition algorithm.
static void printReachingDef(const InstrToInstrs *ColorOpToReachedUses, static void printReachingDef(const InstrToInstrs *ColorOpToReachedUses,
unsigned NbReg, const TargetRegisterInfo *TRI, unsigned NbReg, const TargetRegisterInfo *TRI,
const MapIdToReg &IdToReg) { const MapIdToReg &IdToReg) {
unsigned CurReg; unsigned CurReg;
for (CurReg = 0; CurReg < NbReg; ++CurReg) { for (CurReg = 0; CurReg < NbReg; ++CurReg) {
if (ColorOpToReachedUses[CurReg].empty()) if (ColorOpToReachedUses[CurReg].empty())
continue; continue;
DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n"); DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n");
for (const auto &DefsIt : ColorOpToReachedUses[CurReg]) { for (const auto &DefsIt : ColorOpToReachedUses[CurReg]) {
DEBUG(dbgs() << "Def:\n"); DEBUG(dbgs() << "Def:\n");
DEBUG(DefsIt.first->print(dbgs())); DEBUG(DefsIt.first->print(dbgs()));
DEBUG(dbgs() << "Reachable uses:\n"); DEBUG(dbgs() << "Reachable uses:\n");
for (const MachineInstr *MI : DefsIt.second) { for (const MachineInstr *MI : DefsIt.second) {
DEBUG(MI->print(dbgs())); DEBUG(MI->print(dbgs()));
} }
} }
} }
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
/// Answer the following question: Can Def be one of the definition /// Answer the following question: Can Def be one of the definition
/// involved in a part of a LOH? /// involved in a part of a LOH?
static bool canDefBePartOfLOH(const MachineInstr *Def) { static bool canDefBePartOfLOH(const MachineInstr *Def) {
unsigned Opc = Def->getOpcode(); unsigned Opc = Def->getOpcode();
// Accept ADRP, ADDLow and LOADGot. // Accept ADRP, ADDLow and LOADGot.
switch (Opc) { switch (Opc) {
default: default:
▲ Show 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
#endif // DEBUG #endif // DEBUG
DEBUG(dbgs() << "*** Compute LOH for Others\n"); DEBUG(dbgs() << "*** Compute LOH for Others\n");
// ADRP -> ADD/LDR -> LDR/STR pattern. // ADRP -> ADD/LDR -> LDR/STR pattern.
// Fall back to ADRP -> ADD pattern if we fail to catch the bigger pattern. // Fall back to ADRP -> ADD pattern if we fail to catch the bigger pattern.
// FIXME: When the statistics are not important, // FIXME: When the statistics are not important,
// This initial filtering loop can be merged into the next loop. // This initial filtering loop can be merged into the next loop.
// Currently, we didn't do it to have the same code for both DEBUG and // Currently, we didn't do it to have the same code for both DEBUG and
// NDEBUG builds. Indeed, the iterator of the second loop would need // LLVM_NDEBUG builds. Indeed, the iterator of the second loop would need
// to be changed. // to be changed.
SetOfMachineInstr PotentialCandidates; SetOfMachineInstr PotentialCandidates;
SetOfMachineInstr PotentialADROpportunities; SetOfMachineInstr PotentialADROpportunities;
for (auto &Use : UseToDefs) { for (auto &Use : UseToDefs) {
// If no definition is available, this is a non candidate. // If no definition is available, this is a non candidate.
if (Use.second.empty()) if (Use.second.empty())
continue; continue;
// Keep only instructions that are load or store and at the end of // Keep only instructions that are load or store and at the end of
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lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 980 Lines • ▼ Show 20 LinesAArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
return EndBB; return EndBB;
} }
MachineBasicBlock * MachineBasicBlock *
AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const { MachineBasicBlock *BB) const {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
MI->dump(); MI->dump();
#endif #endif
llvm_unreachable("Unexpected instruction for custom inserter!"); llvm_unreachable("Unexpected instruction for custom inserter!");
case AArch64::F128CSEL: case AArch64::F128CSEL:
return EmitF128CSEL(MI, BB); return EmitF128CSEL(MI, BB);
case TargetOpcode::STACKMAP: case TargetOpcode::STACKMAP:
▲ Show 20 Lines • Show All 8,545 Lines • Show Last 20 Lines

lib/Target/AArch64/AArch64PBQPRegAlloc.cpp

Show All 27 Lines
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
namespace { namespace {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool isFPReg(unsigned reg) { bool isFPReg(unsigned reg) {
return AArch64::FPR32RegClass.contains(reg) || return AArch64::FPR32RegClass.contains(reg) ||
AArch64::FPR64RegClass.contains(reg) || AArch64::FPR64RegClass.contains(reg) ||
AArch64::FPR128RegClass.contains(reg); AArch64::FPR128RegClass.contains(reg);
} }
#endif #endif
bool isOdd(unsigned reg) { bool isOdd(unsigned reg) {
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lib/Target/AArch64/AArch64PromoteConstant.cpp

Show First 20 Lines • Show All 461 Lines • ▼ Show 20 Linesbool AArch64PromoteConstant::insertDefinitions(
// We will create one global variable per Module. // We will create one global variable per Module.
DenseMap<Module *, GlobalVariable *> ModuleToMergedGV; DenseMap<Module *, GlobalVariable *> ModuleToMergedGV;
bool HasChanged = false; bool HasChanged = false;
// Traverse all insertion points in all the function. // Traverse all insertion points in all the function.
for (const auto &FctToInstPtsIt : InsPtsPerFunc) { for (const auto &FctToInstPtsIt : InsPtsPerFunc) {
const InsertionPoints &InsertPts = FctToInstPtsIt.second; const InsertionPoints &InsertPts = FctToInstPtsIt.second;
// Do more checking for debug purposes. // Do more checking for debug purposes.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>( DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>(
*FctToInstPtsIt.first).getDomTree(); *FctToInstPtsIt.first).getDomTree();
#endif #endif
assert(!InsertPts.empty() && "Empty uses does not need a definition"); assert(!InsertPts.empty() && "Empty uses does not need a definition");
Module *M = FctToInstPtsIt.first->getParent(); Module *M = FctToInstPtsIt.first->getParent();
GlobalVariable *&PromotedGV = ModuleToMergedGV[M]; GlobalVariable *&PromotedGV = ModuleToMergedGV[M];
if (!PromotedGV) { if (!PromotedGV) {
Show All 14 Lines for (const auto &IPI : InsertPts) {
LoadInst *LoadedCst = Builder.CreateLoad(PromotedGV); LoadInst *LoadedCst = Builder.CreateLoad(PromotedGV);
DEBUG(dbgs() << "**********\n"); DEBUG(dbgs() << "**********\n");
DEBUG(dbgs() << "New def: "); DEBUG(dbgs() << "New def: ");
DEBUG(LoadedCst->print(dbgs())); DEBUG(LoadedCst->print(dbgs()));
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
// Update the dominated uses. // Update the dominated uses.
for (Use *Use : IPI.second) { for (Use *Use : IPI.second) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(DT.dominates(LoadedCst, findInsertionPoint(*Use)) && assert(DT.dominates(LoadedCst, findInsertionPoint(*Use)) &&
"Inserted definition does not dominate all its uses!"); "Inserted definition does not dominate all its uses!");
#endif #endif
DEBUG(dbgs() << "Use to update " << Use->getOperandNo() << ":"); DEBUG(dbgs() << "Use to update " << Use->getOperandNo() << ":");
DEBUG(Use->getUser()->print(dbgs())); DEBUG(Use->getUser()->print(dbgs()));
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
Use->set(LoadedCst); Use->set(LoadedCst);
++NumPromotedUses; ++NumPromotedUses;
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lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

Show First 20 Lines • Show All 669 Lines • ▼ Show 20 Lines if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
printAnnotation(O, Annot); printAnnotation(O, Annot);
return; return;
} }
AArch64InstPrinter::printInst(MI, O, Annot, STI); AArch64InstPrinter::printInst(MI, O, Annot, STI);
} }
bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) { bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!"); assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
#endif #endif
const char *Asm = nullptr; const char *Asm = nullptr;
const MCOperand &Op1 = MI->getOperand(0); const MCOperand &Op1 = MI->getOperand(0);
const MCOperand &Cn = MI->getOperand(1); const MCOperand &Cn = MI->getOperand(1);
const MCOperand &Cm = MI->getOperand(2); const MCOperand &Cm = MI->getOperand(2);
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lib/Target/AMDGPU/SILowerControlFlow.cpp

Show First 20 Lines • Show All 291 Lines • ▼ Show 20 Linesvoid SILowerControlFlowPass::Branch(MachineInstr &MI) {
// If these aren't equal, this is probably an infinite loop. // If these aren't equal, this is probably an infinite loop.
} }
void SILowerControlFlowPass::Kill(MachineInstr &MI) { void SILowerControlFlowPass::Kill(MachineInstr &MI) {
MachineBasicBlock &MBB = *MI.getParent(); MachineBasicBlock &MBB = *MI.getParent();
DebugLoc DL = MI.getDebugLoc(); DebugLoc DL = MI.getDebugLoc();
const MachineOperand &Op = MI.getOperand(0); const MachineOperand &Op = MI.getOperand(0);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const SIMachineFunctionInfo *MFI const SIMachineFunctionInfo *MFI
= MBB.getParent()->getInfo<SIMachineFunctionInfo>(); = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
// Kill is only allowed in pixel / geometry shaders. // Kill is only allowed in pixel / geometry shaders.
assert(MFI->getShaderType() == ShaderType::PIXEL || assert(MFI->getShaderType() == ShaderType::PIXEL ||
MFI->getShaderType() == ShaderType::GEOMETRY); MFI->getShaderType() == ShaderType::GEOMETRY);
#endif #endif
// Clear this thread from the exec mask if the operand is negative // Clear this thread from the exec mask if the operand is negative
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lib/Target/ARM/ARMBaseInstrInfo.cpp

Show First 20 Lines • Show All 798 Lines • ▼ Show 20 Linesvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI = &getRegisterInfo(); const TargetRegisterInfo *TRI = &getRegisterInfo();
MachineInstrBuilder Mov; MachineInstrBuilder Mov;
// Copy register tuples backward when the first Dest reg overlaps with SrcReg. // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing); BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
Spacing = -Spacing; Spacing = -Spacing;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
SmallSet<unsigned, 4> DstRegs; SmallSet<unsigned, 4> DstRegs;
#endif #endif
for (unsigned i = 0; i != SubRegs; ++i) { for (unsigned i = 0; i != SubRegs; ++i) {
unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
assert(Dst && Src && "Bad sub-register"); assert(Dst && Src && "Bad sub-register");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(!DstRegs.count(Src) && "destructive vector copy"); assert(!DstRegs.count(Src) && "destructive vector copy");
DstRegs.insert(Dst); DstRegs.insert(Dst);
#endif #endif
Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
// VORR takes two source operands. // VORR takes two source operands.
if (Opc == ARM::VORRq) if (Opc == ARM::VORRq)
Mov.addReg(Src); Mov.addReg(Src);
Mov = AddDefaultPred(Mov); Mov = AddDefaultPred(Mov);
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lib/Target/ARM/ARMBaseRegisterInfo.cpp

Show First 20 Lines • Show All 691 Lines • ▼ Show 20 LinesARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned FrameReg; unsigned FrameReg;
int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
// PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
// call frame setup/destroy instructions have already been eliminated. That // call frame setup/destroy instructions have already been eliminated. That
// means the stack pointer cannot be used to access the emergency spill slot // means the stack pointer cannot be used to access the emergency spill slot
// when !hasReservedCallFrame(). // when !hasReservedCallFrame().
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
assert(TFI->hasReservedCallFrame(MF) && assert(TFI->hasReservedCallFrame(MF) &&
"Cannot use SP to access the emergency spill slot in " "Cannot use SP to access the emergency spill slot in "
"functions without a reserved call frame"); "functions without a reserved call frame");
assert(!MF.getFrameInfo()->hasVarSizedObjects() && assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
"Cannot use SP to access the emergency spill slot in " "Cannot use SP to access the emergency spill slot in "
"functions with variable sized frame objects"); "functions with variable sized frame objects");
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
// Modify MI as necessary to handle as much of 'Offset' as possible // Modify MI as necessary to handle as much of 'Offset' as possible
bool Done = false; bool Done = false;
if (!AFI->isThumbFunction()) if (!AFI->isThumbFunction())
Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
else { else {
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lib/Target/ARM/ARMConstantIslandPass.cpp

Show First 20 Lines • Show All 333 Lines • ▼ Show 20 Lines bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
U.getMaxDisp(), U.NegOk, U.IsSoImm); U.getMaxDisp(), U.NegOk, U.IsSoImm);
} }
}; };
char ARMConstantIslands::ID = 0; char ARMConstantIslands::ID = 0;
} }
/// verify - check BBOffsets, BBSizes, alignment of islands /// verify - check BBOffsets, BBSizes, alignment of islands
void ARMConstantIslands::verify() { void ARMConstantIslands::verify() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end(); for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
MBBI != E; ++MBBI) { MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI; MachineBasicBlock *MBB = MBBI;
unsigned MBBId = MBB->getNumber(); unsigned MBBId = MBB->getNumber();
assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset); assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset);
} }
DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n"); DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
▲ Show 20 Lines • Show All 788 Lines • ▼ Show 20 Lines DEBUG({
<< format("CPE address=%#x offset=%+d: ", CPEOffset, << format("CPE address=%#x offset=%+d: ", CPEOffset,
int(CPEOffset-UserOffset)); int(CPEOffset-UserOffset));
}); });
} }
return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk); return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// BBIsJumpedOver - Return true of the specified basic block's only predecessor /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
/// unconditionally branches to its only successor. /// unconditionally branches to its only successor.
static bool BBIsJumpedOver(MachineBasicBlock *MBB) { static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
if (MBB->pred_size() != 1 || MBB->succ_size() != 1) if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
return false; return false;
MachineBasicBlock *Succ = *MBB->succ_begin(); MachineBasicBlock *Succ = *MBB->succ_begin();
MachineBasicBlock *Pred = *MBB->pred_begin(); MachineBasicBlock *Pred = *MBB->pred_begin();
MachineInstr *PredMI = &Pred->back(); MachineInstr *PredMI = &Pred->back();
if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
|| PredMI->getOpcode() == ARM::t2B) || PredMI->getOpcode() == ARM::t2B)
return PredMI->getOperand(0).getMBB() == Succ; return PredMI->getOperand(0).getMBB() == Succ;
return false; return false;
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
void ARMConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) { void ARMConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
unsigned BBNum = BB->getNumber(); unsigned BBNum = BB->getNumber();
for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) { for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
// Get the offset and known bits at the end of the layout predecessor. // Get the offset and known bits at the end of the layout predecessor.
// Include the alignment of the current block. // Include the alignment of the current block.
unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment(); unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
unsigned Offset = BBInfo[i - 1].postOffset(LogAlign); unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
▲ Show 20 Lines • Show All 1,111 Lines • Show Last 20 Lines

lib/Target/ARM/ARMExpandPseudoInsts.cpp

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
}; };
/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
/// load or store pseudo instruction. /// load or store pseudo instruction.
static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
const unsigned NumEntries = array_lengthof(NEONLdStTable); const unsigned NumEntries = array_lengthof(NEONLdStTable);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Make sure the table is sorted. // Make sure the table is sorted.
static bool TableChecked = false; static bool TableChecked = false;
if (!TableChecked) { if (!TableChecked) {
for (unsigned i = 0; i != NumEntries-1; ++i) for (unsigned i = 0; i != NumEntries-1; ++i)
assert(NEONLdStTable[i] < NEONLdStTable[i+1] && assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
"NEONLdStTable is not sorted!"); "NEONLdStTable is not sorted!");
TableChecked = true; TableChecked = true;
} }
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lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

Show First 20 Lines • Show All 480 Lines • ▼ Show 20 Linesvoid ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO1 = MI->getOperand(Op);
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, STI, O); printOperand(MI, Op, STI, O);
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const MCOperand &MO3 = MI->getOperand(Op + 2); const MCOperand &MO3 = MI->getOperand(Op + 2);
unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op"); assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
#endif #endif
printAM2PreOrOffsetIndexOp(MI, Op, STI, O); printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
} }
▲ Show 20 Lines • Show All 1,149 Lines • Show Last 20 Lines

lib/Target/ARM/ThumbRegisterInfo.cpp

Show First 20 Lines • Show All 525 Lines • ▼ Show 20 Lines if (MF.getFrameInfo()->hasVarSizedObjects()) {
} else } else
FrameReg = BasePtr; FrameReg = BasePtr;
} }
// PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
// call frame setup/destroy instructions have already been eliminated. That // call frame setup/destroy instructions have already been eliminated. That
// means the stack pointer cannot be used to access the emergency spill slot // means the stack pointer cannot be used to access the emergency spill slot
// when !hasReservedCallFrame(). // when !hasReservedCallFrame().
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
assert(STI.getFrameLowering()->hasReservedCallFrame(MF) && assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
"Cannot use SP to access the emergency spill slot in " "Cannot use SP to access the emergency spill slot in "
"functions without a reserved call frame"); "functions without a reserved call frame");
assert(!MF.getFrameInfo()->hasVarSizedObjects() && assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
"Cannot use SP to access the emergency spill slot in " "Cannot use SP to access the emergency spill slot in "
"functions with variable sized frame objects"); "functions with variable sized frame objects");
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
// Special handling of dbg_value instructions. // Special handling of dbg_value instructions.
if (MI.isDebugValue()) { if (MI.isDebugValue()) {
MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/); MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset); MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
return; return;
} }
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lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp

Show All 27 Lines
void BPFInstPrinter::printInst(const MCInst *MI, raw_ostream &O, void BPFInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) { StringRef Annot, const MCSubtargetInfo &STI) {
printInstruction(MI, O); printInstruction(MI, O);
printAnnotation(O, Annot); printAnnotation(O, Annot);
} }
static void printExpr(const MCExpr *Expr, raw_ostream &O) { static void printExpr(const MCExpr *Expr, raw_ostream &O) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const MCSymbolRefExpr *SRE; const MCSymbolRefExpr *SRE;
if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr))
SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS()); SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
else else
SRE = dyn_cast<MCSymbolRefExpr>(Expr); SRE = dyn_cast<MCSymbolRefExpr>(Expr);
assert(SRE && "Unexpected MCExpr type."); assert(SRE && "Unexpected MCExpr type.");
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lib/Target/Hexagon/HexagonBitTracker.cpp

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 LinesBT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
switch (ID) { switch (ID) {
case DoubleRegsRegClassID: case DoubleRegsRegClassID:
return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1) return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1)
: BT::BitMask(RW, 2*RW-1); : BT::BitMask(RW, 2*RW-1);
default: default:
break; break;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << PrintReg(Reg, &TRI, Sub) << '\n'; dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
#endif #endif
llvm_unreachable("Unexpected register/subregister"); llvm_unreachable("Unexpected register/subregister");
} }
namespace { namespace {
class RegisterRefs { class RegisterRefs {
std::vector<BT::RegisterRef> Vector; std::vector<BT::RegisterRef> Vector;
▲ Show 20 Lines • Show All 1,073 Lines • Show Last 20 Lines

lib/Target/Hexagon/HexagonFrameLowering.cpp

Show First 20 Lines • Show All 987 Lines • ▼ Show 20 Lines if (HasReplacedPseudoInst && needToReserveScavengingSpillSlots(MF, HRI)) {
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
for (int i=0; i < NumberScavengerSlots; i++) for (int i=0; i < NumberScavengerSlots; i++)
RS->addScavengingFrameIndex( RS->addScavengingFrameIndex(
MFI->CreateSpillStackObject(RC.getSize(), RC.getAlignment())); MFI->CreateSpillStackObject(RC.getSize(), RC.getAlignment()));
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
dbgs() << '{'; dbgs() << '{';
for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) { for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
unsigned R = x; unsigned R = x;
dbgs() << ' ' << PrintReg(R, &TRI); dbgs() << ' ' << PrintReg(R, &TRI);
} }
dbgs() << " }"; dbgs() << " }";
} }
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
if (Off >= 0) if (Off >= 0)
dbgs() << '+'; dbgs() << '+';
dbgs() << Off; dbgs() << Off;
} }
dbgs() << " }\n"; dbgs() << " }\n";
}); });
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify that all registers were handled. // Verify that all registers were handled.
bool MissedReg = false; bool MissedReg = false;
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
unsigned R = x; unsigned R = x;
dbgs() << PrintReg(R, TRI) << ' '; dbgs() << PrintReg(R, TRI) << ' ';
MissedReg = true; MissedReg = true;
} }
if (MissedReg) if (MissedReg)
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lib/Target/Hexagon/HexagonGenInsert.cpp

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
// extenders, but often not practical. // extenders, but often not practical.
static cl::opt<bool> OptConst("insert-const", cl::init(false), cl::Hidden, static cl::opt<bool> OptConst("insert-const", cl::init(false), cl::Hidden,
cl::ZeroOrMore); cl::ZeroOrMore);
namespace { namespace {
// The preprocessor gets confused when the DEBUG macro is passed larger // The preprocessor gets confused when the DEBUG macro is passed larger
// chunks of code. Use this function to detect debugging. // chunks of code. Use this function to detect debugging.
inline bool isDebug() { inline bool isDebug() {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
return ::llvm::DebugFlag && ::llvm::isCurrentDebugType(DEBUG_TYPE); return ::llvm::DebugFlag && ::llvm::isCurrentDebugType(DEBUG_TYPE);
#else #else
return false; return false;
#endif #endif
} }
} }
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lib/Target/Hexagon/HexagonHardwareLoops.cpp

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include <algorithm> #include <algorithm>
#include <vector> #include <vector>
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "hwloops" #define DEBUG_TYPE "hwloops"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<int> HWLoopLimit("hexagon-max-hwloop", cl::Hidden, cl::init(-1)); static cl::opt<int> HWLoopLimit("hexagon-max-hwloop", cl::Hidden, cl::init(-1));
// Option to create preheader only for a specific function. // Option to create preheader only for a specific function.
static cl::opt<std::string> PHFn("hexagon-hwloop-phfn", cl::Hidden, static cl::opt<std::string> PHFn("hexagon-hwloop-phfn", cl::Hidden,
cl::init("")); cl::init(""));
#endif #endif
// Option to create a preheader if one doesn't exist. // Option to create a preheader if one doesn't exist.
Show All 10 Lines
namespace { namespace {
class CountValue; class CountValue;
struct HexagonHardwareLoops : public MachineFunctionPass { struct HexagonHardwareLoops : public MachineFunctionPass {
MachineLoopInfo *MLI; MachineLoopInfo *MLI;
MachineRegisterInfo *MRI; MachineRegisterInfo *MRI;
MachineDominatorTree *MDT; MachineDominatorTree *MDT;
const HexagonInstrInfo *TII; const HexagonInstrInfo *TII;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static int Counter; static int Counter;
#endif #endif
public: public:
static char ID; static char ID;
HexagonHardwareLoops() : MachineFunctionPass(ID) { HexagonHardwareLoops() : MachineFunctionPass(ID) {
initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry()); initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry());
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines private:
bool fixupInductionVariable(MachineLoop *L); bool fixupInductionVariable(MachineLoop *L);
/// \brief Given a loop, if it does not have a preheader, create one. /// \brief Given a loop, if it does not have a preheader, create one.
/// Return the block that is the preheader. /// Return the block that is the preheader.
MachineBasicBlock *createPreheaderForLoop(MachineLoop *L); MachineBasicBlock *createPreheaderForLoop(MachineLoop *L);
}; };
char HexagonHardwareLoops::ID = 0; char HexagonHardwareLoops::ID = 0;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
int HexagonHardwareLoops::Counter = 0; int HexagonHardwareLoops::Counter = 0;
#endif #endif
/// \brief Abstraction for a trip count of a loop. A smaller version /// \brief Abstraction for a trip count of a loop. A smaller version
/// of the MachineOperand class without the concerns of changing the /// of the MachineOperand class without the concerns of changing the
/// operand representation. /// operand representation.
class CountValue { class CountValue {
public: public:
▲ Show 20 Lines • Show All 829 Lines • ▼ Show 20 Lines if (L0Used) {
ENDLOOP = Hexagon::ENDLOOP1; ENDLOOP = Hexagon::ENDLOOP1;
IsInnerHWLoop = 0; IsInnerHWLoop = 0;
} else { } else {
LOOP_i = Hexagon::J2_loop0i; LOOP_i = Hexagon::J2_loop0i;
LOOP_r = Hexagon::J2_loop0r; LOOP_r = Hexagon::J2_loop0r;
ENDLOOP = Hexagon::ENDLOOP0; ENDLOOP = Hexagon::ENDLOOP0;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Stop trying after reaching the limit (if any). // Stop trying after reaching the limit (if any).
int Limit = HWLoopLimit; int Limit = HWLoopLimit;
if (Limit >= 0) { if (Limit >= 0) {
if (Counter >= HWLoopLimit) if (Counter >= HWLoopLimit)
return false; return false;
Counter++; Counter++;
} }
#endif #endif
▲ Show 20 Lines • Show All 683 Lines • ▼ Show 20 Lines if (!HWCreatePreheader)
return nullptr; return nullptr;
MachineBasicBlock *Header = L->getHeader(); MachineBasicBlock *Header = L->getHeader();
MachineBasicBlock *Latch = L->getLoopLatch(); MachineBasicBlock *Latch = L->getLoopLatch();
MachineBasicBlock *ExitingBlock = getExitingBlock(L); MachineBasicBlock *ExitingBlock = getExitingBlock(L);
MachineFunction *MF = Header->getParent(); MachineFunction *MF = Header->getParent();
DebugLoc DL; DebugLoc DL;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if ((PHFn != "") && (PHFn != MF->getName())) if ((PHFn != "") && (PHFn != MF->getName()))
return nullptr; return nullptr;
#endif #endif
if (!Latch || !ExitingBlock || Header->hasAddressTaken()) if (!Latch || !ExitingBlock || Header->hasAddressTaken())
return nullptr; return nullptr;
typedef MachineBasicBlock::instr_iterator instr_iterator; typedef MachineBasicBlock::instr_iterator instr_iterator;
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lib/Target/Hexagon/HexagonISelLowering.cpp

Show First 20 Lines • Show All 2,278 Lines • ▼ Show 20 LinesHexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain); return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
} }
SDValue SDValue
HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode(); unsigned Opc = Op.getOpcode();
switch (Opc) { switch (Opc) {
default: default:
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Op.getNode()->dumpr(&DAG); Op.getNode()->dumpr(&DAG);
if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END) if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
errs() << "Check for a non-legal type in this operation\n"; errs() << "Check for a non-legal type in this operation\n";
#endif #endif
llvm_unreachable("Should not custom lower this!"); llvm_unreachable("Should not custom lower this!");
case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG); case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG); case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
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lib/Target/Hexagon/HexagonMachineScheduler.h

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Linesprotected:
int SchedulingCost(ReadyQueue &Q, int SchedulingCost(ReadyQueue &Q,
SUnit *SU, SchedCandidate &Candidate, SUnit *SU, SchedCandidate &Candidate,
RegPressureDelta &Delta, bool verbose); RegPressureDelta &Delta, bool verbose);
CandResult pickNodeFromQueue(ReadyQueue &Q, CandResult pickNodeFromQueue(ReadyQueue &Q,
const RegPressureTracker &RPTracker, const RegPressureTracker &RPTracker,
SchedCandidate &Candidate); SchedCandidate &Candidate);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
PressureChange P = PressureChange()); PressureChange P = PressureChange());
#endif #endif
}; };
} // namespace } // namespace
#endif #endif

lib/Target/Hexagon/HexagonMachineScheduler.cpp

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesbool VLIWResourceModel::reserveResources(SUnit *SU) {
case TargetOpcode::CFI_INSTRUCTION: case TargetOpcode::CFI_INSTRUCTION:
case TargetOpcode::EH_LABEL: case TargetOpcode::EH_LABEL:
case TargetOpcode::COPY: case TargetOpcode::COPY:
case TargetOpcode::INLINEASM: case TargetOpcode::INLINEASM:
break; break;
} }
Packet.push_back(SU); Packet.push_back(SU);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n"); DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n");
for (unsigned i = 0, e = Packet.size(); i != e; ++i) { for (unsigned i = 0, e = Packet.size(); i != e; ++i) {
DEBUG(dbgs() << "\t[" << i << "] SU("); DEBUG(dbgs() << "\t[" << i << "] SU(");
DEBUG(dbgs() << Packet[i]->NodeNum << ")\t"); DEBUG(dbgs() << Packet[i]->NodeNum << ")\t");
DEBUG(Packet[i]->getInstr()->dump()); DEBUG(Packet[i]->getInstr()->dump());
} }
#endif #endif
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void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) { void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) {
if (SU->isScheduled) if (SU->isScheduled)
return; return;
for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end(); for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) { I != E; ++I) {
unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle; unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
unsigned MinLatency = I->getLatency(); unsigned MinLatency = I->getLatency();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency); Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);
#endif #endif
if (SU->TopReadyCycle < PredReadyCycle + MinLatency) if (SU->TopReadyCycle < PredReadyCycle + MinLatency)
SU->TopReadyCycle = PredReadyCycle + MinLatency; SU->TopReadyCycle = PredReadyCycle + MinLatency;
} }
Top.releaseNode(SU, SU->TopReadyCycle); Top.releaseNode(SU, SU->TopReadyCycle);
} }
void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU) { void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU) {
if (SU->isScheduled) if (SU->isScheduled)
return; return;
assert(SU->getInstr() && "Scheduled SUnit must have instr"); assert(SU->getInstr() && "Scheduled SUnit must have instr");
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) { I != E; ++I) {
unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
unsigned MinLatency = I->getLatency(); unsigned MinLatency = I->getLatency();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency); Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);
#endif #endif
if (SU->BotReadyCycle < SuccReadyCycle + MinLatency) if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)
SU->BotReadyCycle = SuccReadyCycle + MinLatency; SU->BotReadyCycle = SuccReadyCycle + MinLatency;
} }
Bot.releaseNode(SU, SU->BotReadyCycle); Bot.releaseNode(SU, SU->BotReadyCycle);
} }
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines for (unsigned i = 0; Available.empty(); ++i) {
bumpCycle(); bumpCycle();
releasePending(); releasePending();
} }
if (Available.size() == 1) if (Available.size() == 1)
return *Available.begin(); return *Available.begin();
return nullptr; return nullptr;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void ConvergingVLIWScheduler::traceCandidate(const char *Label, void ConvergingVLIWScheduler::traceCandidate(const char *Label,
const ReadyQueue &Q, const ReadyQueue &Q,
SUnit *SU, PressureChange P) { SUnit *SU, PressureChange P) {
dbgs() << Label << " " << Q.getName() << " "; dbgs() << Label << " " << Q.getName() << " ";
if (P.isValid()) if (P.isValid())
dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":" dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":"
<< P.getUnitInc() << " "; << P.getUnitInc() << " ";
else else
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lib/Target/Hexagon/HexagonRegisterInfo.cpp

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Linesvoid HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} }
if (Valid) { if (Valid) {
MI.getOperand(FIOp).ChangeToRegister(BP, false); MI.getOperand(FIOp).ChangeToRegister(BP, false);
MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset); MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const Function *F = MF.getFunction(); const Function *F = MF.getFunction();
dbgs() << "In function "; dbgs() << "In function ";
if (F) dbgs() << F->getName(); if (F) dbgs() << F->getName();
else dbgs() << "<?>"; else dbgs() << "<?>";
dbgs() << ", BB#" << MB.getNumber() << "\n" << MI; dbgs() << ", BB#" << MB.getNumber() << "\n" << MI;
#endif #endif
llvm_unreachable("Unhandled instruction"); llvm_unreachable("Unhandled instruction");
} }
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lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

Show First 20 Lines • Show All 463 Lines • ▼ Show 20 Lines if (QII->isPredicatedTrue(MI))
return PK_True; return PK_True;
return PK_False; return PK_False;
} }
static MachineOperand& GetPostIncrementOperand(MachineInstr *MI, static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
const HexagonInstrInfo *QII) { const HexagonInstrInfo *QII) {
assert(QII->isPostIncrement(MI) && "Not a post increment operation."); assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Post Increment means duplicates. Use dense map to find duplicates in the // Post Increment means duplicates. Use dense map to find duplicates in the
// list. Caution: Densemap initializes with the minimum of 64 buckets, // list. Caution: Densemap initializes with the minimum of 64 buckets,
// whereas there are at most 5 operands in the post increment. // whereas there are at most 5 operands in the post increment.
DenseMap<unsigned, unsigned> DefRegsSet; DenseMap<unsigned, unsigned> DefRegsSet;
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
if (MI->getOperand(opNum).isReg() && if (MI->getOperand(opNum).isReg() &&
MI->getOperand(opNum).isDef()) { MI->getOperand(opNum).isDef()) {
DefRegsSet[MI->getOperand(opNum).getReg()] = 1; DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
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lib/Target/MSP430/MSP430ISelLowering.cpp

Show First 20 Lines • Show All 451 Lines • ▼ Show 20 LinesMSP430TargetLowering::LowerCCCArguments(SDValue Chain,
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i]; CCValAssign &VA = ArgLocs[i];
if (VA.isRegLoc()) { if (VA.isRegLoc()) {
// Arguments passed in registers // Arguments passed in registers
EVT RegVT = VA.getLocVT(); EVT RegVT = VA.getLocVT();
switch (RegVT.getSimpleVT().SimpleTy) { switch (RegVT.getSimpleVT().SimpleTy) {
default: default:
{ {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
errs() << "LowerFormalArguments Unhandled argument type: " errs() << "LowerFormalArguments Unhandled argument type: "
<< RegVT.getSimpleVT().SimpleTy << "\n"; << RegVT.getSimpleVT().SimpleTy << "\n";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
case MVT::i16: case MVT::i16:
unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
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lib/Target/Mips/Mips16ISelLowering.cpp

Show First 20 Lines • Show All 369 Lines • ▼ Show 20 Lines
#undef P #undef P
#undef P_ #undef P_
const char* Mips16TargetLowering:: const char* Mips16TargetLowering::
getMips16HelperFunction getMips16HelperFunction
(Type* RetTy, ArgListTy &Args, bool &needHelper) const { (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const unsigned int maxStubNum = 10; const unsigned int maxStubNum = 10;
assert(stubNum <= maxStubNum); assert(stubNum <= maxStubNum);
const bool validStubNum[maxStubNum+1] = const bool validStubNum[maxStubNum+1] =
{true, true, true, false, false, true, true, false, false, true, true}; {true, true, true, false, false, true, true, false, false, true, true};
assert(validStubNum[stubNum]); assert(validStubNum[stubNum]);
#endif #endif
const char *result; const char *result;
if (RetTy->isFloatTy()) { if (RetTy->isFloatTy()) {
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lib/Target/Mips/MipsCCState.cpp

Show All 28 Lines const char *const LibCalls[] = {
"powl", "rintl", "sinl", "sqrtl", "powl", "rintl", "sinl", "sqrtl",
"truncl"}; "truncl"};
const char *const *End = LibCalls + array_lengthof(LibCalls); const char *const *End = LibCalls + array_lengthof(LibCalls);
// Check that LibCalls is sorted alphabetically. // Check that LibCalls is sorted alphabetically.
MipsTargetLowering::LTStr Comp; MipsTargetLowering::LTStr Comp;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (const char *const *I = LibCalls; I < End - 1; ++I) for (const char *const *I = LibCalls; I < End - 1; ++I)
assert(Comp(*I, *(I + 1))); assert(Comp(*I, *(I + 1)));
#endif #endif
return std::binary_search(LibCalls, End, CallSym, Comp); return std::binary_search(LibCalls, End, CallSym, Comp);
} }
/// This function returns true if Ty is fp128, {f128} or i128 which was /// This function returns true if Ty is fp128, {f128} or i128 which was
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lib/Target/Mips/MipsConstantIslandPass.cpp

Show First 20 Lines • Show All 1,018 Lines • ▼ Show 20 Lines DEBUG({
<< format("CPE address=%#x offset=%+d: ", CPEOffset, << format("CPE address=%#x offset=%+d: ", CPEOffset,
int(CPEOffset-UserOffset)); int(CPEOffset-UserOffset));
}); });
} }
return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk); return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// BBIsJumpedOver - Return true of the specified basic block's only predecessor /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
/// unconditionally branches to its only successor. /// unconditionally branches to its only successor.
static bool BBIsJumpedOver(MachineBasicBlock *MBB) { static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
if (MBB->pred_size() != 1 || MBB->succ_size() != 1) if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
return false; return false;
MachineBasicBlock *Succ = *MBB->succ_begin(); MachineBasicBlock *Succ = *MBB->succ_begin();
MachineBasicBlock *Pred = *MBB->pred_begin(); MachineBasicBlock *Pred = *MBB->pred_begin();
MachineInstr *PredMI = &Pred->back(); MachineInstr *PredMI = &Pred->back();
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lib/Target/Mips/MipsDelaySlotFiller.cpp

Show First 20 Lines • Show All 274 Lines • ▼ Show 20 Lines
static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) { static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) { for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
const MachineOperand &MO = Filler->getOperand(I); const MachineOperand &MO = Filler->getOperand(I);
unsigned R; unsigned R;
if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg())) if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
continue; continue;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const MachineFunction &MF = *MBB.getParent(); const MachineFunction &MF = *MBB.getParent();
assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
"Shouldn't move an instruction with unallocatable registers across " "Shouldn't move an instruction with unallocatable registers across "
"basic block boundaries."); "basic block boundaries.");
#endif #endif
if (!MBB.isLiveIn(R)) if (!MBB.isLiveIn(R))
MBB.addLiveIn(R); MBB.addLiveIn(R);
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lib/Target/Mips/MipsISelDAGToDAG.cpp

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 LinesSDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
switch(Opcode) { switch(Opcode) {
default: break; default: break;
// Get target GOT address. // Get target GOT address.
case ISD::GLOBAL_OFFSET_TABLE: case ISD::GLOBAL_OFFSET_TABLE:
return getGlobalBaseReg(); return getGlobalBaseReg();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
case ISD::LOAD: case ISD::LOAD:
case ISD::STORE: case ISD::STORE:
assert((Subtarget->systemSupportsUnalignedAccess() || assert((Subtarget->systemSupportsUnalignedAccess() ||
cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <= cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
cast<MemSDNode>(Node)->getAlignment()) && cast<MemSDNode>(Node)->getAlignment()) &&
"Unexpected unaligned loads/stores."); "Unexpected unaligned loads/stores.");
break; break;
#endif #endif
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lib/Target/Mips/MipsMachineFunction.h

Show All 36 Linespublic:
explicit MipsCallEntry(StringRef N); explicit MipsCallEntry(StringRef N);
explicit MipsCallEntry(const GlobalValue *V); explicit MipsCallEntry(const GlobalValue *V);
bool isConstant(const MachineFrameInfo *) const override; bool isConstant(const MachineFrameInfo *) const override;
bool isAliased(const MachineFrameInfo *) const override; bool isAliased(const MachineFrameInfo *) const override;
bool mayAlias(const MachineFrameInfo *) const override; bool mayAlias(const MachineFrameInfo *) const override;
private: private:
void printCustom(raw_ostream &O) const override; void printCustom(raw_ostream &O) const override;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
std::string Name; std::string Name;
const GlobalValue *Val; const GlobalValue *Val;
#endif #endif
}; };
/// MipsFunctionInfo - This class is derived from MachineFunction private /// MipsFunctionInfo - This class is derived from MachineFunction private
/// Mips target-specific information for each MachineFunction. /// Mips target-specific information for each MachineFunction.
class MipsFunctionInfo : public MachineFunctionInfo { class MipsFunctionInfo : public MachineFunctionInfo {
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lib/Target/Mips/MipsMachineFunction.cpp

Show All 20 Lines
using namespace llvm; using namespace llvm;
static cl::opt<bool> static cl::opt<bool>
FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
cl::desc("Always use $gp as the global base register.")); cl::desc("Always use $gp as the global base register."));
// class MipsCallEntry. // class MipsCallEntry.
MipsCallEntry::MipsCallEntry(StringRef N) { MipsCallEntry::MipsCallEntry(StringRef N) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Name = N; Name = N;
Val = nullptr; Val = nullptr;
#endif #endif
} }
MipsCallEntry::MipsCallEntry(const GlobalValue *V) { MipsCallEntry::MipsCallEntry(const GlobalValue *V) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Val = V; Val = V;
#endif #endif
} }
bool MipsCallEntry::isConstant(const MachineFrameInfo *) const { bool MipsCallEntry::isConstant(const MachineFrameInfo *) const {
return false; return false;
} }
bool MipsCallEntry::isAliased(const MachineFrameInfo *) const { bool MipsCallEntry::isAliased(const MachineFrameInfo *) const {
return false; return false;
} }
bool MipsCallEntry::mayAlias(const MachineFrameInfo *) const { bool MipsCallEntry::mayAlias(const MachineFrameInfo *) const {
return false; return false;
} }
void MipsCallEntry::printCustom(raw_ostream &O) const { void MipsCallEntry::printCustom(raw_ostream &O) const {
O << "MipsCallEntry: "; O << "MipsCallEntry: ";
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (Val) if (Val)
O << Val->getName(); O << Val->getName();
else else
O << Name; O << Name;
#endif #endif
} }
MipsFunctionInfo::~MipsFunctionInfo() {} MipsFunctionInfo::~MipsFunctionInfo() {}
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lib/Target/PowerPC/PPC.h

Show All 25 Linesnamespace llvm {
class PassRegistry; class PassRegistry;
class FunctionPass; class FunctionPass;
class ImmutablePass; class ImmutablePass;
class MachineInstr; class MachineInstr;
class AsmPrinter; class AsmPrinter;
class MCInst; class MCInst;
FunctionPass *createPPCCTRLoops(PPCTargetMachine &TM); FunctionPass *createPPCCTRLoops(PPCTargetMachine &TM);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
FunctionPass *createPPCCTRLoopsVerify(); FunctionPass *createPPCCTRLoopsVerify();
#endif #endif
FunctionPass *createPPCLoopDataPrefetchPass(); FunctionPass *createPPCLoopDataPrefetchPass();
FunctionPass *createPPCLoopPreIncPrepPass(PPCTargetMachine &TM); FunctionPass *createPPCLoopPreIncPrepPass(PPCTargetMachine &TM);
FunctionPass *createPPCTOCRegDepsPass(); FunctionPass *createPPCTOCRegDepsPass();
FunctionPass *createPPCEarlyReturnPass(); FunctionPass *createPPCEarlyReturnPass();
FunctionPass *createPPCVSXCopyPass(); FunctionPass *createPPCVSXCopyPass();
FunctionPass *createPPCVSXFMAMutatePass(); FunctionPass *createPPCVSXFMAMutatePass();
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lib/Target/PowerPC/PPCCTRLoops.cpp

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
#include "llvm/PassSupport.h" #include "llvm/PassSupport.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/LoopUtils.h" #include "llvm/Transforms/Utils/LoopUtils.h"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#endif #endif
#include <algorithm> #include <algorithm>
#include <vector> #include <vector>
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "ctrloops" #define DEBUG_TYPE "ctrloops"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<int> CTRLoopLimit("ppc-max-ctrloop", cl::Hidden, cl::init(-1)); static cl::opt<int> CTRLoopLimit("ppc-max-ctrloop", cl::Hidden, cl::init(-1));
#endif #endif
STATISTIC(NumCTRLoops, "Number of loops converted to CTR loops"); STATISTIC(NumCTRLoops, "Number of loops converted to CTR loops");
namespace llvm { namespace llvm {
void initializePPCCTRLoopsPass(PassRegistry&); void initializePPCCTRLoopsPass(PassRegistry&);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void initializePPCCTRLoopsVerifyPass(PassRegistry&); void initializePPCCTRLoopsVerifyPass(PassRegistry&);
#endif #endif
} }
namespace { namespace {
struct PPCCTRLoops : public FunctionPass { struct PPCCTRLoops : public FunctionPass {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static int Counter; static int Counter;
#endif #endif
public: public:
static char ID; static char ID;
PPCCTRLoops() : FunctionPass(ID), TM(nullptr) { PPCCTRLoops() : FunctionPass(ID), TM(nullptr) {
initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry()); initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry());
Show All 21 Lines private:
LoopInfo *LI; LoopInfo *LI;
ScalarEvolution *SE; ScalarEvolution *SE;
const DataLayout *DL; const DataLayout *DL;
DominatorTree *DT; DominatorTree *DT;
const TargetLibraryInfo *LibInfo; const TargetLibraryInfo *LibInfo;
}; };
char PPCCTRLoops::ID = 0; char PPCCTRLoops::ID = 0;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
int PPCCTRLoops::Counter = 0; int PPCCTRLoops::Counter = 0;
#endif #endif
#ifndef NDEBUG #ifndef LLVM_NDEBUG
struct PPCCTRLoopsVerify : public MachineFunctionPass { struct PPCCTRLoopsVerify : public MachineFunctionPass {
public: public:
static char ID; static char ID;
PPCCTRLoopsVerify() : MachineFunctionPass(ID) { PPCCTRLoopsVerify() : MachineFunctionPass(ID) {
initializePPCCTRLoopsVerifyPass(*PassRegistry::getPassRegistry()); initializePPCCTRLoopsVerifyPass(*PassRegistry::getPassRegistry());
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
private: private:
MachineDominatorTree *MDT; MachineDominatorTree *MDT;
}; };
char PPCCTRLoopsVerify::ID = 0; char PPCCTRLoopsVerify::ID = 0;
#endif // NDEBUG #endif // LLVM_NDEBUG
} // end anonymous namespace } // end anonymous namespace
INITIALIZE_PASS_BEGIN(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops", INITIALIZE_PASS_BEGIN(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops",
false, false) false, false)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(ScalarEvolution) INITIALIZE_PASS_DEPENDENCY(ScalarEvolution)
INITIALIZE_PASS_END(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops", INITIALIZE_PASS_END(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops",
false, false) false, false)
FunctionPass *llvm::createPPCCTRLoops(PPCTargetMachine &TM) { FunctionPass *llvm::createPPCCTRLoops(PPCTargetMachine &TM) {
return new PPCCTRLoops(TM); return new PPCCTRLoops(TM);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
INITIALIZE_PASS_BEGIN(PPCCTRLoopsVerify, "ppc-ctr-loops-verify", INITIALIZE_PASS_BEGIN(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
"PowerPC CTR Loops Verify", false, false) "PowerPC CTR Loops Verify", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_END(PPCCTRLoopsVerify, "ppc-ctr-loops-verify", INITIALIZE_PASS_END(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
"PowerPC CTR Loops Verify", false, false) "PowerPC CTR Loops Verify", false, false)
FunctionPass *llvm::createPPCCTRLoopsVerify() { FunctionPass *llvm::createPPCCTRLoopsVerify() {
return new PPCCTRLoopsVerify(); return new PPCCTRLoopsVerify();
} }
#endif // NDEBUG #endif // LLVM_NDEBUG
bool PPCCTRLoops::runOnFunction(Function &F) { bool PPCCTRLoops::runOnFunction(Function &F) {
LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo(); LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
SE = &getAnalysis<ScalarEvolution>(); SE = &getAnalysis<ScalarEvolution>();
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree(); DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
DL = &F.getParent()->getDataLayout(); DL = &F.getParent()->getDataLayout();
auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>(); auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();
LibInfo = TLIP ? &TLIP->getTLI() : nullptr; LibInfo = TLIP ? &TLIP->getTLI() : nullptr;
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 Linesbool PPCCTRLoops::convertToCTRLoop(Loop *L) {
for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I) { for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
MadeChange |= convertToCTRLoop(*I); MadeChange |= convertToCTRLoop(*I);
} }
// If a nested loop has been converted, then we can't convert this loop. // If a nested loop has been converted, then we can't convert this loop.
if (MadeChange) if (MadeChange)
return MadeChange; return MadeChange;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Stop trying after reaching the limit (if any). // Stop trying after reaching the limit (if any).
int Limit = CTRLoopLimit; int Limit = CTRLoopLimit;
if (Limit >= 0) { if (Limit >= 0) {
if (Counter >= CTRLoopLimit) if (Counter >= CTRLoopLimit)
return false; return false;
Counter++; Counter++;
} }
#endif #endif
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines#endif
// (the original induction variable). // (the original induction variable).
RecursivelyDeleteTriviallyDeadInstructions(OldCond); RecursivelyDeleteTriviallyDeadInstructions(OldCond);
DeleteDeadPHIs(CountedExitBlock); DeleteDeadPHIs(CountedExitBlock);
++NumCTRLoops; ++NumCTRLoops;
return MadeChange; return MadeChange;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static bool clobbersCTR(const MachineInstr *MI) { static bool clobbersCTR(const MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg()) { if (MO.isReg()) {
if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
return true; return true;
} else if (MO.isRegMask()) { } else if (MO.isRegMask()) {
if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8)) if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8))
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines for (MachineBasicBlock::iterator MII = MBB->getFirstTerminator(),
Opc == PPC::BDZ8 || Opc == PPC::BDZ) Opc == PPC::BDZ8 || Opc == PPC::BDZ)
if (!verifyCTRBranch(MBB, MII)) if (!verifyCTRBranch(MBB, MII))
llvm_unreachable("Invalid PPC CTR loop!"); llvm_unreachable("Invalid PPC CTR loop!");
} }
} }
return false; return false;
} }
#endif // NDEBUG #endif // LLVM_NDEBUG

lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,532 Lines • ▼ Show 20 Lines for (unsigned i = 0; i != NumArgs; ++i) {
Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
CCInfo); CCInfo);
} else { } else {
Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
ArgFlags, CCInfo); ArgFlags, CCInfo);
} }
if (Result) { if (Result) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
errs() << "Call operand #" << i << " has unhandled type " errs() << "Call operand #" << i << " has unhandled type "
<< EVT(ArgVT).getEVTString() << "\n"; << EVT(ArgVT).getEVTString() << "\n";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
} }
} else { } else {
// All arguments are treated the same. // All arguments are treated the same.
▲ Show 20 Lines • Show All 6,953 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCTargetMachine.cpp

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Linesbool PPCPassConfig::addILPOpts() {
return true; return true;
} }
bool PPCPassConfig::addInstSelector() { bool PPCPassConfig::addInstSelector() {
// Install an instruction selector. // Install an instruction selector.
addPass(createPPCISelDag(getPPCTargetMachine())); addPass(createPPCISelDag(getPPCTargetMachine()));
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
addPass(createPPCCTRLoopsVerify()); addPass(createPPCCTRLoopsVerify());
#endif #endif
addPass(createPPCVSXCopyPass()); addPass(createPPCVSXCopyPass());
return false; return false;
} }
Show All 35 Lines

lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 LinesgetCallTargetOpValue(const MCInst &MI, unsigned OpNo,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups, STI); return getMachineOpValue(MI, MO, Fixups, STI);
if (MI.getOpcode() == SP::TLS_CALL) { if (MI.getOpcode() == SP::TLS_CALL) {
// No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
// encodeInstruction. // encodeInstruction.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify that the callee is actually __tls_get_addr. // Verify that the callee is actually __tls_get_addr.
const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr()); const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef && assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
"Unexpected expression in TLS_CALL"); "Unexpected expression in TLS_CALL");
const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr()); const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
assert(SymExpr->getSymbol().getName() == "__tls_get_addr" && assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
"Unexpected function for TLS_CALL"); "Unexpected function for TLS_CALL");
#endif #endif
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lib/Target/Sparc/SparcAsmPrinter.cpp

Show First 20 Lines • Show All 294 Lines • ▼ Show 20 Lines
} }
void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
raw_ostream &O) { raw_ostream &O) {
const DataLayout &DL = getDataLayout(); const DataLayout &DL = getDataLayout();
const MachineOperand &MO = MI->getOperand (opNum); const MachineOperand &MO = MI->getOperand (opNum);
SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags(); SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Verify the target flags. // Verify the target flags.
if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) { if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
if (MI->getOpcode() == SP::CALL) if (MI->getOpcode() == SP::CALL)
assert(TF == SparcMCExpr::VK_Sparc_None && assert(TF == SparcMCExpr::VK_Sparc_None &&
"Cannot handle target flags on call address"); "Cannot handle target flags on call address");
else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi) else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
assert((TF == SparcMCExpr::VK_Sparc_HI assert((TF == SparcMCExpr::VK_Sparc_HI
|| TF == SparcMCExpr::VK_Sparc_H44 || TF == SparcMCExpr::VK_Sparc_H44
▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines

lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
/// applies given a specific set of attributes. Hence there are only IC_max /// applies given a specific set of attributes. Hence there are only IC_max
/// entries in this table, rather than 2^(ATTR_max). /// entries in this table, rather than 2^(ATTR_max).
struct ContextDecision { struct ContextDecision {
OpcodeDecision opcodeDecisions[IC_max]; OpcodeDecision opcodeDecisions[IC_max];
}; };
#include "X86GenDisassemblerTables.inc" #include "X86GenDisassemblerTables.inc"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
#define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0) #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
#else #else
#define debug(s) do { } while (0) #define debug(s) do { } while (0)
#endif #endif
/* /*
* contextForAttrs - Client for the instruction context table. Takes a set of * contextForAttrs - Client for the instruction context table. Takes a set of
▲ Show 20 Lines • Show All 1,806 Lines • Show Last 20 Lines

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Lines if ((BaseReg.getReg() != 0 &&
(IndexReg.getReg() != 0 && (IndexReg.getReg() != 0 &&
X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
return true; return true;
return false; return false;
} }
/// Is64BitMemOperand - Return true if the specified instruction has /// Is64BitMemOperand - Return true if the specified instruction has
/// a 64-bit memory operand. Op specifies the operand # of the memoperand. /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
if ((BaseReg.getReg() != 0 && if ((BaseReg.getReg() != 0 &&
X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
(IndexReg.getReg() != 0 && (IndexReg.getReg() != 0 &&
X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
▲ Show 20 Lines • Show All 1,234 Lines • ▼ Show 20 Lines if (TSFlags & X86II::VEX_I8IMM) {
X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
CurByte, OS, Fixups); CurByte, OS, Fixups);
} }
} }
if (TSFlags & X86II::Has3DNow0F0FOpcode) if (TSFlags & X86II::Has3DNow0F0FOpcode)
EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// FIXME: Verify. // FIXME: Verify.
if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
errs() << "Cannot encode all operands of: "; errs() << "Cannot encode all operands of: ";
MI.dump(); MI.dump();
errs() << '\n'; errs() << '\n';
abort(); abort();
} }
#endif #endif
} }

lib/Target/X86/X86FloatingPoint.cpp

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines private:
unsigned RegMap[NumFPRegs]; unsigned RegMap[NumFPRegs];
// Set up our stack model to match the incoming registers to MBB. // Set up our stack model to match the incoming registers to MBB.
void setupBlockStack(); void setupBlockStack();
// Shuffle live registers to match the expectations of successor blocks. // Shuffle live registers to match the expectations of successor blocks.
void finishBlockStack(); void finishBlockStack();
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dumpStack() const { void dumpStack() const {
dbgs() << "Stack contents:"; dbgs() << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) { for (unsigned i = 0; i != StackTop; ++i) {
dbgs() << " FP" << Stack[i]; dbgs() << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
} }
} }
#endif #endif
▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines struct TableEntry {
} }
friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V, friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
const TableEntry &TE) { const TableEntry &TE) {
return V < TE.from; return V < TE.from;
} }
}; };
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
for (unsigned i = 0; i != NumEntries-1; ++i) for (unsigned i = 0; i != NumEntries-1; ++i)
if (!(Table[i] < Table[i+1])) return false; if (!(Table[i] < Table[i+1])) return false;
return true; return true;
} }
#endif #endif
static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
if (I != Table+N && I->from == Opcode) if (I != Table+N && I->from == Opcode)
return I->to; return I->to;
return -1; return -1;
} }
#ifdef NDEBUG #ifdef LLVM_NDEBUG
#define ASSERT_SORTED(TABLE) #define ASSERT_SORTED(TABLE)
#else #else
#define ASSERT_SORTED(TABLE) \ #define ASSERT_SORTED(TABLE) \
{ static bool TABLE##Checked = false; \ { static bool TABLE##Checked = false; \
if (!TABLE##Checked) { \ if (!TABLE##Checked) { \
assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \ assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
"All lookup tables must be sorted for efficient access!"); \ "All lookup tables must be sorted for efficient access!"); \
TABLE##Checked = true; \ TABLE##Checked = true; \
▲ Show 20 Lines • Show All 454 Lines • ▼ Show 20 Lines
/// non-fp operands after their FP operands. /// non-fp operands after their FP operands.
/// ///
/// Examples: /// Examples:
/// R1 = fchs R2 /// R1 = fchs R2
/// R1 = fadd R2, [mem] /// R1 = fadd R2, [mem]
/// ///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I; MachineInstr *MI = I;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned NumOps = MI->getDesc().getNumOperands(); unsigned NumOps = MI->getDesc().getNumOperands();
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
#endif #endif
// Is this the last use of the source register? // Is this the last use of the source register?
unsigned Reg = getFPReg(MI->getOperand(1)); unsigned Reg = getFPReg(MI->getOperand(1));
bool KillsSrc = MI->killsRegister(X86::FP0+Reg); bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
▲ Show 20 Lines • Show All 393 Lines • ▼ Show 20 Lines case TargetOpcode::INLINEASM: {
unsigned STPopped = STUses & (STDefs | STClobbers); unsigned STPopped = STUses & (STDefs | STClobbers);
if (STPopped && !isMask_32(STPopped)) if (STPopped && !isMask_32(STPopped))
MI->emitError("implicitly popped regs must be last on the x87 stack"); MI->emitError("implicitly popped regs must be last on the x87 stack");
unsigned NumSTPopped = countTrailingOnes(STPopped); unsigned NumSTPopped = countTrailingOnes(STPopped);
DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops " DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
<< NumSTPopped << ", and defines " << NumSTDefs << " regs.\n"); << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If any input operand uses constraint "f", all output register // If any input operand uses constraint "f", all output register
// constraints must be early-clobber defs. // constraints must be early-clobber defs.
for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I) for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I)
if (FRegIdx.count(I)) { if (FRegIdx.count(I)) {
assert((1 << getFPReg(MI->getOperand(I)) & STDefs) == 0 && assert((1 << getFPReg(MI->getOperand(I)) & STDefs) == 0 &&
"Operands with constraint \"f\" cannot overlap with defs"); "Operands with constraint \"f\" cannot overlap with defs");
} }
#endif #endif
▲ Show 20 Lines • Show All 234 Lines • Show Last 20 Lines

lib/Target/X86/X86FrameLowering.cpp

Show First 20 Lines • Show All 1,194 Lines • ▼ Show 20 Lines
} }
// Simplified from getFrameIndexOffset keeping only StackPointer cases // Simplified from getFrameIndexOffset keeping only StackPointer cases
int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const { int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
const MachineFrameInfo *MFI = MF.getFrameInfo(); const MachineFrameInfo *MFI = MF.getFrameInfo();
// Does not include any dynamic realign. // Does not include any dynamic realign.
const uint64_t StackSize = MFI->getStackSize(); const uint64_t StackSize = MFI->getStackSize();
{ {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Note: LLVM arranges the stack as: // Note: LLVM arranges the stack as:
// Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP) // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
// > "Stack Slots" (<--SP) // > "Stack Slots" (<--SP)
// We can always address StackSlots from RSP. We can usually (unless // We can always address StackSlots from RSP. We can usually (unless
// needsStackRealignment) address CSRs from RSP, but sometimes need to // needsStackRealignment) address CSRs from RSP, but sometimes need to
// address them from RBP. FixedObjects can be placed anywhere in the stack // address them from RBP. FixedObjects can be placed anywhere in the stack
// frame depending on their specific requirements (i.e. we can actually // frame depending on their specific requirements (i.e. we can actually
// refer to arguments to the function which are stored in the *callers* // refer to arguments to the function which are stored in the *callers*
▲ Show 20 Lines • Show All 704 Lines • Show Last 20 Lines

lib/Target/X86/X86ISelDAGToDAG.cpp

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines bool isRIPRelative() const {
return false; return false;
} }
void setBaseReg(SDValue Reg) { void setBaseReg(SDValue Reg) {
BaseType = RegBase; BaseType = RegBase;
Base_Reg = Reg; Base_Reg = Reg;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dump() { void dump() {
dbgs() << "X86ISelAddressMode " << this << '\n'; dbgs() << "X86ISelAddressMode " << this << '\n';
dbgs() << "Base_Reg "; dbgs() << "Base_Reg ";
if (Base_Reg.getNode()) if (Base_Reg.getNode())
Base_Reg.getNode()->dump(); Base_Reg.getNode()->dump();
else else
dbgs() << "nul"; dbgs() << "nul";
dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n' dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
▲ Show 20 Lines • Show All 2,813 Lines • Show Last 20 Lines

lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 13,578 Lines • ▼ Show 20 Linesstatic SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
SDValue Op1 = Op.getOperand(1); SDValue Op1 = Op.getOperand(1);
SDValue CC = Op.getOperand(2); SDValue CC = Op.getOperand(2);
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint(); bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
SDLoc dl(Op); SDLoc dl(Op);
if (isFP) { if (isFP) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
MVT EltVT = Op0.getSimpleValueType().getVectorElementType(); MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
assert(EltVT == MVT::f32 || EltVT == MVT::f64); assert(EltVT == MVT::f32 || EltVT == MVT::f64);
#endif #endif
unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1); unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
unsigned Opc = X86ISD::CMPP; unsigned Opc = X86ISD::CMPP;
if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) { if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
assert(VT.getVectorNumElements() <= 16); assert(VT.getVectorNumElements() <= 16);
▲ Show 20 Lines • Show All 2,847 Lines • ▼ Show 20 Lines unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("ebp", X86::EBP) .Case("ebp", X86::EBP)
.Case("rbp", X86::RBP) .Case("rbp", X86::RBP)
.Default(0); .Default(0);
if (Reg == X86::EBP || Reg == X86::RBP) { if (Reg == X86::EBP || Reg == X86::RBP) {
if (!TFI.hasFP(MF)) if (!TFI.hasFP(MF))
report_fatal_error("register " + StringRef(RegName) + report_fatal_error("register " + StringRef(RegName) +
" is allocatable: function has no frame pointer"); " is allocatable: function has no frame pointer");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
else { else {
const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo(); const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
unsigned FrameReg = unsigned FrameReg =
RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction()); RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
assert((FrameReg == X86::EBP || FrameReg == X86::RBP) && assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
"Invalid Frame Register!"); "Invalid Frame Register!");
} }
#endif #endif
▲ Show 20 Lines • Show All 5,130 Lines • ▼ Show 20 Linesstatic SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary); bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
(void)HaveMask; (void)HaveMask;
assert(HaveMask); assert(HaveMask);
// If we have more than 128-bits, only the low 128-bits of shuffle mask // If we have more than 128-bits, only the low 128-bits of shuffle mask
// matter. Check that the upper masks are repeats and remove them. // matter. Check that the upper masks are repeats and remove them.
if (VT.getSizeInBits() > 128) { if (VT.getSizeInBits() > 128) {
int LaneElts = 128 / VT.getScalarSizeInBits(); int LaneElts = 128 / VT.getScalarSizeInBits();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i) for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
for (int j = 0; j < LaneElts; ++j) for (int j = 0; j < LaneElts; ++j)
assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) && assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
"Mask doesn't repeat in high 128-bit lanes!"); "Mask doesn't repeat in high 128-bit lanes!");
#endif #endif
Mask.resize(LaneElts); Mask.resize(LaneElts);
} }
▲ Show 20 Lines • Show All 4,976 Lines • Show Last 20 Lines

lib/Target/X86/X86SelectionDAGInfo.cpp

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 LinesX86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
SDValue Dst, SDValue Src, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool isVolatile,
MachinePointerInfo DstPtrInfo) const { MachinePointerInfo DstPtrInfo) const {
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
const X86Subtarget &Subtarget = const X86Subtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<X86Subtarget>(); DAG.getMachineFunction().getSubtarget<X86Subtarget>();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If the base register might conflict with our physical registers, bail out. // If the base register might conflict with our physical registers, bail out.
const unsigned ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, const unsigned ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
X86::ECX, X86::EAX, X86::EDI}; X86::ECX, X86::EAX, X86::EDI};
assert(!isBaseRegConflictPossible(DAG, ClobberSet)); assert(!isBaseRegConflictPossible(DAG, ClobberSet));
#endif #endif
// If to a segment-relative address space, use the default lowering. // If to a segment-relative address space, use the default lowering.
if (DstPtrInfo.getAddrSpace() >= 256) if (DstPtrInfo.getAddrSpace() >= 256)
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lib/Target/X86/X86WinEHState.cpp

Show First 20 Lines • Show All 518 Lines • ▼ Show 20 Lines for (auto I = BB.begin(), E = BB.end(); I != E; ++I) {
assert(!ActionList.empty()); assert(!ActionList.empty());
CurState += ActionList.size(); CurState += ActionList.size();
State += ActionList.size() - 1; State += ActionList.size() - 1;
// Remember all the __except block targets. // Remember all the __except block targets.
for (auto &Handler : ActionList) { for (auto &Handler : ActionList) {
if (auto *CH = dyn_cast<CatchHandler>(Handler.get())) { if (auto *CH = dyn_cast<CatchHandler>(Handler.get())) {
auto *BA = cast<BlockAddress>(CH->getHandlerBlockOrFunc()); auto *BA = cast<BlockAddress>(CH->getHandlerBlockOrFunc());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (BasicBlock *Pred : predecessors(BA->getBasicBlock())) for (BasicBlock *Pred : predecessors(BA->getBasicBlock()))
assert(Pred->isLandingPad() && assert(Pred->isLandingPad() &&
"WinEHPrepare failed to split block"); "WinEHPrepare failed to split block");
#endif #endif
ExceptBlocks.insert(BA->getBasicBlock()); ExceptBlocks.insert(BA->getBasicBlock());
} }
} }
} }
Show All 21 Lines

lib/Target/XCore/XCoreFrameLowering.cpp

Show First 20 Lines • Show All 492 Lines • ▼ Show 20 Lines if (Amount != 0) {
Amount = (Amount+Align-1)/Align*Align; Amount = (Amount+Align-1)/Align*Align;
assert(Amount%4 == 0); assert(Amount%4 == 0);
Amount /= 4; Amount /= 4;
bool isU6 = isImmU6(Amount); bool isU6 = isImmU6(Amount);
if (!isU6 && !isImmU16(Amount)) { if (!isU6 && !isImmU16(Amount)) {
// FIX could emit multiple instructions in this case. // FIX could emit multiple instructions in this case.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
errs() << "eliminateCallFramePseudoInstr size too big: " errs() << "eliminateCallFramePseudoInstr size too big: "
<< Amount << "\n"; << Amount << "\n";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
MachineInstr *New; MachineInstr *New;
if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
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lib/Target/XCore/XCoreISelLowering.cpp

Show First 20 Lines • Show All 1,330 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
SDValue ArgIn; SDValue ArgIn;
if (VA.isRegLoc()) { if (VA.isRegLoc()) {
// Arguments passed in registers // Arguments passed in registers
EVT RegVT = VA.getLocVT(); EVT RegVT = VA.getLocVT();
switch (RegVT.getSimpleVT().SimpleTy) { switch (RegVT.getSimpleVT().SimpleTy) {
default: default:
{ {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
errs() << "LowerFormalArguments Unhandled argument type: " errs() << "LowerFormalArguments Unhandled argument type: "
<< RegVT.getSimpleVT().SimpleTy << "\n"; << RegVT.getSimpleVT().SimpleTy << "\n";
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
case MVT::i32: case MVT::i32:
unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
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lib/Target/XCore/XCoreRegisterInfo.cpp

Show First 20 Lines • Show All 268 Lines • ▼ Show 20 LinesXCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineFunction &MF = *MI.getParent()->getParent(); MachineFunction &MF = *MI.getParent()->getParent();
const XCoreInstrInfo &TII = const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
const XCoreFrameLowering *TFI = getFrameLowering(MF); const XCoreFrameLowering *TFI = getFrameLowering(MF);
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
int StackSize = MF.getFrameInfo()->getStackSize(); int StackSize = MF.getFrameInfo()->getStackSize();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(errs() << "\nFunction : " DEBUG(errs() << "\nFunction : "
<< MF.getName() << "\n"); << MF.getName() << "\n");
DEBUG(errs() << "<--------->\n"); DEBUG(errs() << "<--------->\n");
DEBUG(MI.print(errs())); DEBUG(MI.print(errs()));
DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"); DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
DEBUG(errs() << "FrameOffset : " << Offset << "\n"); DEBUG(errs() << "FrameOffset : " << Offset << "\n");
DEBUG(errs() << "StackSize : " << StackSize << "\n"); DEBUG(errs() << "StackSize : " << StackSize << "\n");
#endif #endif
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lib/Transforms/InstCombine/InstCombineAddSub.cpp

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Lines private:
Value *createNaryFAdd(const AddendVect& Opnds, unsigned InstrQuota); Value *createNaryFAdd(const AddendVect& Opnds, unsigned InstrQuota);
void createInstPostProc(Instruction *NewInst, bool NoNumber = false); void createInstPostProc(Instruction *NewInst, bool NoNumber = false);
InstCombiner::BuilderTy *Builder; InstCombiner::BuilderTy *Builder;
Instruction *Instr; Instruction *Instr;
private: private:
// Debugging stuff are clustered here. // Debugging stuff are clustered here.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
unsigned CreateInstrNum; unsigned CreateInstrNum;
void initCreateInstNum() { CreateInstrNum = 0; } void initCreateInstNum() { CreateInstrNum = 0; }
void incCreateInstNum() { CreateInstrNum++; } void incCreateInstNum() { CreateInstrNum++; }
#else #else
void initCreateInstNum() {} void initCreateInstNum() {}
void incCreateInstNum() {} void incCreateInstNum() {}
#endif #endif
}; };
▲ Show 20 Lines • Show All 542 Lines • ▼ Show 20 Lines for (AddendVect::const_iterator I = Opnds.begin(), E = Opnds.end();
LastValNeedNeg = false; LastValNeedNeg = false;
} }
if (LastValNeedNeg) { if (LastValNeedNeg) {
LastVal = createFNeg(LastVal); LastVal = createFNeg(LastVal);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(CreateInstrNum == InstrNeeded && assert(CreateInstrNum == InstrNeeded &&
"Inconsistent in instruction numbers"); "Inconsistent in instruction numbers");
#endif #endif
return LastVal; return LastVal;
} }
Value *FAddCombine::createFSub(Value *Opnd0, Value *Opnd1) { Value *FAddCombine::createFSub(Value *Opnd0, Value *Opnd1) {
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lib/Transforms/InstCombine/InstructionCombining.cpp

Show First 20 Lines • Show All 2,762 Lines • ▼ Show 20 Lines if (I->hasOneUse()) {
} }
} }
} }
// Now that we have an instruction, try combining it to simplify it. // Now that we have an instruction, try combining it to simplify it.
Builder->SetInsertPoint(I->getParent(), I); Builder->SetInsertPoint(I->getParent(), I);
Builder->SetCurrentDebugLocation(I->getDebugLoc()); Builder->SetCurrentDebugLocation(I->getDebugLoc());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
std::string OrigI; std::string OrigI;
#endif #endif
DEBUG(raw_string_ostream SS(OrigI); I->print(SS); OrigI = SS.str();); DEBUG(raw_string_ostream SS(OrigI); I->print(SS); OrigI = SS.str(););
DEBUG(dbgs() << "IC: Visiting: " << OrigI << '\n'); DEBUG(dbgs() << "IC: Visiting: " << OrigI << '\n');
if (Instruction *Result = visit(*I)) { if (Instruction *Result = visit(*I)) {
++NumCombined; ++NumCombined;
// Should we replace the old instruction with a new one? // Should we replace the old instruction with a new one?
Show All 21 Lines if (Instruction *Result = visit(*I)) {
// insertion point. // insertion point.
if (!isa<PHINode>(Result) && isa<PHINode>(InsertPos)) if (!isa<PHINode>(Result) && isa<PHINode>(InsertPos))
InsertPos = InstParent->getFirstInsertionPt(); InsertPos = InstParent->getFirstInsertionPt();
InstParent->getInstList().insert(InsertPos, Result); InstParent->getInstList().insert(InsertPos, Result);
EraseInstFromFunction(*I); EraseInstFromFunction(*I);
} else { } else {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(dbgs() << "IC: Mod = " << OrigI << '\n' DEBUG(dbgs() << "IC: Mod = " << OrigI << '\n'
<< " New = " << *I << '\n'); << " New = " << *I << '\n');
#endif #endif
// If the instruction was modified, it's possible that it is now dead. // If the instruction was modified, it's possible that it is now dead.
// if so, remove it. // if so, remove it.
if (isInstructionTriviallyDead(I, TLI)) { if (isInstructionTriviallyDead(I, TLI)) {
EraseInstFromFunction(*I); EraseInstFromFunction(*I);
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lib/Transforms/Instrumentation/MemorySanitizer.cpp

Show First 20 Lines • Show All 1,149 Lines • ▼ Show 20 Linesstruct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
/// \brief Remember the place where a shadow check should be inserted. /// \brief Remember the place where a shadow check should be inserted.
/// ///
/// This location will be later instrumented with a check that will print a /// This location will be later instrumented with a check that will print a
/// UMR warning in runtime if the shadow value is not 0. /// UMR warning in runtime if the shadow value is not 0.
void insertShadowCheck(Value *Shadow, Value *Origin, Instruction *OrigIns) { void insertShadowCheck(Value *Shadow, Value *Origin, Instruction *OrigIns) {
assert(Shadow); assert(Shadow);
if (!InsertChecks) return; if (!InsertChecks) return;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Type *ShadowTy = Shadow->getType(); Type *ShadowTy = Shadow->getType();
assert((isa<IntegerType>(ShadowTy) || isa<VectorType>(ShadowTy)) && assert((isa<IntegerType>(ShadowTy) || isa<VectorType>(ShadowTy)) &&
"Can only insert checks for integer and vector shadow types"); "Can only insert checks for integer and vector shadow types");
#endif #endif
InstrumentationList.push_back( InstrumentationList.push_back(
ShadowOriginAndInsertPoint(Shadow, Origin, OrigIns)); ShadowOriginAndInsertPoint(Shadow, Origin, OrigIns));
} }
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lib/Transforms/ObjCARC/ObjCARCOpts.cpp

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
STATISTIC(NumNoops, "Number of no-op objc calls eliminated"); STATISTIC(NumNoops, "Number of no-op objc calls eliminated");
STATISTIC(NumPartialNoops, "Number of partially no-op objc calls eliminated"); STATISTIC(NumPartialNoops, "Number of partially no-op objc calls eliminated");
STATISTIC(NumAutoreleases,"Number of autoreleases converted to releases"); STATISTIC(NumAutoreleases,"Number of autoreleases converted to releases");
STATISTIC(NumRets, "Number of return value forwarding " STATISTIC(NumRets, "Number of return value forwarding "
"retain+autoreleases eliminated"); "retain+autoreleases eliminated");
STATISTIC(NumRRs, "Number of retain+release paths eliminated"); STATISTIC(NumRRs, "Number of retain+release paths eliminated");
STATISTIC(NumPeeps, "Number of calls peephole-optimized"); STATISTIC(NumPeeps, "Number of calls peephole-optimized");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
STATISTIC(NumRetainsBeforeOpt, STATISTIC(NumRetainsBeforeOpt,
"Number of retains before optimization"); "Number of retains before optimization");
STATISTIC(NumReleasesBeforeOpt, STATISTIC(NumReleasesBeforeOpt,
"Number of releases before optimization"); "Number of releases before optimization");
STATISTIC(NumRetainsAfterOpt, STATISTIC(NumRetainsAfterOpt,
"Number of retains after optimization"); "Number of retains after optimization");
STATISTIC(NumReleasesAfterOpt, STATISTIC(NumReleasesAfterOpt,
"Number of releases after optimization"); "Number of releases after optimization");
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines bool PerformCodePlacement(DenseMap<const BasicBlock *, BBState> &BBStates,
DenseMap<Value *, RRInfo> &Releases, Module *M); DenseMap<Value *, RRInfo> &Releases, Module *M);
void OptimizeWeakCalls(Function &F); void OptimizeWeakCalls(Function &F);
bool OptimizeSequences(Function &F); bool OptimizeSequences(Function &F);
void OptimizeReturns(Function &F); void OptimizeReturns(Function &F);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void GatherStatistics(Function &F, bool AfterOptimization = false); void GatherStatistics(Function &F, bool AfterOptimization = false);
#endif #endif
void getAnalysisUsage(AnalysisUsage &AU) const override; void getAnalysisUsage(AnalysisUsage &AU) const override;
bool doInitialization(Module &M) override; bool doInitialization(Module &M) override;
bool runOnFunction(Function &F) override; bool runOnFunction(Function &F) override;
void releaseMemory() override; void releaseMemory() override;
▲ Show 20 Lines • Show All 1,582 Lines • ▼ Show 20 Lines for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) {
++NumRets; ++NumRets;
DEBUG(dbgs() << "Erasing: " << *Retain << "\nErasing: " DEBUG(dbgs() << "Erasing: " << *Retain << "\nErasing: "
<< *Autorelease << "\n"); << *Autorelease << "\n");
EraseInstruction(Retain); EraseInstruction(Retain);
EraseInstruction(Autorelease); EraseInstruction(Autorelease);
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void void
ObjCARCOpt::GatherStatistics(Function &F, bool AfterOptimization) { ObjCARCOpt::GatherStatistics(Function &F, bool AfterOptimization) {
llvm::Statistic &NumRetains = llvm::Statistic &NumRetains =
AfterOptimization? NumRetainsAfterOpt : NumRetainsBeforeOpt; AfterOptimization? NumRetainsAfterOpt : NumRetainsBeforeOpt;
llvm::Statistic &NumReleases = llvm::Statistic &NumReleases =
AfterOptimization? NumReleasesAfterOpt : NumReleasesBeforeOpt; AfterOptimization? NumReleasesAfterOpt : NumReleasesBeforeOpt;
for (inst_iterator I = inst_begin(&F), E = inst_end(&F); I != E; ) { for (inst_iterator I = inst_begin(&F), E = inst_end(&F); I != E; ) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesbool ObjCARCOpt::runOnFunction(Function &F) {
Changed = false; Changed = false;
DEBUG(dbgs() << "<<< ObjCARCOpt: Visiting Function: " << F.getName() << " >>>" DEBUG(dbgs() << "<<< ObjCARCOpt: Visiting Function: " << F.getName() << " >>>"
"\n"); "\n");
PA.setAA(&getAnalysis<AliasAnalysis>()); PA.setAA(&getAnalysis<AliasAnalysis>());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (AreStatisticsEnabled()) { if (AreStatisticsEnabled()) {
GatherStatistics(F, false); GatherStatistics(F, false);
} }
#endif #endif
// This pass performs several distinct transformations. As a compile-time aid // This pass performs several distinct transformations. As a compile-time aid
// when compiling code that isn't ObjC, skip these if the relevant ObjC // when compiling code that isn't ObjC, skip these if the relevant ObjC
// library functions aren't declared. // library functions aren't declared.
Show All 21 Lines if (UsedInThisFunction & (1 << unsigned(ARCInstKind::Release)))
while (OptimizeSequences(F)) {} while (OptimizeSequences(F)) {}
// Optimizations if objc_autorelease is used. // Optimizations if objc_autorelease is used.
if (UsedInThisFunction & ((1 << unsigned(ARCInstKind::Autorelease)) | if (UsedInThisFunction & ((1 << unsigned(ARCInstKind::Autorelease)) |
(1 << unsigned(ARCInstKind::AutoreleaseRV)))) (1 << unsigned(ARCInstKind::AutoreleaseRV))))
OptimizeReturns(F); OptimizeReturns(F);
// Gather statistics after optimization. // Gather statistics after optimization.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (AreStatisticsEnabled()) { if (AreStatisticsEnabled()) {
GatherStatistics(F, true); GatherStatistics(F, true);
} }
#endif #endif
DEBUG(dbgs() << "\n"); DEBUG(dbgs() << "\n");
return Changed; return Changed;
} }
void ObjCARCOpt::releaseMemory() { void ObjCARCOpt::releaseMemory() {
PA.clear(); PA.clear();
} }
/// @} /// @}
/// ///

lib/Transforms/Scalar/GVN.cpp

Show First 20 Lines • Show All 735 Lines • ▼ Show 20 Lines
INITIALIZE_PASS_BEGIN(GVN, "gvn", "Global Value Numbering", false, false) INITIALIZE_PASS_BEGIN(GVN, "gvn", "Global Value Numbering", false, false)
INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker) INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
INITIALIZE_PASS_DEPENDENCY(MemoryDependenceAnalysis) INITIALIZE_PASS_DEPENDENCY(MemoryDependenceAnalysis)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
INITIALIZE_AG_DEPENDENCY(AliasAnalysis) INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
INITIALIZE_PASS_END(GVN, "gvn", "Global Value Numbering", false, false) INITIALIZE_PASS_END(GVN, "gvn", "Global Value Numbering", false, false)
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void GVN::dump(DenseMap<uint32_t, Value*>& d) { void GVN::dump(DenseMap<uint32_t, Value*>& d) {
errs() << "{\n"; errs() << "{\n";
for (DenseMap<uint32_t, Value*>::iterator I = d.begin(), for (DenseMap<uint32_t, Value*>::iterator I = d.begin(),
E = d.end(); I != E; ++I) { E = d.end(); I != E; ++I) {
errs() << I->first << "\n"; errs() << I->first << "\n";
I->second->dump(); I->second->dump();
} }
errs() << "}\n"; errs() << "}\n";
▲ Show 20 Lines • Show All 2,062 Lines • Show Last 20 Lines

lib/Transforms/Scalar/IndVarSimplify.cpp

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
#define DEBUG_TYPE "indvars" #define DEBUG_TYPE "indvars"
STATISTIC(NumWidened , "Number of indvars widened"); STATISTIC(NumWidened , "Number of indvars widened");
STATISTIC(NumReplaced , "Number of exit values replaced"); STATISTIC(NumReplaced , "Number of exit values replaced");
STATISTIC(NumLFTR , "Number of loop exit tests replaced"); STATISTIC(NumLFTR , "Number of loop exit tests replaced");
STATISTIC(NumElimExt , "Number of IV sign/zero extends eliminated"); STATISTIC(NumElimExt , "Number of IV sign/zero extends eliminated");
STATISTIC(NumElimIV , "Number of congruent IVs eliminated"); STATISTIC(NumElimIV , "Number of congruent IVs eliminated");
// Trip count verification can be enabled by default under NDEBUG if we // Trip count verification can be enabled by default under LLVM_NDEBUG if we
// implement a strong expression equivalence checker in SCEV. Until then, we // implement a strong expression equivalence checker in SCEV. Until then, we
// use the verify-indvars flag, which may assert in some cases. // use the verify-indvars flag, which may assert in some cases.
static cl::opt<bool> VerifyIndvars( static cl::opt<bool> VerifyIndvars(
"verify-indvars", cl::Hidden, "verify-indvars", cl::Hidden,
cl::desc("Verify the ScalarEvolution result after running indvars")); cl::desc("Verify the ScalarEvolution result after running indvars"));
static cl::opt<bool> ReduceLiveIVs("liv-reduce", cl::Hidden, static cl::opt<bool> ReduceLiveIVs("liv-reduce", cl::Hidden,
cl::desc("Reduce live induction variables.")); cl::desc("Reduce live induction variables."));
▲ Show 20 Lines • Show All 1,937 Lines • ▼ Show 20 Linesbool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) {
// If there are any floating-point recurrences, attempt to // If there are any floating-point recurrences, attempt to
// transform them to use integer recurrences. // transform them to use integer recurrences.
RewriteNonIntegerIVs(L); RewriteNonIntegerIVs(L);
const SCEV *BackedgeTakenCount = SE->getBackedgeTakenCount(L); const SCEV *BackedgeTakenCount = SE->getBackedgeTakenCount(L);
// Create a rewriter object which we'll use to transform the code with. // Create a rewriter object which we'll use to transform the code with.
SCEVExpander Rewriter(*SE, DL, "indvars"); SCEVExpander Rewriter(*SE, DL, "indvars");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Rewriter.setDebugType(DEBUG_TYPE); Rewriter.setDebugType(DEBUG_TYPE);
#endif #endif
// Eliminate redundant IV users. // Eliminate redundant IV users.
// //
// Simplification works best when run before other consumers of SCEV. We // Simplification works best when run before other consumers of SCEV. We
// attempt to avoid evaluating SCEVs for sign/zero extend operations until // attempt to avoid evaluating SCEVs for sign/zero extend operations until
// other expressions involving loop IVs have been evaluated. This helps SCEV // other expressions involving loop IVs have been evaluated. This helps SCEV
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines#endif
// Clean up dead instructions. // Clean up dead instructions.
Changed |= DeleteDeadPHIs(L->getHeader(), TLI); Changed |= DeleteDeadPHIs(L->getHeader(), TLI);
// Check a post-condition. // Check a post-condition.
assert(L->isLCSSAForm(*DT) && assert(L->isLCSSAForm(*DT) &&
"Indvars did not leave the loop in lcssa form!"); "Indvars did not leave the loop in lcssa form!");
// Verify that LFTR, and any other change have not interfered with SCEV's // Verify that LFTR, and any other change have not interfered with SCEV's
// ability to compute trip count. // ability to compute trip count.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (VerifyIndvars && !isa<SCEVCouldNotCompute>(BackedgeTakenCount)) { if (VerifyIndvars && !isa<SCEVCouldNotCompute>(BackedgeTakenCount)) {
SE->forgetLoop(L); SE->forgetLoop(L);
const SCEV *NewBECount = SE->getBackedgeTakenCount(L); const SCEV *NewBECount = SE->getBackedgeTakenCount(L);
if (SE->getTypeSizeInBits(BackedgeTakenCount->getType()) < if (SE->getTypeSizeInBits(BackedgeTakenCount->getType()) <
SE->getTypeSizeInBits(NewBECount->getType())) SE->getTypeSizeInBits(NewBECount->getType()))
NewBECount = SE->getTruncateOrNoop(NewBECount, NewBECount = SE->getTruncateOrNoop(NewBECount,
BackedgeTakenCount->getType()); BackedgeTakenCount->getType());
else else
BackedgeTakenCount = SE->getTruncateOrNoop(BackedgeTakenCount, BackedgeTakenCount = SE->getTruncateOrNoop(BackedgeTakenCount,
NewBECount->getType()); NewBECount->getType());
assert(BackedgeTakenCount == NewBECount && "indvars must preserve SCEV"); assert(BackedgeTakenCount == NewBECount && "indvars must preserve SCEV");
} }
#endif #endif
return Changed; return Changed;
} }

lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines if (Length)
Length->print(OS); Length->print(OS);
else else
OS << "(null)"; OS << "(null)";
OS << "\n Branch: "; OS << "\n Branch: ";
getBranch()->print(OS); getBranch()->print(OS);
OS << "\n"; OS << "\n";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dump() { void dump() {
print(dbgs()); print(dbgs());
} }
#endif #endif
BranchInst *getBranch() const { return Branch; } BranchInst *getBranch() const { return Branch; }
/// Represents an signed integer range [Range.getBegin(), Range.getEnd()). If /// Represents an signed integer range [Range.getBegin(), Range.getEnd()). If
▲ Show 20 Lines • Show All 1,330 Lines • Show Last 20 Lines

lib/Transforms/Scalar/JumpThreading.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Linesnamespace {
/// if (X < 3) { /// if (X < 3) {
/// ///
/// In this case, the unconditional branch at the end of the first if can be /// In this case, the unconditional branch at the end of the first if can be
/// revectored to the false side of the second if. /// revectored to the false side of the second if.
/// ///
class JumpThreading : public FunctionPass { class JumpThreading : public FunctionPass {
TargetLibraryInfo *TLI; TargetLibraryInfo *TLI;
LazyValueInfo *LVI; LazyValueInfo *LVI;
#ifdef NDEBUG #ifdef LLVM_NDEBUG
SmallPtrSet<BasicBlock*, 16> LoopHeaders; SmallPtrSet<BasicBlock*, 16> LoopHeaders;
#else #else
SmallSet<AssertingVH<BasicBlock>, 16> LoopHeaders; SmallSet<AssertingVH<BasicBlock>, 16> LoopHeaders;
#endif #endif
DenseSet<std::pair<Value*, BasicBlock*> > RecursionSet; DenseSet<std::pair<Value*, BasicBlock*> > RecursionSet;
unsigned BBDupThreshold; unsigned BBDupThreshold;
▲ Show 20 Lines • Show All 1,636 Lines • Show Last 20 Lines

lib/Transforms/Scalar/LICM.cpp

Show First 20 Lines • Show All 582 Lines • ▼ Show 20 Linesstatic bool sink(Instruction &I, const LoopInfo *LI, const DominatorTree *DT,
const Loop *CurLoop, AliasSetTracker *CurAST ) { const Loop *CurLoop, AliasSetTracker *CurAST ) {
DEBUG(dbgs() << "LICM sinking instruction: " << I << "\n"); DEBUG(dbgs() << "LICM sinking instruction: " << I << "\n");
bool Changed = false; bool Changed = false;
if (isa<LoadInst>(I)) ++NumMovedLoads; if (isa<LoadInst>(I)) ++NumMovedLoads;
else if (isa<CallInst>(I)) ++NumMovedCalls; else if (isa<CallInst>(I)) ++NumMovedCalls;
++NumSunk; ++NumSunk;
Changed = true; Changed = true;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
SmallVector<BasicBlock *, 32> ExitBlocks; SmallVector<BasicBlock *, 32> ExitBlocks;
CurLoop->getUniqueExitBlocks(ExitBlocks); CurLoop->getUniqueExitBlocks(ExitBlocks);
SmallPtrSet<BasicBlock *, 32> ExitBlockSet(ExitBlocks.begin(), SmallPtrSet<BasicBlock *, 32> ExitBlockSet(ExitBlocks.begin(),
ExitBlocks.end()); ExitBlocks.end());
#endif #endif
// Clones of this instruction. Don't create more than one per exit block! // Clones of this instruction. Don't create more than one per exit block!
SmallDenseMap<BasicBlock *, Instruction *, 32> SunkCopies; SmallDenseMap<BasicBlock *, Instruction *, 32> SunkCopies;
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lib/Transforms/Scalar/LoopDistribute.cpp

Show First 20 Lines • Show All 464 Lines • ▼ Show 20 Lines void print(raw_ostream &OS) const {
for (const auto &P : PartitionContainer) { for (const auto &P : PartitionContainer) {
OS << "Partition " << Index++ << " (" << &P << "):\n"; OS << "Partition " << Index++ << " (" << &P << "):\n";
P.print(); P.print();
} }
} }
void dump() const { print(dbgs()); } void dump() const { print(dbgs()); }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
friend raw_ostream &operator<<(raw_ostream &OS, friend raw_ostream &operator<<(raw_ostream &OS,
const InstPartitionContainer &Partitions) { const InstPartitionContainer &Partitions) {
Partitions.print(OS); Partitions.print(OS);
return OS; return OS;
} }
#endif #endif
void printBlocks() const { void printBlocks() const {
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lib/Transforms/Scalar/LoopStrengthReduce.cpp

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
// Temporary flag to cleanup congruent phis after LSR phi expansion. // Temporary flag to cleanup congruent phis after LSR phi expansion.
// It's currently disabled until we can determine whether it's truly useful or // It's currently disabled until we can determine whether it's truly useful or
// not. The flag should be removed after the v3.0 release. // not. The flag should be removed after the v3.0 release.
// This is now needed for ivchains. // This is now needed for ivchains.
static cl::opt<bool> EnablePhiElim( static cl::opt<bool> EnablePhiElim(
"enable-lsr-phielim", cl::Hidden, cl::init(true), "enable-lsr-phielim", cl::Hidden, cl::init(true),
cl::desc("Enable LSR phi elimination")); cl::desc("Enable LSR phi elimination"));
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Stress test IV chain generation. // Stress test IV chain generation.
static cl::opt<bool> StressIVChain( static cl::opt<bool> StressIVChain(
"stress-ivchain", cl::Hidden, cl::init(false), "stress-ivchain", cl::Hidden, cl::init(false),
cl::desc("Stress test LSR IV chains")); cl::desc("Stress test LSR IV chains"));
#else #else
static bool StressIVChain = false; static bool StressIVChain = false;
#endif #endif
Show All 11 Lines
}; };
} }
void RegSortData::print(raw_ostream &OS) const { void RegSortData::print(raw_ostream &OS) const {
OS << "[NumUses=" << UsedByIndices.count() << ']'; OS << "[NumUses=" << UsedByIndices.count() << ']';
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void RegSortData::dump() const { void RegSortData::dump() const {
print(errs()); errs() << '\n'; print(errs()); errs() << '\n';
} }
#endif #endif
namespace { namespace {
/// RegUseTracker - Map register candidates to information about how they are /// RegUseTracker - Map register candidates to information about how they are
▲ Show 20 Lines • Show All 342 Lines • ▼ Show 20 Lines if (Scale != 0) {
OS << ')'; OS << ')';
} }
if (UnfoldedOffset != 0) { if (UnfoldedOffset != 0) {
if (!First) OS << " + "; if (!First) OS << " + ";
OS << "imm(" << UnfoldedOffset << ')'; OS << "imm(" << UnfoldedOffset << ')';
} }
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void Formula::dump() const { void Formula::dump() const {
print(errs()); errs() << '\n'; print(errs()); errs() << '\n';
} }
#endif #endif
/// isAddRecSExtable - Return true if the given addrec can be sign-extended /// isAddRecSExtable - Return true if the given addrec can be sign-extended
/// without changing its value. /// without changing its value.
static bool isAddRecSExtable(const SCEVAddRecExpr *AR, ScalarEvolution &SE) { static bool isAddRecSExtable(const SCEVAddRecExpr *AR, ScalarEvolution &SE) {
▲ Show 20 Lines • Show All 365 Lines • ▼ Show 20 Linespublic:
Cost() Cost()
: NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0), : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0),
SetupCost(0), ScaleCost(0) {} SetupCost(0), ScaleCost(0) {}
bool operator<(const Cost &Other) const; bool operator<(const Cost &Other) const;
void Lose(); void Lose();
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Once any of the metrics loses, they must all remain losers. // Once any of the metrics loses, they must all remain losers.
bool isValid() { bool isValid() {
return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds
| ImmCost | SetupCost | ScaleCost) != ~0u) | ImmCost | SetupCost | ScaleCost) != ~0u)
|| ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds
& ImmCost & SetupCost & ScaleCost) == ~0u); & ImmCost & SetupCost & ScaleCost) == ~0u);
} }
#endif #endif
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Linesvoid Cost::print(raw_ostream &OS) const {
if (ScaleCost != 0) if (ScaleCost != 0)
OS << ", plus " << ScaleCost << " scale cost"; OS << ", plus " << ScaleCost << " scale cost";
if (ImmCost != 0) if (ImmCost != 0)
OS << ", plus " << ImmCost << " imm cost"; OS << ", plus " << ImmCost << " imm cost";
if (SetupCost != 0) if (SetupCost != 0)
OS << ", plus " << SetupCost << " setup cost"; OS << ", plus " << SetupCost << " setup cost";
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void Cost::dump() const { void Cost::dump() const {
print(errs()); errs() << '\n'; print(errs()); errs() << '\n';
} }
#endif #endif
namespace { namespace {
/// LSRFixup - An operand value in an instruction which is to be replaced /// LSRFixup - An operand value in an instruction which is to be replaced
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesvoid LSRFixup::print(raw_ostream &OS) const {
if (LUIdx != ~size_t(0)) if (LUIdx != ~size_t(0))
OS << ", LUIdx=" << LUIdx; OS << ", LUIdx=" << LUIdx;
if (Offset != 0) if (Offset != 0)
OS << ", Offset=" << Offset; OS << ", Offset=" << Offset;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void LSRFixup::dump() const { void LSRFixup::dump() const {
print(errs()); errs() << '\n'; print(errs()); errs() << '\n';
} }
#endif #endif
namespace { namespace {
/// UniquifierDenseMapInfo - A DenseMapInfo implementation for holding /// UniquifierDenseMapInfo - A DenseMapInfo implementation for holding
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Linesbool LSRUse::InsertFormula(const Formula &F) {
std::sort(Key.begin(), Key.end()); std::sort(Key.begin(), Key.end());
if (!Uniquifier.insert(Key).second) if (!Uniquifier.insert(Key).second)
return false; return false;
// Using a register to hold the value of 0 is not profitable. // Using a register to hold the value of 0 is not profitable.
assert((!F.ScaledReg || !F.ScaledReg->isZero()) && assert((!F.ScaledReg || !F.ScaledReg->isZero()) &&
"Zero allocated in a scaled register!"); "Zero allocated in a scaled register!");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (const SCEV *BaseReg : F.BaseRegs) for (const SCEV *BaseReg : F.BaseRegs)
assert(!BaseReg->isZero() && "Zero allocated in a base register!"); assert(!BaseReg->isZero() && "Zero allocated in a base register!");
#endif #endif
// Add the formula to the list. // Add the formula to the list.
Formulae.push_back(F); Formulae.push_back(F);
// Record registers now being used by this use. // Record registers now being used by this use.
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesvoid LSRUse::print(raw_ostream &OS) const {
if (AllFixupsOutsideLoop) if (AllFixupsOutsideLoop)
OS << ", all-fixups-outside-loop"; OS << ", all-fixups-outside-loop";
if (WidestFixupType) if (WidestFixupType)
OS << ", widest fixup type: " << *WidestFixupType; OS << ", widest fixup type: " << *WidestFixupType;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void LSRUse::dump() const { void LSRUse::dump() const {
print(errs()); errs() << '\n'; print(errs()); errs() << '\n';
} }
#endif #endif
static bool isAMCompletelyFolded(const TargetTransformInfo &TTI, static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
LSRUse::KindType Kind, Type *AccessTy, LSRUse::KindType Kind, Type *AccessTy,
GlobalValue *BaseGV, int64_t BaseOffset, GlobalValue *BaseGV, int64_t BaseOffset,
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} }
void WorkItem::print(raw_ostream &OS) const { void WorkItem::print(raw_ostream &OS) const {
OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx
<< " , add offset " << Imm; << " , add offset " << Imm;
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void WorkItem::dump() const { void WorkItem::dump() const {
print(errs()); errs() << '\n'; print(errs()); errs() << '\n';
} }
#endif #endif
/// GenerateCrossUseConstantOffsets - Look for registers which are a constant /// GenerateCrossUseConstantOffsets - Look for registers which are a constant
/// distance apart and try to form reuse opportunities between them. /// distance apart and try to form reuse opportunities between them.
void LSRInstance::GenerateCrossUseConstantOffsets() { void LSRInstance::GenerateCrossUseConstantOffsets() {
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} }
/// If there are multiple formulae with the same set of registers used /// If there are multiple formulae with the same set of registers used
/// by other uses, pick the best one and delete the others. /// by other uses, pick the best one and delete the others.
void LSRInstance::FilterOutUndesirableDedicatedRegisters() { void LSRInstance::FilterOutUndesirableDedicatedRegisters() {
DenseSet<const SCEV *> VisitedRegs; DenseSet<const SCEV *> VisitedRegs;
SmallPtrSet<const SCEV *, 16> Regs; SmallPtrSet<const SCEV *, 16> Regs;
SmallPtrSet<const SCEV *, 16> LoserRegs; SmallPtrSet<const SCEV *, 16> LoserRegs;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
bool ChangedFormulae = false; bool ChangedFormulae = false;
#endif #endif
// Collect the best formula for each unique set of shared registers. This // Collect the best formula for each unique set of shared registers. This
// is reset for each use. // is reset for each use.
typedef DenseMap<SmallVector<const SCEV *, 4>, size_t, UniquifierDenseMapInfo> typedef DenseMap<SmallVector<const SCEV *, 4>, size_t, UniquifierDenseMapInfo>
BestFormulaeTy; BestFormulaeTy;
BestFormulaeTy BestFormulae; BestFormulaeTy BestFormulae;
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines for (size_t FIdx = 0, NumForms = LU.Formulae.size();
DT, LU); DT, LU);
if (CostF < CostBest) if (CostF < CostBest)
std::swap(F, Best); std::swap(F, Best);
DEBUG(dbgs() << " Filtering out formula "; F.print(dbgs()); DEBUG(dbgs() << " Filtering out formula "; F.print(dbgs());
dbgs() << "\n" dbgs() << "\n"
" in favor of formula "; Best.print(dbgs()); " in favor of formula "; Best.print(dbgs());
dbgs() << '\n'); dbgs() << '\n');
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
ChangedFormulae = true; ChangedFormulae = true;
#endif #endif
LU.DeleteFormula(F); LU.DeleteFormula(F);
--FIdx; --FIdx;
--NumForms; --NumForms;
Any = true; Any = true;
} }
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LSRInstance::ImplementSolution(const SmallVectorImpl<const Formula *> &Solution, LSRInstance::ImplementSolution(const SmallVectorImpl<const Formula *> &Solution,
Pass *P) { Pass *P) {
// Keep track of instructions we may have made dead, so that // Keep track of instructions we may have made dead, so that
// we can remove them after we are done working. // we can remove them after we are done working.
SmallVector<WeakVH, 16> DeadInsts; SmallVector<WeakVH, 16> DeadInsts;
SCEVExpander Rewriter(SE, L->getHeader()->getModule()->getDataLayout(), SCEVExpander Rewriter(SE, L->getHeader()->getModule()->getDataLayout(),
"lsr"); "lsr");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Rewriter.setDebugType(DEBUG_TYPE); Rewriter.setDebugType(DEBUG_TYPE);
#endif #endif
Rewriter.disableCanonicalMode(); Rewriter.disableCanonicalMode();
Rewriter.enableLSRMode(); Rewriter.enableLSRMode();
Rewriter.setIVIncInsertPos(L, IVIncInsertPos); Rewriter.setIVIncInsertPos(L, IVIncInsertPos);
// Mark phi nodes that terminate chains so the expander tries to reuse them. // Mark phi nodes that terminate chains so the expander tries to reuse them.
for (const IVChain &Chain : IVChainVec) { for (const IVChain &Chain : IVChainVec) {
Show All 39 LinesLSRInstance::LSRInstance(Loop *L, Pass *P)
for (const IVStrideUse &U : IU) { for (const IVStrideUse &U : IU) {
if (++NumUsers > MaxIVUsers) { if (++NumUsers > MaxIVUsers) {
(void)U; (void)U;
DEBUG(dbgs() << "LSR skipping loop, too many IV Users in " << U << "\n"); DEBUG(dbgs() << "LSR skipping loop, too many IV Users in " << U << "\n");
return; return;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// All dominating loops must have preheaders, or SCEVExpander may not be able // All dominating loops must have preheaders, or SCEVExpander may not be able
// to materialize an AddRecExpr whose Start is an outer AddRecExpr. // to materialize an AddRecExpr whose Start is an outer AddRecExpr.
// //
// IVUsers analysis should only create users that are dominated by simple loop // IVUsers analysis should only create users that are dominated by simple loop
// headers. Since this loop should dominate all of its users, its user list // headers. Since this loop should dominate all of its users, its user list
// should be empty if this loop itself is not within a simple loop nest. // should be empty if this loop itself is not within a simple loop nest.
for (DomTreeNode *Rung = DT.getNode(L->getLoopPreheader()); for (DomTreeNode *Rung = DT.getNode(L->getLoopPreheader());
Rung; Rung = Rung->getIDom()) { Rung; Rung = Rung->getIDom()) {
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines#endif // DEBUG
// Release memory that is no longer needed. // Release memory that is no longer needed.
Factors.clear(); Factors.clear();
Types.clear(); Types.clear();
RegUses.clear(); RegUses.clear();
if (Solution.empty()) if (Solution.empty())
return; return;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Formulae should be legal. // Formulae should be legal.
for (const LSRUse &LU : Uses) { for (const LSRUse &LU : Uses) {
for (const Formula &F : LU.Formulae) for (const Formula &F : LU.Formulae)
assert(isLegalUse(TTI, LU.MinOffset, LU.MaxOffset, LU.Kind, LU.AccessTy, assert(isLegalUse(TTI, LU.MinOffset, LU.MaxOffset, LU.Kind, LU.AccessTy,
F) && "Illegal formula generated!"); F) && "Illegal formula generated!");
}; };
#endif #endif
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} }
void LSRInstance::print(raw_ostream &OS) const { void LSRInstance::print(raw_ostream &OS) const {
print_factors_and_types(OS); print_factors_and_types(OS);
print_fixups(OS); print_fixups(OS);
print_uses(OS); print_uses(OS);
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void LSRInstance::dump() const { void LSRInstance::dump() const {
print(errs()); errs() << '\n'; print(errs()); errs() << '\n';
} }
#endif #endif
namespace { namespace {
class LoopStrengthReduce : public LoopPass { class LoopStrengthReduce : public LoopPass {
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesbool LoopStrengthReduce::runOnLoop(Loop *L, LPPassManager & /*LPM*/) {
Changed |= LSRInstance(L, this).getChanged(); Changed |= LSRInstance(L, this).getChanged();
// Remove any extra phis created by processing inner loops. // Remove any extra phis created by processing inner loops.
Changed |= DeleteDeadPHIs(L->getHeader()); Changed |= DeleteDeadPHIs(L->getHeader());
if (EnablePhiElim && L->isLoopSimplifyForm()) { if (EnablePhiElim && L->isLoopSimplifyForm()) {
SmallVector<WeakVH, 16> DeadInsts; SmallVector<WeakVH, 16> DeadInsts;
const DataLayout &DL = L->getHeader()->getModule()->getDataLayout(); const DataLayout &DL = L->getHeader()->getModule()->getDataLayout();
SCEVExpander Rewriter(getAnalysis<ScalarEvolution>(), DL, "lsr"); SCEVExpander Rewriter(getAnalysis<ScalarEvolution>(), DL, "lsr");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Rewriter.setDebugType(DEBUG_TYPE); Rewriter.setDebugType(DEBUG_TYPE);
#endif #endif
unsigned numFolded = Rewriter.replaceCongruentIVs( unsigned numFolded = Rewriter.replaceCongruentIVs(
L, &getAnalysis<DominatorTreeWrapperPass>().getDomTree(), DeadInsts, L, &getAnalysis<DominatorTreeWrapperPass>().getDomTree(), DeadInsts,
&getAnalysis<TargetTransformInfoWrapperPass>().getTTI( &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(
*L->getHeader()->getParent())); *L->getHeader()->getParent()));
if (numFolded) { if (numFolded) {
Changed = true; Changed = true;
DeleteTriviallyDeadInstructions(DeadInsts); DeleteTriviallyDeadInstructions(DeadInsts);
DeleteDeadPHIs(L->getHeader()); DeleteDeadPHIs(L->getHeader());
} }
} }
return Changed; return Changed;
} }

lib/Transforms/Scalar/Reassociate.cpp

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines struct ValueEntry {
Value *Op; Value *Op;
ValueEntry(unsigned R, Value *O) : Rank(R), Op(O) {} ValueEntry(unsigned R, Value *O) : Rank(R), Op(O) {}
}; };
inline bool operator<(const ValueEntry &LHS, const ValueEntry &RHS) { inline bool operator<(const ValueEntry &LHS, const ValueEntry &RHS) {
return LHS.Rank > RHS.Rank; // Sort so that highest rank goes to start. return LHS.Rank > RHS.Rank; // Sort so that highest rank goes to start.
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// Print out the expression identified in the Ops list. /// Print out the expression identified in the Ops list.
/// ///
static void PrintOps(Instruction *I, const SmallVectorImpl<ValueEntry> &Ops) { static void PrintOps(Instruction *I, const SmallVectorImpl<ValueEntry> &Ops) {
Module *M = I->getParent()->getParent()->getParent(); Module *M = I->getParent()->getParent()->getParent();
dbgs() << Instruction::getOpcodeName(I->getOpcode()) << " " dbgs() << Instruction::getOpcodeName(I->getOpcode()) << " "
<< *Ops[0].Op->getType() << '\t'; << *Ops[0].Op->getType() << '\t';
for (unsigned i = 0, e = Ops.size(); i != e; ++i) { for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
dbgs() << "[ "; dbgs() << "[ ";
▲ Show 20 Lines • Show All 508 Lines • ▼ Show 20 Linesstatic bool LinearizeExprTree(BinaryOperator *I,
// are explored. // are explored.
// Leaves - Keeps track of the set of putative leaves as well as the number of // Leaves - Keeps track of the set of putative leaves as well as the number of
// paths to each leaf seen so far. // paths to each leaf seen so far.
typedef DenseMap<Value*, APInt> LeafMap; typedef DenseMap<Value*, APInt> LeafMap;
LeafMap Leaves; // Leaf -> Total weight so far. LeafMap Leaves; // Leaf -> Total weight so far.
SmallVector<Value*, 8> LeafOrder; // Ensure deterministic leaf output order. SmallVector<Value*, 8> LeafOrder; // Ensure deterministic leaf output order.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
SmallPtrSet<Value*, 8> Visited; // For sanity checking the iteration scheme. SmallPtrSet<Value*, 8> Visited; // For sanity checking the iteration scheme.
#endif #endif
while (!Worklist.empty()) { while (!Worklist.empty()) {
std::pair<BinaryOperator*, APInt> P = Worklist.pop_back_val(); std::pair<BinaryOperator*, APInt> P = Worklist.pop_back_val();
I = P.first; // We examine the operands of this binary operator. I = P.first; // We examine the operands of this binary operator.
for (unsigned OpIdx = 0; OpIdx < 2; ++OpIdx) { // Visit operands. for (unsigned OpIdx = 0; OpIdx < 2; ++OpIdx) { // Visit operands.
Value *Op = I->getOperand(OpIdx); Value *Op = I->getOperand(OpIdx);
▲ Show 20 Lines • Show All 1,661 Lines • Show Last 20 Lines

lib/Transforms/Scalar/RewriteStatepointsForGC.cpp

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Linesstatic bool isHandledGCPointerType(Type *T) {
// We partially support vectors of gc pointers. The code will assert if it // We partially support vectors of gc pointers. The code will assert if it
// can't handle something. // can't handle something.
if (auto VT = dyn_cast<VectorType>(T)) if (auto VT = dyn_cast<VectorType>(T))
if (isGCPointerType(VT->getElementType())) if (isGCPointerType(VT->getElementType()))
return true; return true;
return false; return false;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// Returns true if this type contains a gc pointer whether we know how to /// Returns true if this type contains a gc pointer whether we know how to
/// handle that type or not. /// handle that type or not.
static bool containsGCPtrType(Type *Ty) { static bool containsGCPtrType(Type *Ty) {
if (isGCPointerType(Ty)) if (isGCPointerType(Ty))
return true; return true;
if (VectorType *VT = dyn_cast<VectorType>(Ty)) if (VectorType *VT = dyn_cast<VectorType>(Ty))
return isGCPointerType(VT->getScalarType()); return isGCPointerType(VT->getScalarType());
if (ArrayType *AT = dyn_cast<ArrayType>(Ty)) if (ArrayType *AT = dyn_cast<ArrayType>(Ty))
▲ Show 20 Lines • Show All 481 Lines • ▼ Show 20 Linesstatic Value *findBasePointer(Value *I, DefiningValueMapTy &cache) {
// - For every conflict, add arguments for the base[a] of each input // - For every conflict, add arguments for the base[a] of each input
// arguments. // arguments.
// //
// Note: A simpler form of this would be to add the conflict form of all // Note: A simpler form of this would be to add the conflict form of all
// PHIs without running the optimistic algorithm. This would be // PHIs without running the optimistic algorithm. This would be
// analougous to pessimistic data flow and would likely lead to an // analougous to pessimistic data flow and would likely lead to an
// overall worse solution. // overall worse solution.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
auto isExpectedBDVType = [](Value *BDV) { auto isExpectedBDVType = [](Value *BDV) {
return isa<PHINode>(BDV) || isa<SelectInst>(BDV); return isa<PHINode>(BDV) || isa<SelectInst>(BDV);
}; };
#endif #endif
// Once populated, will contain a mapping from each potentially non-base BDV // Once populated, will contain a mapping from each potentially non-base BDV
// to a lattice value (described above) which corresponds to that BDV. // to a lattice value (described above) which corresponds to that BDV.
ConflictStateMapTy states; ConflictStateMapTy states;
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines if (isKnownBaseResult(baseValue))
return BDVState(baseValue); return BDVState(baseValue);
auto I = states.find(baseValue); auto I = states.find(baseValue);
assert(I != states.end() && "lookup failed!"); assert(I != states.end() && "lookup failed!");
return I->second; return I->second;
}; };
bool progress = true; bool progress = true;
while (progress) { while (progress) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
size_t oldSize = states.size(); size_t oldSize = states.size();
#endif #endif
progress = false; progress = false;
// We're only changing keys in this loop, thus safe to keep iterators // We're only changing keys in this loop, thus safe to keep iterators
for (auto Pair : states) { for (auto Pair : states) {
Value *v = Pair.first; Value *v = Pair.first;
assert(!isKnownBaseResult(v) && "why did it get added?"); assert(!isKnownBaseResult(v) && "why did it get added?");
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines if (PHINode *basephi = dyn_cast<PHINode>(state.getBase())) {
// has a different type than base, we'll end up adding two // has a different type than base, we'll end up adding two
// bitcasts (and hence two distinct values) as incoming // bitcasts (and hence two distinct values) as incoming
// values for the same basic block. // values for the same basic block.
int blockIndex = basephi->getBasicBlockIndex(InBB); int blockIndex = basephi->getBasicBlockIndex(InBB);
if (blockIndex != -1) { if (blockIndex != -1) {
Value *oldBase = basephi->getIncomingValue(blockIndex); Value *oldBase = basephi->getIncomingValue(blockIndex);
basephi->addIncoming(oldBase, InBB); basephi->addIncoming(oldBase, InBB);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Value *base = findBaseOrBDV(InVal, cache); Value *base = findBaseOrBDV(InVal, cache);
if (!isKnownBaseResult(base)) { if (!isKnownBaseResult(base)) {
// Either conflict or base. // Either conflict or base.
assert(states.count(base)); assert(states.count(base));
base = states[base].getBase(); base = states[base].getBase();
assert(base != nullptr && "unknown BDVState!"); assert(base != nullptr && "unknown BDVState!");
} }
▲ Show 20 Lines • Show All 416 Lines • ▼ Show 20 Lines if (CS.isCall()) {
// statepoint // statepoint
} }
assert(token); assert(token);
// Take the name of the original value call if it had one. // Take the name of the original value call if it had one.
token->takeName(CS.getInstruction()); token->takeName(CS.getInstruction());
// The GCResult is already inserted, we just need to find it // The GCResult is already inserted, we just need to find it
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Instruction *toReplace = CS.getInstruction(); Instruction *toReplace = CS.getInstruction();
assert((toReplace->hasNUses(0) || toReplace->hasNUses(1)) && assert((toReplace->hasNUses(0) || toReplace->hasNUses(1)) &&
"only valid use before rewrite is gc.result"); "only valid use before rewrite is gc.result");
assert(!toReplace->hasOneUse() || assert(!toReplace->hasOneUse() ||
isGCResult(cast<Instruction>(*toReplace->user_begin()))); isGCResult(cast<Instruction>(*toReplace->user_begin())));
#endif #endif
// Update the gc.result of the original statepoint (if any) to use the newly // Update the gc.result of the original statepoint (if any) to use the newly
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines for (User *U : GCRelocs) {
IRBuilder<> Builder(RelocatedValue->getNextNode()); IRBuilder<> Builder(RelocatedValue->getNextNode());
Value *CastedRelocatedValue = Value *CastedRelocatedValue =
Builder.CreateBitCast(RelocatedValue, cast<AllocaInst>(Alloca)->getAllocatedType(), Builder.CreateBitCast(RelocatedValue, cast<AllocaInst>(Alloca)->getAllocatedType(),
RelocatedValue->hasName() ? RelocatedValue->getName() + ".casted" : ""); RelocatedValue->hasName() ? RelocatedValue->getName() + ".casted" : "");
StoreInst *Store = new StoreInst(CastedRelocatedValue, Alloca); StoreInst *Store = new StoreInst(CastedRelocatedValue, Alloca);
Store->insertAfter(cast<Instruction>(CastedRelocatedValue)); Store->insertAfter(cast<Instruction>(CastedRelocatedValue));
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VisitedLiveValues.insert(OriginalValue); VisitedLiveValues.insert(OriginalValue);
#endif #endif
} }
} }
// Helper function for the "relocationViaAlloca". Similar to the // Helper function for the "relocationViaAlloca". Similar to the
// "insertRelocationStores" but works for rematerialized values. // "insertRelocationStores" but works for rematerialized values.
static void static void
insertRematerializationStores( insertRematerializationStores(
RematerializedValueMapTy RematerializedValues, RematerializedValueMapTy RematerializedValues,
DenseMap<Value *, Value *> &AllocaMap, DenseMap<Value *, Value *> &AllocaMap,
DenseSet<Value *> &VisitedLiveValues) { DenseSet<Value *> &VisitedLiveValues) {
for (auto RematerializedValuePair: RematerializedValues) { for (auto RematerializedValuePair: RematerializedValues) {
Instruction *RematerializedValue = RematerializedValuePair.first; Instruction *RematerializedValue = RematerializedValuePair.first;
Value *OriginalValue = RematerializedValuePair.second; Value *OriginalValue = RematerializedValuePair.second;
assert(AllocaMap.count(OriginalValue) && assert(AllocaMap.count(OriginalValue) &&
"Can not find alloca for rematerialized value"); "Can not find alloca for rematerialized value");
Value *Alloca = AllocaMap[OriginalValue]; Value *Alloca = AllocaMap[OriginalValue];
StoreInst *Store = new StoreInst(RematerializedValue, Alloca); StoreInst *Store = new StoreInst(RematerializedValue, Alloca);
Store->insertAfter(RematerializedValue); Store->insertAfter(RematerializedValue);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
VisitedLiveValues.insert(OriginalValue); VisitedLiveValues.insert(OriginalValue);
#endif #endif
} }
} }
/// do all the relocation update via allocas and mem2reg /// do all the relocation update via allocas and mem2reg
static void relocationViaAlloca( static void relocationViaAlloca(
Function &F, DominatorTree &DT, ArrayRef<Value *> Live, Function &F, DominatorTree &DT, ArrayRef<Value *> Live,
ArrayRef<struct PartiallyConstructedSafepointRecord> Records) { ArrayRef<struct PartiallyConstructedSafepointRecord> Records) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// record initial number of (static) allocas; we'll check we have the same // record initial number of (static) allocas; we'll check we have the same
// number when we get done. // number when we get done.
int InitialAllocaNum = 0; int InitialAllocaNum = 0;
for (auto I = F.getEntryBlock().begin(), E = F.getEntryBlock().end(); I != E; for (auto I = F.getEntryBlock().begin(), E = F.getEntryBlock().end(); I != E;
I++) I++)
if (isa<AllocaInst>(*I)) if (isa<AllocaInst>(*I))
InitialAllocaNum++; InitialAllocaNum++;
#endif #endif
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines#endif
assert(PromotableAllocas.size() == Live.size() + NumRematerializedValues && assert(PromotableAllocas.size() == Live.size() + NumRematerializedValues &&
"we must have the same allocas with lives"); "we must have the same allocas with lives");
if (!PromotableAllocas.empty()) { if (!PromotableAllocas.empty()) {
// apply mem2reg to promote alloca to SSA // apply mem2reg to promote alloca to SSA
PromoteMemToReg(PromotableAllocas, DT); PromoteMemToReg(PromotableAllocas, DT);
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (auto I = F.getEntryBlock().begin(), E = F.getEntryBlock().end(); I != E; for (auto I = F.getEntryBlock().begin(), E = F.getEntryBlock().end(); I != E;
I++) I++)
if (isa<AllocaInst>(*I)) if (isa<AllocaInst>(*I))
InitialAllocaNum--; InitialAllocaNum--;
assert(InitialAllocaNum == 0 && "We must not introduce any extra allocas"); assert(InitialAllocaNum == 0 && "We must not introduce any extra allocas");
#endif #endif
} }
▲ Show 20 Lines • Show All 321 Lines • ▼ Show 20 Lines auto rematerializeChain = [&ChainToBase](Instruction *InsertBefore) {
ClonedValue->insertBefore(InsertBefore); ClonedValue->insertBefore(InsertBefore);
ClonedValue->setName(Instr->getName() + ".remat"); ClonedValue->setName(Instr->getName() + ".remat");
// If it is not first instruction in the chain then it uses previously // If it is not first instruction in the chain then it uses previously
// cloned value. We should update it to use cloned value. // cloned value. We should update it to use cloned value.
if (LastClonedValue) { if (LastClonedValue) {
assert(LastValue); assert(LastValue);
ClonedValue->replaceUsesOfWith(LastValue, LastClonedValue); ClonedValue->replaceUsesOfWith(LastValue, LastClonedValue);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Assert that cloned instruction does not use any instructions from // Assert that cloned instruction does not use any instructions from
// this chain other than LastClonedValue // this chain other than LastClonedValue
for (auto OpValue : ClonedValue->operand_values()) { for (auto OpValue : ClonedValue->operand_values()) {
assert(std::find(ChainToBase.begin(), ChainToBase.end(), OpValue) == assert(std::find(ChainToBase.begin(), ChainToBase.end(), OpValue) ==
ChainToBase.end() && ChainToBase.end() &&
"incorrect use in rematerialization chain"); "incorrect use in rematerialization chain");
} }
#endif #endif
Show All 34 Lines#endif
// Remove rematerializaed values from the live set // Remove rematerializaed values from the live set
for (auto LiveValue: LiveValuesToBeDeleted) { for (auto LiveValue: LiveValuesToBeDeleted) {
Info.liveset.erase(LiveValue); Info.liveset.erase(LiveValue);
} }
} }
static bool insertParsePoints(Function &F, DominatorTree &DT, Pass *P, static bool insertParsePoints(Function &F, DominatorTree &DT, Pass *P,
SmallVectorImpl<CallSite> &toUpdate) { SmallVectorImpl<CallSite> &toUpdate) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// sanity check the input // sanity check the input
std::set<CallSite> uniqued; std::set<CallSite> uniqued;
uniqued.insert(toUpdate.begin(), toUpdate.end()); uniqued.insert(toUpdate.begin(), toUpdate.end());
assert(uniqued.size() == toUpdate.size() && "no duplicates please!"); assert(uniqued.size() == toUpdate.size() && "no duplicates please!");
for (size_t i = 0; i < toUpdate.size(); i++) { for (size_t i = 0; i < toUpdate.size(); i++) {
CallSite &CS = toUpdate[i]; CallSite &CS = toUpdate[i];
assert(CS.getInstruction()->getParent()->getParent() == &F); assert(CS.getInstruction()->getParent()->getParent() == &F);
▲ Show 20 Lines • Show All 155 Lines • ▼ Show 20 Lines for (size_t i = 0; i < records.size(); i++) {
// We can't simply save the live set from the original insertion. One of // We can't simply save the live set from the original insertion. One of
// the live values might be the result of a call which needs a safepoint. // the live values might be the result of a call which needs a safepoint.
// That Value* no longer exists and we need to use the new gc_result. // That Value* no longer exists and we need to use the new gc_result.
// Thankfully, the liveset is embedded in the statepoint (and updated), so // Thankfully, the liveset is embedded in the statepoint (and updated), so
// we just grab that. // we just grab that.
Statepoint statepoint(info.StatepointToken); Statepoint statepoint(info.StatepointToken);
live.insert(live.end(), statepoint.gc_args_begin(), live.insert(live.end(), statepoint.gc_args_begin(),
statepoint.gc_args_end()); statepoint.gc_args_end());
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Do some basic sanity checks on our liveness results before performing // Do some basic sanity checks on our liveness results before performing
// relocation. Relocation can and will turn mistakes in liveness results // relocation. Relocation can and will turn mistakes in liveness results
// into non-sensical code which is must harder to debug. // into non-sensical code which is must harder to debug.
// TODO: It would be nice to test consistency as well // TODO: It would be nice to test consistency as well
assert(DT.isReachableFromEntry(info.StatepointToken->getParent()) && assert(DT.isReachableFromEntry(info.StatepointToken->getParent()) &&
"statepoint must be reachable or liveness is meaningless"); "statepoint must be reachable or liveness is meaningless");
for (Value *V : statepoint.gc_args()) { for (Value *V : statepoint.gc_args()) {
if (!isa<Instruction>(V)) if (!isa<Instruction>(V))
// Non-instruction values trivial dominate all possible uses // Non-instruction values trivial dominate all possible uses
continue; continue;
auto LiveInst = cast<Instruction>(V); auto LiveInst = cast<Instruction>(V);
assert(DT.isReachableFromEntry(LiveInst->getParent()) && assert(DT.isReachableFromEntry(LiveInst->getParent()) &&
"unreachable values should never be live"); "unreachable values should never be live");
assert(DT.dominates(LiveInst, info.StatepointToken) && assert(DT.dominates(LiveInst, info.StatepointToken) &&
"basic SSA liveness expectation violated by liveness analysis"); "basic SSA liveness expectation violated by liveness analysis");
} }
#endif #endif
} }
unique_unsorted(live); unique_unsorted(live);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// sanity check // sanity check
for (auto ptr : live) { for (auto ptr : live) {
assert(isGCPointerType(ptr->getType()) && "must be a gc pointer type"); assert(isGCPointerType(ptr->getType()) && "must be a gc pointer type");
} }
#endif #endif
relocationViaAlloca(F, DT, live, records); relocationViaAlloca(F, DT, live, records);
return !records.empty(); return !records.empty();
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines if (F.hasGC()) {
const StringRef CoreCLRName("coreclr"); const StringRef CoreCLRName("coreclr");
return (StatepointExampleName == FunctionGCName) || return (StatepointExampleName == FunctionGCName) ||
(CoreCLRName == FunctionGCName); (CoreCLRName == FunctionGCName);
} else } else
return false; return false;
} }
void RewriteStatepointsForGC::stripDereferenceabilityInfo(Module &M) { void RewriteStatepointsForGC::stripDereferenceabilityInfo(Module &M) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
assert(std::any_of(M.begin(), M.end(), shouldRewriteStatepointsIn) && assert(std::any_of(M.begin(), M.end(), shouldRewriteStatepointsIn) &&
"precondition!"); "precondition!");
#endif #endif
for (Function &F : M) for (Function &F : M)
stripDereferenceabilityInfoFromPrototype(F); stripDereferenceabilityInfoFromPrototype(F);
for (Function &F : M) for (Function &F : M)
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
static DenseSet<Value *> computeKillSet(BasicBlock *BB) { static DenseSet<Value *> computeKillSet(BasicBlock *BB) {
DenseSet<Value *> KillSet; DenseSet<Value *> KillSet;
for (Instruction &I : *BB) for (Instruction &I : *BB)
if (isHandledGCPointerType(I.getType())) if (isHandledGCPointerType(I.getType()))
KillSet.insert(&I); KillSet.insert(&I);
return KillSet; return KillSet;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// Check that the items in 'Live' dominate 'TI'. This is used as a basic /// Check that the items in 'Live' dominate 'TI'. This is used as a basic
/// sanity check for the liveness computation. /// sanity check for the liveness computation.
static void checkBasicSSA(DominatorTree &DT, DenseSet<Value *> &Live, static void checkBasicSSA(DominatorTree &DT, DenseSet<Value *> &Live,
TerminatorInst *TI, bool TermOkay = false) { TerminatorInst *TI, bool TermOkay = false) {
for (Value *V : Live) { for (Value *V : Live) {
if (auto *I = dyn_cast<Instruction>(V)) { if (auto *I = dyn_cast<Instruction>(V)) {
// The terminator can be a member of the LiveOut set. LLVM's definition // The terminator can be a member of the LiveOut set. LLVM's definition
// of instruction dominance states that V does not dominate itself. As // of instruction dominance states that V does not dominate itself. As
Show All 32 Linesstatic void computeLiveInValues(DominatorTree &DT, Function &F,
}; };
// Seed the liveness for each individual block // Seed the liveness for each individual block
for (BasicBlock &BB : F) { for (BasicBlock &BB : F) {
Data.KillSet[&BB] = computeKillSet(&BB); Data.KillSet[&BB] = computeKillSet(&BB);
Data.LiveSet[&BB].clear(); Data.LiveSet[&BB].clear();
computeLiveInValues(BB.rbegin(), BB.rend(), Data.LiveSet[&BB]); computeLiveInValues(BB.rbegin(), BB.rend(), Data.LiveSet[&BB]);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (Value *Kill : Data.KillSet[&BB]) for (Value *Kill : Data.KillSet[&BB])
assert(!Data.LiveSet[&BB].count(Kill) && "live set contains kill"); assert(!Data.LiveSet[&BB].count(Kill) && "live set contains kill");
#endif #endif
Data.LiveOut[&BB] = DenseSet<Value *>(); Data.LiveOut[&BB] = DenseSet<Value *>();
computeLiveOutSeed(&BB, Data.LiveOut[&BB]); computeLiveOutSeed(&BB, Data.LiveOut[&BB]);
Data.LiveIn[&BB] = Data.LiveSet[&BB]; Data.LiveIn[&BB] = Data.LiveSet[&BB];
set_union(Data.LiveIn[&BB], Data.LiveOut[&BB]); set_union(Data.LiveIn[&BB], Data.LiveOut[&BB]);
Show All 32 Lines while (!Worklist.empty()) {
const DenseSet<Value *> &OldLiveIn = Data.LiveIn[BB]; const DenseSet<Value *> &OldLiveIn = Data.LiveIn[BB];
// assert: OldLiveIn is a subset of LiveTmp // assert: OldLiveIn is a subset of LiveTmp
if (OldLiveIn.size() != LiveTmp.size()) { if (OldLiveIn.size() != LiveTmp.size()) {
Data.LiveIn[BB] = LiveTmp; Data.LiveIn[BB] = LiveTmp;
AddPredsToWorklist(BB); AddPredsToWorklist(BB);
} }
} // while( !worklist.empty() ) } // while( !worklist.empty() )
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// Sanity check our ouput against SSA properties. This helps catch any // Sanity check our ouput against SSA properties. This helps catch any
// missing kills during the above iteration. // missing kills during the above iteration.
for (BasicBlock &BB : F) { for (BasicBlock &BB : F) {
checkBasicSSA(DT, Data, BB); checkBasicSSA(DT, Data, BB);
} }
#endif #endif
} }
Show All 18 Lines
static void recomputeLiveInValues(GCPtrLivenessData &RevisedLivenessData, static void recomputeLiveInValues(GCPtrLivenessData &RevisedLivenessData,
const CallSite &CS, const CallSite &CS,
PartiallyConstructedSafepointRecord &Info) { PartiallyConstructedSafepointRecord &Info) {
Instruction *Inst = CS.getInstruction(); Instruction *Inst = CS.getInstruction();
StatepointLiveSetTy Updated; StatepointLiveSetTy Updated;
findLiveSetAtInst(Inst, RevisedLivenessData, Updated); findLiveSetAtInst(Inst, RevisedLivenessData, Updated);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DenseSet<Value *> Bases; DenseSet<Value *> Bases;
for (auto KVPair : Info.PointerToBase) { for (auto KVPair : Info.PointerToBase) {
Bases.insert(KVPair.second); Bases.insert(KVPair.second);
} }
#endif #endif
// We may have base pointers which are now live that weren't before. We need // We may have base pointers which are now live that weren't before. We need
// to update the PointerToBase structure to reflect this. // to update the PointerToBase structure to reflect this.
for (auto V : Updated) for (auto V : Updated)
if (!Info.PointerToBase.count(V)) { if (!Info.PointerToBase.count(V)) {
assert(Bases.count(V) && "can't find base for unexpected live value"); assert(Bases.count(V) && "can't find base for unexpected live value");
Info.PointerToBase[V] = V; Info.PointerToBase[V] = V;
continue; continue;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (auto V : Updated) { for (auto V : Updated) {
assert(Info.PointerToBase.count(V) && assert(Info.PointerToBase.count(V) &&
"must be able to find base for live value"); "must be able to find base for live value");
} }
#endif #endif
// Remove any stale base mappings - this can happen since our liveness is // Remove any stale base mappings - this can happen since our liveness is
// more precise then the one inherent in the base pointer analysis // more precise then the one inherent in the base pointer analysis
DenseSet<Value *> ToErase; DenseSet<Value *> ToErase;
for (auto KVPair : Info.PointerToBase) for (auto KVPair : Info.PointerToBase)
if (!Updated.count(KVPair.first)) if (!Updated.count(KVPair.first))
ToErase.insert(KVPair.first); ToErase.insert(KVPair.first);
for (auto V : ToErase) for (auto V : ToErase)
Info.PointerToBase.erase(V); Info.PointerToBase.erase(V);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (auto KVPair : Info.PointerToBase) for (auto KVPair : Info.PointerToBase)
assert(Updated.count(KVPair.first) && "record for non-live value"); assert(Updated.count(KVPair.first) && "record for non-live value");
#endif #endif
Info.liveset = Updated; Info.liveset = Updated;
} }

lib/Transforms/Scalar/SCCP.cpp

Show First 20 Lines • Show All 570 Lines • ▼ Show 20 Linesvoid SCCPSolver::getFeasibleSuccessors(TerminatorInst &TI,
// TODO: This could be improved if the operand is a [cast of a] BlockAddress. // TODO: This could be improved if the operand is a [cast of a] BlockAddress.
if (isa<IndirectBrInst>(&TI)) { if (isa<IndirectBrInst>(&TI)) {
// Just mark all destinations executable! // Just mark all destinations executable!
Succs.assign(TI.getNumSuccessors(), true); Succs.assign(TI.getNumSuccessors(), true);
return; return;
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Unknown terminator instruction: " << TI << '\n'; dbgs() << "Unknown terminator instruction: " << TI << '\n';
#endif #endif
llvm_unreachable("SCCP: Don't know how to handle this terminator!"); llvm_unreachable("SCCP: Don't know how to handle this terminator!");
} }
// isEdgeFeasible - Return true if the control flow edge from the 'From' basic // isEdgeFeasible - Return true if the control flow edge from the 'From' basic
// block to the 'To' basic block is currently feasible. // block to the 'To' basic block is currently feasible.
Show All 39 Lines if (SwitchInst *SI = dyn_cast<SwitchInst>(TI)) {
return SI->findCaseValue(CI).getCaseSuccessor() == To; return SI->findCaseValue(CI).getCaseSuccessor() == To;
} }
// Just mark all destinations executable! // Just mark all destinations executable!
// TODO: This could be improved if the operand is a [cast of a] BlockAddress. // TODO: This could be improved if the operand is a [cast of a] BlockAddress.
if (isa<IndirectBrInst>(TI)) if (isa<IndirectBrInst>(TI))
return true; return true;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
dbgs() << "Unknown terminator instruction: " << *TI << '\n'; dbgs() << "Unknown terminator instruction: " << *TI << '\n';
#endif #endif
llvm_unreachable(nullptr); llvm_unreachable(nullptr);
} }
// visit Implementations - Something changed in this instruction, either an // visit Implementations - Something changed in this instruction, either an
// operand made a transition, or the instruction is newly executable. Change // operand made a transition, or the instruction is newly executable. Change
// the value type of I to reflect these changes if appropriate. This method // the value type of I to reflect these changes if appropriate. This method
▲ Show 20 Lines • Show All 1,213 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = BlocksToErase.size(); i != e; ++i) {
// Ignore blockaddress users; BasicBlock's dtor will handle them. // Ignore blockaddress users; BasicBlock's dtor will handle them.
if (!I) continue; if (!I) continue;
bool Folded = ConstantFoldTerminator(I->getParent()); bool Folded = ConstantFoldTerminator(I->getParent());
if (!Folded) { if (!Folded) {
// The constant folder may not have been able to fold the terminator // The constant folder may not have been able to fold the terminator
// if this is a branch or switch on undef. Fold it manually as a // if this is a branch or switch on undef. Fold it manually as a
// branch to the first successor. // branch to the first successor.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
if (BranchInst *BI = dyn_cast<BranchInst>(I)) { if (BranchInst *BI = dyn_cast<BranchInst>(I)) {
assert(BI->isConditional() && isa<UndefValue>(BI->getCondition()) && assert(BI->isConditional() && isa<UndefValue>(BI->getCondition()) &&
"Branch should be foldable!"); "Branch should be foldable!");
} else if (SwitchInst *SI = dyn_cast<SwitchInst>(I)) { } else if (SwitchInst *SI = dyn_cast<SwitchInst>(I)) {
assert(isa<UndefValue>(SI->getCondition()) && "Switch should fold"); assert(isa<UndefValue>(SI->getCondition()) && "Switch should fold");
} else { } else {
llvm_unreachable("Didn't fold away reference to block!"); llvm_unreachable("Didn't fold away reference to block!");
} }
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

lib/Transforms/Scalar/SROA.cpp

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/Support/TimeValue.h" #include "llvm/Support/TimeValue.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/PromoteMemToReg.h" #include "llvm/Transforms/Utils/PromoteMemToReg.h"
#include "llvm/Transforms/Utils/SSAUpdater.h" #include "llvm/Transforms/Utils/SSAUpdater.h"
#if __cplusplus >= 201103L && !defined(NDEBUG) #if __cplusplus >= 201103L && !defined(LLVM_NDEBUG)
// We only use this for a debug check in C++11 // We only use this for a debug check in C++11
#include <random> #include <random>
#endif #endif
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "sroa" #define DEBUG_TYPE "sroa"
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
template <> template <>
class IRBuilderPrefixedInserter<false> class IRBuilderPrefixedInserter<false>
: public IRBuilderDefaultInserter<false> { : public IRBuilderDefaultInserter<false> {
public: public:
void SetNamePrefix(const Twine &P) {} void SetNamePrefix(const Twine &P) {}
}; };
/// \brief Provide a typedef for IRBuilder that drops names in release builds. /// \brief Provide a typedef for IRBuilder that drops names in release builds.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
typedef llvm::IRBuilder<true, ConstantFolder, IRBuilderPrefixedInserter<true>> typedef llvm::IRBuilder<true, ConstantFolder, IRBuilderPrefixedInserter<true>>
IRBuilderTy; IRBuilderTy;
#else #else
typedef llvm::IRBuilder<false, ConstantFolder, IRBuilderPrefixedInserter<false>> typedef llvm::IRBuilder<false, ConstantFolder, IRBuilderPrefixedInserter<false>>
IRBuilderTy; IRBuilderTy;
#endif #endif
} }
▲ Show 20 Lines • Show All 403 Lines • ▼ Show 20 Linespublic:
/// \brief Access the dead operands referring to this alloca. /// \brief Access the dead operands referring to this alloca.
/// ///
/// These are operands which have cannot actually be used to refer to the /// These are operands which have cannot actually be used to refer to the
/// alloca as they are outside its range and the user doesn't correct for /// alloca as they are outside its range and the user doesn't correct for
/// that. These mostly consist of PHI node inputs and the like which we just /// that. These mostly consist of PHI node inputs and the like which we just
/// need to replace with undef. /// need to replace with undef.
ArrayRef<Use *> getDeadOperands() const { return DeadOperands; } ArrayRef<Use *> getDeadOperands() const { return DeadOperands; }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void print(raw_ostream &OS, const_iterator I, StringRef Indent = " ") const; void print(raw_ostream &OS, const_iterator I, StringRef Indent = " ") const;
void printSlice(raw_ostream &OS, const_iterator I, void printSlice(raw_ostream &OS, const_iterator I,
StringRef Indent = " ") const; StringRef Indent = " ") const;
void printUse(raw_ostream &OS, const_iterator I, void printUse(raw_ostream &OS, const_iterator I,
StringRef Indent = " ") const; StringRef Indent = " ") const;
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
void dump(const_iterator I) const; void dump(const_iterator I) const;
void dump() const; void dump() const;
#endif #endif
private: private:
template <typename DerivedT, typename RetT = void> class BuilderBase; template <typename DerivedT, typename RetT = void> class BuilderBase;
class SliceBuilder; class SliceBuilder;
friend class AllocaSlices::SliceBuilder; friend class AllocaSlices::SliceBuilder;
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// \brief Handle to alloca instruction to simplify method interfaces. /// \brief Handle to alloca instruction to simplify method interfaces.
AllocaInst &AI; AllocaInst &AI;
#endif #endif
/// \brief The instruction responsible for this alloca not having a known set /// \brief The instruction responsible for this alloca not having a known set
/// of slices. /// of slices.
/// ///
/// When an instruction (potentially) escapes the pointer to the alloca, we /// When an instruction (potentially) escapes the pointer to the alloca, we
▲ Show 20 Lines • Show All 425 Lines • ▼ Show 20 Linesprivate:
void visitSelectInst(SelectInst &SI) { visitPHINodeOrSelectInst(SI); } void visitSelectInst(SelectInst &SI) { visitPHINodeOrSelectInst(SI); }
/// \brief Disable SROA entirely if there are unhandled users of the alloca. /// \brief Disable SROA entirely if there are unhandled users of the alloca.
void visitInstruction(Instruction &I) { PI.setAborted(&I); } void visitInstruction(Instruction &I) { PI.setAborted(&I); }
}; };
AllocaSlices::AllocaSlices(const DataLayout &DL, AllocaInst &AI) AllocaSlices::AllocaSlices(const DataLayout &DL, AllocaInst &AI)
: :
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
AI(AI), AI(AI),
#endif #endif
PointerEscapingInstr(nullptr) { PointerEscapingInstr(nullptr) {
SliceBuilder PB(DL, AI, *this); SliceBuilder PB(DL, AI, *this);
SliceBuilder::PtrInfo PtrI = PB.visitPtr(AI); SliceBuilder::PtrInfo PtrI = PB.visitPtr(AI);
if (PtrI.isEscaped() || PtrI.isAborted()) { if (PtrI.isEscaped() || PtrI.isAborted()) {
// FIXME: We should sink the escape vs. abort info into the caller nicely, // FIXME: We should sink the escape vs. abort info into the caller nicely,
// possibly by just storing the PtrInfo in the AllocaSlices. // possibly by just storing the PtrInfo in the AllocaSlices.
PointerEscapingInstr = PtrI.getEscapingInst() ? PtrI.getEscapingInst() PointerEscapingInstr = PtrI.getEscapingInst() ? PtrI.getEscapingInst()
: PtrI.getAbortingInst(); : PtrI.getAbortingInst();
assert(PointerEscapingInstr && "Did not track a bad instruction"); assert(PointerEscapingInstr && "Did not track a bad instruction");
return; return;
} }
Slices.erase(std::remove_if(Slices.begin(), Slices.end(), Slices.erase(std::remove_if(Slices.begin(), Slices.end(),
[](const Slice &S) { [](const Slice &S) {
return S.isDead(); return S.isDead();
}), }),
Slices.end()); Slices.end());
#if __cplusplus >= 201103L && !defined(NDEBUG) #if __cplusplus >= 201103L && !defined(LLVM_NDEBUG)
if (SROARandomShuffleSlices) { if (SROARandomShuffleSlices) {
std::mt19937 MT(static_cast<unsigned>(sys::TimeValue::now().msec())); std::mt19937 MT(static_cast<unsigned>(sys::TimeValue::now().msec()));
std::shuffle(Slices.begin(), Slices.end(), MT); std::shuffle(Slices.begin(), Slices.end(), MT);
} }
#endif #endif
// Sort the uses. This arranges for the offsets to be in ascending order, // Sort the uses. This arranges for the offsets to be in ascending order,
// and the sizes to be in descending order. // and the sizes to be in descending order.
std::sort(Slices.begin(), Slices.end()); std::sort(Slices.begin(), Slices.end());
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
void AllocaSlices::print(raw_ostream &OS, const_iterator I, void AllocaSlices::print(raw_ostream &OS, const_iterator I,
StringRef Indent) const { StringRef Indent) const {
printSlice(OS, I, Indent); printSlice(OS, I, Indent);
OS << "\n"; OS << "\n";
printUse(OS, I, Indent); printUse(OS, I, Indent);
} }
Show All 22 Lines for (const_iterator I = begin(), E = end(); I != E; ++I)
print(OS, I); print(OS, I);
} }
LLVM_DUMP_METHOD void AllocaSlices::dump(const_iterator I) const { LLVM_DUMP_METHOD void AllocaSlices::dump(const_iterator I) const {
print(dbgs(), I); print(dbgs(), I);
} }
LLVM_DUMP_METHOD void AllocaSlices::dump() const { print(dbgs()); } LLVM_DUMP_METHOD void AllocaSlices::dump() const { print(dbgs()); }
#endif // !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #endif // !defined(LLVM_NDEBUG) || defined(LLVM_ENABLE_DUMP)
namespace { namespace {
/// \brief Implementation of LoadAndStorePromoter for promoting allocas. /// \brief Implementation of LoadAndStorePromoter for promoting allocas.
/// ///
/// This subclass of LoadAndStorePromoter adds overrides to handle promoting /// This subclass of LoadAndStorePromoter adds overrides to handle promoting
/// the loads and stores of an alloca instruction, as well as updating its /// the loads and stores of an alloca instruction, as well as updating its
/// debug information. This is used when a domtree is unavailable and thus /// debug information. This is used when a domtree is unavailable and thus
/// mem2reg in its full form can't be used to handle promotion of allocas to /// mem2reg in its full form can't be used to handle promotion of allocas to
▲ Show 20 Lines • Show All 988 Lines • ▼ Show 20 Lines if (!HaveCommonEltTy) {
}; };
std::sort(CandidateTys.begin(), CandidateTys.end(), RankVectorTypes); std::sort(CandidateTys.begin(), CandidateTys.end(), RankVectorTypes);
CandidateTys.erase( CandidateTys.erase(
std::unique(CandidateTys.begin(), CandidateTys.end(), RankVectorTypes), std::unique(CandidateTys.begin(), CandidateTys.end(), RankVectorTypes),
CandidateTys.end()); CandidateTys.end());
} else { } else {
// The only way to have the same element type in every vector type is to // The only way to have the same element type in every vector type is to
// have the same vector type. Check that and remove all but one. // have the same vector type. Check that and remove all but one.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (VectorType *VTy : CandidateTys) { for (VectorType *VTy : CandidateTys) {
assert(VTy->getElementType() == CommonEltTy && assert(VTy->getElementType() == CommonEltTy &&
"Unaccounted for element type!"); "Unaccounted for element type!");
assert(VTy == CandidateTys[0] && assert(VTy == CandidateTys[0] &&
"Different vector types with the same element type!"); "Different vector types with the same element type!");
} }
#endif #endif
CandidateTys.resize(1); CandidateTys.resize(1);
▲ Show 20 Lines • Show All 415 Lines • ▼ Show 20 Linesprivate:
} }
Value *getNewAllocaSlicePtr(IRBuilderTy &IRB, Type *PointerTy) { Value *getNewAllocaSlicePtr(IRBuilderTy &IRB, Type *PointerTy) {
// Note that the offset computation can use BeginOffset or NewBeginOffset // Note that the offset computation can use BeginOffset or NewBeginOffset
// interchangeably for unsplit slices. // interchangeably for unsplit slices.
assert(IsSplit || BeginOffset == NewBeginOffset); assert(IsSplit || BeginOffset == NewBeginOffset);
uint64_t Offset = NewBeginOffset - NewAllocaBeginOffset; uint64_t Offset = NewBeginOffset - NewAllocaBeginOffset;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
StringRef OldName = OldPtr->getName(); StringRef OldName = OldPtr->getName();
// Skip through the last '.sroa.' component of the name. // Skip through the last '.sroa.' component of the name.
size_t LastSROAPrefix = OldName.rfind(".sroa."); size_t LastSROAPrefix = OldName.rfind(".sroa.");
if (LastSROAPrefix != StringRef::npos) { if (LastSROAPrefix != StringRef::npos) {
OldName = OldName.substr(LastSROAPrefix + strlen(".sroa.")); OldName = OldName.substr(LastSROAPrefix + strlen(".sroa."));
// Look for an SROA slice index. // Look for an SROA slice index.
size_t IndexEnd = OldName.find_first_not_of("0123456789"); size_t IndexEnd = OldName.find_first_not_of("0123456789");
if (IndexEnd != StringRef::npos && OldName[IndexEnd] == '.') { if (IndexEnd != StringRef::npos && OldName[IndexEnd] == '.') {
// Strip the index and look for the offset. // Strip the index and look for the offset.
OldName = OldName.substr(IndexEnd + 1); OldName = OldName.substr(IndexEnd + 1);
size_t OffsetEnd = OldName.find_first_not_of("0123456789"); size_t OffsetEnd = OldName.find_first_not_of("0123456789");
if (OffsetEnd != StringRef::npos && OldName[OffsetEnd] == '.') if (OffsetEnd != StringRef::npos && OldName[OffsetEnd] == '.')
// Strip the offset. // Strip the offset.
OldName = OldName.substr(OffsetEnd + 1); OldName = OldName.substr(OffsetEnd + 1);
} }
} }
// Strip any SROA suffixes as well. // Strip any SROA suffixes as well.
OldName = OldName.substr(0, OldName.find(".sroa_")); OldName = OldName.substr(0, OldName.find(".sroa_"));
#endif #endif
return getAdjustedPtr(IRB, DL, &NewAI, return getAdjustedPtr(IRB, DL, &NewAI,
APInt(DL.getPointerSizeInBits(), Offset), PointerTy, APInt(DL.getPointerSizeInBits(), Offset), PointerTy,
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Twine(OldName) + "." Twine(OldName) + "."
#else #else
Twine() Twine()
#endif #endif
); );
} }
/// \brief Compute suitable alignment to access this slice of the *new* /// \brief Compute suitable alignment to access this slice of the *new*
▲ Show 20 Lines • Show All 1,450 Lines • ▼ Show 20 Lines AS.erase(std::remove_if(AS.begin(), AS.end(), [](const Slice &S) {
return S.isDead(); return S.isDead();
}), AS.end()); }), AS.end());
// Insert our new slices. This will sort and merge them into the sorted // Insert our new slices. This will sort and merge them into the sorted
// sequence. // sequence.
AS.insert(NewSlices); AS.insert(NewSlices);
DEBUG(dbgs() << " Pre-split slices:\n"); DEBUG(dbgs() << " Pre-split slices:\n");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (auto I = AS.begin(), E = AS.end(); I != E; ++I) for (auto I = AS.begin(), E = AS.end(); I != E; ++I)
DEBUG(AS.print(dbgs(), I, " ")); DEBUG(AS.print(dbgs(), I, " "));
#endif #endif
// Finally, don't try to promote any allocas that new require re-splitting. // Finally, don't try to promote any allocas that new require re-splitting.
// They have already been added to the worklist above. // They have already been added to the worklist above.
PromotableAllocas.erase( PromotableAllocas.erase(
std::remove_if( std::remove_if(
▲ Show 20 Lines • Show All 530 Lines • Show Last 20 Lines

lib/Transforms/Utils/CloneFunction.cpp

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesvoid llvm::CloneFunctionInto(Function *NewFunc, const Function *OldFunc,
ValueToValueMapTy &VMap, ValueToValueMapTy &VMap,
bool ModuleLevelChanges, bool ModuleLevelChanges,
SmallVectorImpl<ReturnInst*> &Returns, SmallVectorImpl<ReturnInst*> &Returns,
const char *NameSuffix, ClonedCodeInfo *CodeInfo, const char *NameSuffix, ClonedCodeInfo *CodeInfo,
ValueMapTypeRemapper *TypeMapper, ValueMapTypeRemapper *TypeMapper,
ValueMaterializer *Materializer) { ValueMaterializer *Materializer) {
assert(NameSuffix && "NameSuffix cannot be null!"); assert(NameSuffix && "NameSuffix cannot be null!");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (Function::const_arg_iterator I = OldFunc->arg_begin(), for (Function::const_arg_iterator I = OldFunc->arg_begin(),
E = OldFunc->arg_end(); I != E; ++I) E = OldFunc->arg_end(); I != E; ++I)
assert(VMap.count(I) && "No mapping from source argument specified!"); assert(VMap.count(I) && "No mapping from source argument specified!");
#endif #endif
// Copy all attributes other than those stored in the AttributeSet. We need // Copy all attributes other than those stored in the AttributeSet. We need
// to remap the parameter indices of the AttributeSet. // to remap the parameter indices of the AttributeSet.
AttributeSet NewAttrs = NewFunc->getAttributes(); AttributeSet NewAttrs = NewFunc->getAttributes();
▲ Show 20 Lines • Show All 382 Lines • ▼ Show 20 Linesvoid llvm::CloneAndPruneIntoFromInst(Function *NewFunc, const Function *OldFunc,
ValueMapTypeRemapper *TypeMapper = nullptr; ValueMapTypeRemapper *TypeMapper = nullptr;
ValueMaterializer *Materializer = nullptr; ValueMaterializer *Materializer = nullptr;
if (Director) { if (Director) {
TypeMapper = Director->getTypeRemapper(); TypeMapper = Director->getTypeRemapper();
Materializer = Director->getValueMaterializer(); Materializer = Director->getValueMaterializer();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// If the cloning starts at the begining of the function, verify that // If the cloning starts at the begining of the function, verify that
// the function arguments are mapped. // the function arguments are mapped.
if (!StartingInst) if (!StartingInst)
for (Function::const_arg_iterator II = OldFunc->arg_begin(), for (Function::const_arg_iterator II = OldFunc->arg_begin(),
E = OldFunc->arg_end(); II != E; ++II) E = OldFunc->arg_end(); II != E; ++II)
assert(VMap.count(II) && "No mapping from source argument specified!"); assert(VMap.count(II) && "No mapping from source argument specified!");
#endif #endif
▲ Show 20 Lines • Show All 294 Lines • Show Last 20 Lines

lib/Transforms/Utils/CodeExtractor.cpp

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines if (!Result.insert(*I))
llvm_unreachable("Repeated basic blocks in extraction input"); llvm_unreachable("Repeated basic blocks in extraction input");
if (!isBlockValidForExtraction(**I)) { if (!isBlockValidForExtraction(**I)) {
Result.clear(); Result.clear();
return Result; return Result;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (SetVector<BasicBlock *>::iterator I = std::next(Result.begin()), for (SetVector<BasicBlock *>::iterator I = std::next(Result.begin()),
E = Result.end(); E = Result.end();
I != E; ++I) I != E; ++I)
for (pred_iterator PI = pred_begin(*I), PE = pred_end(*I); for (pred_iterator PI = pred_begin(*I), PE = pred_end(*I);
PI != PE; ++PI) PI != PE; ++PI)
assert(Result.count(*PI) && assert(Result.count(*PI) &&
"No blocks in this region may have entries from outside the region" "No blocks in this region may have entries from outside the region"
" except for the first block!"); " except for the first block!");
▲ Show 20 Lines • Show All 679 Lines • Show Last 20 Lines

lib/Transforms/Utils/Local.cpp

Show First 20 Lines • Show All 417 Lines • ▼ Show 20 Lines
/// simplify any instructions in it and recursively delete dead instructions. /// simplify any instructions in it and recursively delete dead instructions.
/// ///
/// This returns true if it changed the code, note that it can delete /// This returns true if it changed the code, note that it can delete
/// instructions in other blocks as well in this block. /// instructions in other blocks as well in this block.
bool llvm::SimplifyInstructionsInBlock(BasicBlock *BB, bool llvm::SimplifyInstructionsInBlock(BasicBlock *BB,
const TargetLibraryInfo *TLI) { const TargetLibraryInfo *TLI) {
bool MadeChange = false; bool MadeChange = false;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
// In debug builds, ensure that the terminator of the block is never replaced // In debug builds, ensure that the terminator of the block is never replaced
// or deleted by these simplifications. The idea of simplification is that it // or deleted by these simplifications. The idea of simplification is that it
// cannot introduce new instructions, and there is no way to replace the // cannot introduce new instructions, and there is no way to replace the
// terminator of a block without introducing a new instruction. // terminator of a block without introducing a new instruction.
AssertingVH<Instruction> TerminatorVH(--BB->end()); AssertingVH<Instruction> TerminatorVH(--BB->end());
#endif #endif
for (BasicBlock::iterator BI = BB->begin(), E = --BB->end(); BI != E; ) { for (BasicBlock::iterator BI = BB->begin(), E = --BB->end(); BI != E; ) {
▲ Show 20 Lines • Show All 912 Lines • Show Last 20 Lines

lib/Transforms/Utils/LowerSwitch.cpp

Show First 20 Lines • Show All 457 Lines • ▼ Show 20 Lines for (const auto &I : Cases) {
// Count popularity. // Count popularity.
int64_t N = High - Low + 1; int64_t N = High - Low + 1;
unsigned &Pop = Popularity[I.BB]; unsigned &Pop = Popularity[I.BB];
if ((Pop += N) > MaxPop) { if ((Pop += N) > MaxPop) {
MaxPop = Pop; MaxPop = Pop;
PopSucc = I.BB; PopSucc = I.BB;
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/* UnreachableRanges should be sorted and the ranges non-adjacent. */ /* UnreachableRanges should be sorted and the ranges non-adjacent. */
for (auto I = UnreachableRanges.begin(), E = UnreachableRanges.end(); for (auto I = UnreachableRanges.begin(), E = UnreachableRanges.end();
I != E; ++I) { I != E; ++I) {
assert(I->Low <= I->High); assert(I->Low <= I->High);
auto Next = I + 1; auto Next = I + 1;
if (Next != E) { if (Next != E) {
assert(Next->Low > I->High); assert(Next->Low > I->High);
} }
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

lib/Transforms/Vectorize/BBVectorize.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
NoMemOpBoost("bb-vectorize-no-mem-op-boost", NoMemOpBoost("bb-vectorize-no-mem-op-boost",
cl::init(false), cl::Hidden, cl::init(false), cl::Hidden,
cl::desc("Don't boost the chain-depth contribution of loads and stores")); cl::desc("Don't boost the chain-depth contribution of loads and stores"));
static cl::opt<bool> static cl::opt<bool>
FastDep("bb-vectorize-fast-dep", cl::init(false), cl::Hidden, FastDep("bb-vectorize-fast-dep", cl::init(false), cl::Hidden,
cl::desc("Use a fast instruction dependency analysis")); cl::desc("Use a fast instruction dependency analysis"));
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static cl::opt<bool> static cl::opt<bool>
DebugInstructionExamination("bb-vectorize-debug-instruction-examination", DebugInstructionExamination("bb-vectorize-debug-instruction-examination",
cl::init(false), cl::Hidden, cl::init(false), cl::Hidden,
cl::desc("When debugging is enabled, output information on the" cl::desc("When debugging is enabled, output information on the"
" instruction-examination process")); " instruction-examination process"));
static cl::opt<bool> static cl::opt<bool>
DebugCandidateSelection("bb-vectorize-debug-candidate-selection", DebugCandidateSelection("bb-vectorize-debug-candidate-selection",
cl::init(false), cl::Hidden, cl::init(false), cl::Hidden,
▲ Show 20 Lines • Show All 3,065 Lines • Show Last 20 Lines

lib/Transforms/Vectorize/LoopVectorize.cpp

Show First 20 Lines • Show All 512 Lines • ▼ Show 20 Lines
/// instruction. /// instruction.
static void setDebugLocFromInst(IRBuilder<> &B, const Value *Ptr) { static void setDebugLocFromInst(IRBuilder<> &B, const Value *Ptr) {
if (const Instruction *Inst = dyn_cast_or_null<Instruction>(Ptr)) if (const Instruction *Inst = dyn_cast_or_null<Instruction>(Ptr))
B.SetCurrentDebugLocation(Inst->getDebugLoc()); B.SetCurrentDebugLocation(Inst->getDebugLoc());
else else
B.SetCurrentDebugLocation(DebugLoc()); B.SetCurrentDebugLocation(DebugLoc());
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// \return string containing a file name and a line # for the given loop. /// \return string containing a file name and a line # for the given loop.
static std::string getDebugLocString(const Loop *L) { static std::string getDebugLocString(const Loop *L) {
std::string Result; std::string Result;
if (L) { if (L) {
raw_string_ostream OS(Result); raw_string_ostream OS(Result);
if (const DebugLoc LoopDbgLoc = L->getStartLoc()) if (const DebugLoc LoopDbgLoc = L->getStartLoc())
LoopDbgLoc.print(OS); LoopDbgLoc.print(OS);
else else
▲ Show 20 Lines • Show All 997 Lines • ▼ Show 20 Lines if (!IsUnrollMetadata) {
NewLoopID->replaceOperandWith(0, NewLoopID); NewLoopID->replaceOperandWith(0, NewLoopID);
L->setLoopID(NewLoopID); L->setLoopID(NewLoopID);
} }
} }
bool processLoop(Loop *L) { bool processLoop(Loop *L) {
assert(L->empty() && "Only process inner loops."); assert(L->empty() && "Only process inner loops.");
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const std::string DebugLocStr = getDebugLocString(L); const std::string DebugLocStr = getDebugLocString(L);
#endif /* NDEBUG */ #endif /* LLVM_NDEBUG */
DEBUG(dbgs() << "\nLV: Checking a loop in \"" DEBUG(dbgs() << "\nLV: Checking a loop in \""
<< L->getHeader()->getParent()->getName() << "\" from " << L->getHeader()->getParent()->getName() << "\" from "
<< DebugLocStr << "\n"); << DebugLocStr << "\n");
LoopVectorizeHints Hints(L, DisableUnrolling); LoopVectorizeHints Hints(L, DisableUnrolling);
DEBUG(dbgs() << "LV: Loop hints:" DEBUG(dbgs() << "LV: Loop hints:"
▲ Show 20 Lines • Show All 2,981 Lines • ▼ Show 20 Lines if (UserVF != 0) {
assert(isPowerOf2_32(UserVF) && "VF needs to be a power of two"); assert(isPowerOf2_32(UserVF) && "VF needs to be a power of two");
DEBUG(dbgs() << "LV: Using user VF " << UserVF << ".\n"); DEBUG(dbgs() << "LV: Using user VF " << UserVF << ".\n");
Factor.Width = UserVF; Factor.Width = UserVF;
return Factor; return Factor;
} }
float Cost = expectedCost(1); float Cost = expectedCost(1);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
const float ScalarCost = Cost; const float ScalarCost = Cost;
#endif /* NDEBUG */ #endif /* LLVM_NDEBUG */
unsigned Width = 1; unsigned Width = 1;
DEBUG(dbgs() << "LV: Scalar loop costs: " << (int)ScalarCost << ".\n"); DEBUG(dbgs() << "LV: Scalar loop costs: " << (int)ScalarCost << ".\n");
bool ForceVectorization = Hints->getForce() == LoopVectorizeHints::FK_Enabled; bool ForceVectorization = Hints->getForce() == LoopVectorizeHints::FK_Enabled;
// Ignore scalar width, because the user explicitly wants vectorization. // Ignore scalar width, because the user explicitly wants vectorization.
if (ForceVectorization && VF > 1) { if (ForceVectorization && VF > 1) {
Width = 2; Width = 2;
Cost = expectedCost(Width) / (float)Width; Cost = expectedCost(Width) / (float)Width;
▲ Show 20 Lines • Show All 860 Lines • Show Last 20 Lines

lib/Transforms/Vectorize/SLPVectorizer.cpp

Show First 20 Lines • Show All 698 Lines • ▼ Show 20 Lines struct ScheduleData {
/// single instructions. /// single instructions.
int UnscheduledDepsInBundle; int UnscheduledDepsInBundle;
/// True if this instruction is scheduled (or considered as scheduled in the /// True if this instruction is scheduled (or considered as scheduled in the
/// dry-run). /// dry-run).
bool IsScheduled; bool IsScheduled;
}; };
#ifndef NDEBUG #ifndef LLVM_NDEBUG
friend raw_ostream &operator<<(raw_ostream &os, friend raw_ostream &operator<<(raw_ostream &os,
const BoUpSLP::ScheduleData &SD); const BoUpSLP::ScheduleData &SD);
#endif #endif
/// Contains all scheduling data for a basic block. /// Contains all scheduling data for a basic block.
/// ///
struct BlockScheduling { struct BlockScheduling {
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines#endif
TargetLibraryInfo *TLI; TargetLibraryInfo *TLI;
AliasAnalysis *AA; AliasAnalysis *AA;
LoopInfo *LI; LoopInfo *LI;
DominatorTree *DT; DominatorTree *DT;
/// Instruction builder to construct the vectorized tree. /// Instruction builder to construct the vectorized tree.
IRBuilder<> Builder; IRBuilder<> Builder;
}; };
#ifndef NDEBUG #ifndef LLVM_NDEBUG
raw_ostream &operator<<(raw_ostream &os, const BoUpSLP::ScheduleData &SD) { raw_ostream &operator<<(raw_ostream &os, const BoUpSLP::ScheduleData &SD) {
SD.dump(os); SD.dump(os);
return os; return os;
} }
#endif #endif
void BoUpSLP::buildTree(ArrayRef<Value *> Roots, void BoUpSLP::buildTree(ArrayRef<Value *> Roots,
ArrayRef<Value *> UserIgnoreLst) { ArrayRef<Value *> UserIgnoreLst) {
▲ Show 20 Lines • Show All 1,650 Lines • ▼ Show 20 Lines for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) {
// No need to handle users of gathered values. // No need to handle users of gathered values.
if (Entry->NeedToGather) if (Entry->NeedToGather)
continue; continue;
assert(Entry->VectorizedValue && "Can't find vectorizable value"); assert(Entry->VectorizedValue && "Can't find vectorizable value");
Type *Ty = Scalar->getType(); Type *Ty = Scalar->getType();
if (!Ty->isVoidTy()) { if (!Ty->isVoidTy()) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (User *U : Scalar->users()) { for (User *U : Scalar->users()) {
DEBUG(dbgs() << "SLP: \tvalidating user:" << *U << ".\n"); DEBUG(dbgs() << "SLP: \tvalidating user:" << *U << ".\n");
assert((ScalarToTreeEntry.count(U) || assert((ScalarToTreeEntry.count(U) ||
// It is legal to replace users in the ignorelist by undef. // It is legal to replace users in the ignorelist by undef.
(std::find(UserIgnoreList.begin(), UserIgnoreList.end(), U) != (std::find(UserIgnoreList.begin(), UserIgnoreList.end(), U) !=
UserIgnoreList.end())) && UserIgnoreList.end())) &&
"Replacing out-of-tree value with undef"); "Replacing out-of-tree value with undef");
▲ Show 20 Lines • Show All 1,493 Lines • Show Last 20 Lines

tools/verify-uselistorder/verify-uselistorder.cpp

Show First 20 Lines • Show All 236 Lines • ▼ Show 20 Lines if (auto *C = dyn_cast<Constant>(V))
if (!isa<GlobalValue>(C)) if (!isa<GlobalValue>(C))
for (const Value *Op : C->operands()) for (const Value *Op : C->operands())
map(Op); map(Op);
Values.push_back(V); Values.push_back(V);
IDs[V] = Values.size(); IDs[V] = Values.size();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static void dumpMapping(const ValueMapping &VM) { static void dumpMapping(const ValueMapping &VM) {
dbgs() << "value-mapping (size = " << VM.Values.size() << "):\n"; dbgs() << "value-mapping (size = " << VM.Values.size() << "):\n";
for (unsigned I = 0, E = VM.Values.size(); I != E; ++I) { for (unsigned I = 0, E = VM.Values.size(); I != E; ++I) {
dbgs() << " - id = " << I << ", value = "; dbgs() << " - id = " << I << ", value = ";
VM.Values[I]->dump(); VM.Values[I]->dump();
} }
} }
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utils/TableGen/CodeGenDAGPatterns.cpp

Show First 20 Lines • Show All 692 Lines • ▼ Show 20 Linesstatic void FindDepVars(TreePatternNode *N, MultipleUseVarSet &DepVars) {
DepVarMap depcounts; DepVarMap depcounts;
FindDepVarsOf(N, depcounts); FindDepVarsOf(N, depcounts);
for (DepVarMap_citer i = depcounts.begin(); i != depcounts.end(); ++i) { for (DepVarMap_citer i = depcounts.begin(); i != depcounts.end(); ++i) {
if (i->second > 1) // std::pair<std::string, int> if (i->second > 1) // std::pair<std::string, int>
DepVars.insert(i->first); DepVars.insert(i->first);
} }
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
/// Dump the dependent variable set: /// Dump the dependent variable set:
static void DumpDepVars(MultipleUseVarSet &DepVars) { static void DumpDepVars(MultipleUseVarSet &DepVars) {
if (DepVars.empty()) { if (DepVars.empty()) {
DEBUG(errs() << "<empty set>"); DEBUG(errs() << "<empty set>");
} else { } else {
DEBUG(errs() << "[ "); DEBUG(errs() << "[ ");
for (MultipleUseVarSet::const_iterator i = DepVars.begin(), for (MultipleUseVarSet::const_iterator i = DepVars.begin(),
e = DepVars.end(); i != e; ++i) { e = DepVars.end(); i != e; ++i) {
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/// pattern's predicates concatenated with "&&" operators. /// pattern's predicates concatenated with "&&" operators.
/// ///
std::string PatternToMatch::getPredicateCheck() const { std::string PatternToMatch::getPredicateCheck() const {
std::string PredicateCheck; std::string PredicateCheck;
for (Init *I : Predicates->getValues()) { for (Init *I : Predicates->getValues()) {
if (DefInit *Pred = dyn_cast<DefInit>(I)) { if (DefInit *Pred = dyn_cast<DefInit>(I)) {
Record *Def = Pred->getDef(); Record *Def = Pred->getDef();
if (!Def->isSubClassOf("Predicate")) { if (!Def->isSubClassOf("Predicate")) {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
Def->dump(); Def->dump();
#endif #endif
llvm_unreachable("Unknown predicate type!"); llvm_unreachable("Unknown predicate type!");
} }
if (!PredicateCheck.empty()) if (!PredicateCheck.empty())
PredicateCheck += " && "; PredicateCheck += " && ";
PredicateCheck += "(" + Def->getValueAsString("CondString") + ")"; PredicateCheck += "(" + Def->getValueAsString("CondString") + ")";
} }
▲ Show 20 Lines • Show All 2,663 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = ChildVariants.size(); i != e; ++i)
if (ChildVariants[i].empty()) if (ChildVariants[i].empty())
return; return;
// The end result is an all-pairs construction of the resultant pattern. // The end result is an all-pairs construction of the resultant pattern.
std::vector<unsigned> Idxs; std::vector<unsigned> Idxs;
Idxs.resize(ChildVariants.size()); Idxs.resize(ChildVariants.size());
bool NotDone; bool NotDone;
do { do {
#ifndef NDEBUG #ifndef LLVM_NDEBUG
DEBUG(if (!Idxs.empty()) { DEBUG(if (!Idxs.empty()) {
errs() << Orig->getOperator()->getName() << ": Idxs = [ "; errs() << Orig->getOperator()->getName() << ": Idxs = [ ";
for (unsigned i = 0; i < Idxs.size(); ++i) { for (unsigned i = 0; i < Idxs.size(); ++i) {
errs() << Idxs[i] << " "; errs() << Idxs[i] << " ";
} }
errs() << "]\n"; errs() << "]\n";
}); });
#endif #endif
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utils/TableGen/CodeGenSchedule.h

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines bool isValid() const {
assert((!HasVariants || TheDef) && "Variant write needs record def"); assert((!HasVariants || TheDef) && "Variant write needs record def");
assert((!IsVariadic || HasVariants) && "Variadic write needs variants"); assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
assert((!IsSequence || !HasVariants) && "Sequence can't have variant"); assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty"); assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases"); assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
return TheDef || !Sequence.empty(); return TheDef || !Sequence.empty();
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void dump() const; void dump() const;
#endif #endif
}; };
/// Represent a transition between SchedClasses induced by SchedVariant. /// Represent a transition between SchedClasses induced by SchedVariant.
struct CodeGenSchedTransition { struct CodeGenSchedTransition {
unsigned ToClassIdx; unsigned ToClassIdx;
IdxVec ProcIndices; IdxVec ProcIndices;
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesstruct CodeGenSchedClass {
bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) { bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) {
return ItinClassDef == IC && Writes == W && Reads == R; return ItinClassDef == IC && Writes == W && Reads == R;
} }
// Is this class generated from a variants if existing classes? Instructions // Is this class generated from a variants if existing classes? Instructions
// are never mapped directly to inferred scheduling classes. // are never mapped directly to inferred scheduling classes.
bool isInferred() const { return !ItinClassDef; } bool isInferred() const { return !ItinClassDef; }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void dump(const CodeGenSchedModels *SchedModels) const; void dump(const CodeGenSchedModels *SchedModels) const;
#endif #endif
}; };
// Processor model. // Processor model.
// //
// ModelName is a unique name used to name an instantiation of MCSchedModel. // ModelName is a unique name used to name an instantiation of MCSchedModel.
// //
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesstruct CodeGenProcModel {
} }
bool hasInstrSchedModel() const { bool hasInstrSchedModel() const {
return !WriteResDefs.empty() || !ItinRWDefs.empty(); return !WriteResDefs.empty() || !ItinRWDefs.empty();
} }
unsigned getProcResourceIdx(Record *PRDef) const; unsigned getProcResourceIdx(Record *PRDef) const;
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void dump() const; void dump() const;
#endif #endif
}; };
/// Top level container for machine model data. /// Top level container for machine model data.
class CodeGenSchedModels { class CodeGenSchedModels {
RecordKeeper &Records; RecordKeeper &Records;
const CodeGenTarget &Target; const CodeGenTarget &Target;
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utils/TableGen/CodeGenSchedule.cpp

Show All 17 Lines
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/Regex.h" #include "llvm/Support/Regex.h"
#include "llvm/TableGen/Error.h" #include "llvm/TableGen/Error.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "subtarget-emitter" #define DEBUG_TYPE "subtarget-emitter"
#ifndef NDEBUG #ifndef LLVM_NDEBUG
static void dumpIdxVec(const IdxVec &V) { static void dumpIdxVec(const IdxVec &V) {
for (unsigned i = 0, e = V.size(); i < e; ++i) { for (unsigned i = 0, e = V.size(); i < e; ++i) {
dbgs() << V[i] << ", "; dbgs() << V[i] << ", ";
} }
} }
static void dumpIdxVec(const SmallVectorImpl<unsigned> &V) { static void dumpIdxVec(const SmallVectorImpl<unsigned> &V) {
for (unsigned i = 0, e = V.size(); i < e; ++i) { for (unsigned i = 0, e = V.size(); i < e; ++i) {
dbgs() << V[i] << ", "; dbgs() << V[i] << ", ";
▲ Show 20 Lines • Show All 907 Lines • ▼ Show 20 Linespublic:
PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {} PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
void substituteVariantOperand(const SmallVectorImpl<unsigned> &RWSeq, void substituteVariantOperand(const SmallVectorImpl<unsigned> &RWSeq,
bool IsRead, unsigned StartIdx); bool IsRead, unsigned StartIdx);
void substituteVariants(const PredTransition &Trans); void substituteVariants(const PredTransition &Trans);
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void dump() const; void dump() const;
#endif #endif
private: private:
bool mutuallyExclusive(Record *PredDef, ArrayRef<PredCheck> Term); bool mutuallyExclusive(Record *PredDef, ArrayRef<PredCheck> Term);
void getIntersectingVariants( void getIntersectingVariants(
const CodeGenSchedRW &SchedRW, unsigned TransIdx, const CodeGenSchedRW &SchedRW, unsigned TransIdx,
std::vector<TransVariant> &IntersectingVariants); std::vector<TransVariant> &IntersectingVariants);
▲ Show 20 Lines • Show All 744 Lines • ▼ Show 20 Lines RecIter PRPos = std::find(ProcResourceDefs.begin(), ProcResourceDefs.end(),
PRDef); PRDef);
if (PRPos == ProcResourceDefs.end()) if (PRPos == ProcResourceDefs.end())
PrintFatalError(PRDef->getLoc(), "ProcResource def is not included in " PrintFatalError(PRDef->getLoc(), "ProcResource def is not included in "
"the ProcResources list for " + ModelName); "the ProcResources list for " + ModelName);
// Idx=0 is reserved for invalid. // Idx=0 is reserved for invalid.
return 1 + (PRPos - ProcResourceDefs.begin()); return 1 + (PRPos - ProcResourceDefs.begin());
} }
#ifndef NDEBUG #ifndef LLVM_NDEBUG
void CodeGenProcModel::dump() const { void CodeGenProcModel::dump() const {
dbgs() << Index << ": " << ModelName << " " dbgs() << Index << ": " << ModelName << " "
<< (ModelDef ? ModelDef->getName() : "inferred") << " " << (ModelDef ? ModelDef->getName() : "inferred") << " "
<< (ItinsDef ? ItinsDef->getName() : "no itinerary") << '\n'; << (ItinsDef ? ItinsDef->getName() : "no itinerary") << '\n';
} }
void CodeGenSchedRW::dump() const { void CodeGenSchedRW::dump() const {
dbgs() << Name << (IsVariadic ? " (V) " : " "); dbgs() << Name << (IsVariadic ? " (V) " : " ");
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
dbgs() << ", "; dbgs() << ", ";
dbgs() << SchedModels.getSchedWrite(*WI).Name; dbgs() << SchedModels.getSchedWrite(*WI).Name;
} }
dbgs() << "),"; dbgs() << "),";
} }
dbgs() << "}\n"; dbgs() << "}\n";
} }
} }
#endif // NDEBUG #endif // LLVM_NDEBUG

utils/TableGen/RegisterInfoEmitter.cpp

Show First 20 Lines • Show All 862 Lines • ▼ Show 20 Lines for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
RegUnitInitScale[i] = Scale; RegUnitInitScale[i] = Scale;
DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
const auto &RUMasks = Reg.getRegUnitLaneMasks(); const auto &RUMasks = Reg.getRegUnitLaneMasks();
MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
assert(LaneMaskVec.empty()); assert(LaneMaskVec.empty());
LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end()); LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end());
// Terminator mask should not be used inside of the list. // Terminator mask should not be used inside of the list.
#ifndef NDEBUG #ifndef LLVM_NDEBUG
for (unsigned M : LaneMaskVec) { for (unsigned M : LaneMaskVec) {
assert(M != ~0u && "terminator mask should not be part of the list"); assert(M != ~0u && "terminator mask should not be part of the list");
} }
#endif #endif
LaneMaskSeqs.add(LaneMaskVec); LaneMaskSeqs.add(LaneMaskVec);
} }
// Compute the final layout of the sequence table. // Compute the final layout of the sequence table.
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utils/TableGen/SubtargetEmitter.cpp

Show First 20 Lines • Show All 817 Lines • ▼ Show 20 Linesvoid SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(), for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) { SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
DEBUG(SCI->dump(&SchedModels)); DEBUG(SCI->dump(&SchedModels));
SCTab.resize(SCTab.size() + 1); SCTab.resize(SCTab.size() + 1);
MCSchedClassDesc &SCDesc = SCTab.back(); MCSchedClassDesc &SCDesc = SCTab.back();
// SCDesc.Name is guarded by NDEBUG // SCDesc.Name is guarded by LLVM_NDEBUG
SCDesc.NumMicroOps = 0; SCDesc.NumMicroOps = 0;
SCDesc.BeginGroup = false; SCDesc.BeginGroup = false;
SCDesc.EndGroup = false; SCDesc.EndGroup = false;
SCDesc.WriteProcResIdx = 0; SCDesc.WriteProcResIdx = 0;
SCDesc.WriteLatencyIdx = 0; SCDesc.WriteLatencyIdx = 0;
SCDesc.ReadAdvanceIdx = 0; SCDesc.ReadAdvanceIdx = 0;
// A Variant SchedClass has no resources of its own. // A Variant SchedClass has no resources of its own.
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// //
// EmitSchedModel - Emits all scheduling model tables, folding common patterns. // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
// //
void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
OS << "#ifdef DBGFIELD\n" OS << "#ifdef DBGFIELD\n"
<< "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n" << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
<< "#endif\n" << "#endif\n"
<< "#ifndef NDEBUG\n" << "#ifndef LLVM_NDEBUG\n"
<< "#define DBGFIELD(x) x,\n" << "#define DBGFIELD(x) x,\n"
<< "#else\n" << "#else\n"
<< "#define DBGFIELD(x)\n" << "#define DBGFIELD(x)\n"
<< "#endif\n"; << "#endif\n";
if (SchedModels.hasItineraries()) { if (SchedModels.hasItineraries()) {
std::vector<std::vector<InstrItinerary> > ProcItinLists; std::vector<std::vector<InstrItinerary> > ProcItinLists;
// Emit the stage data // Emit the stage data
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