[Hexagon] Return an i64 for result 0 from LowerREADCYCLECOUNTER instead of an i32.

[craig.topper]

Summary

As far as I can tell, the node coming in has an i64 result so the
return should have the same type. The HexagonISD node used for
this has a type profile that says the result is i64.

Found while trying to add assserts to LegalizeDAG to catch
result type mismatches.

[kparzysz]

Thanks!

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
 // is marked as having side-effects, while the register read on Hexagon does
 // not have any. TableGen refuses to accept the direct pattern from that node
 // to the A4_tfrcpp.
 SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   SDLoc dl(Op);
-  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
+  SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
   return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
 }
 
 SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
       SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
   // Lower the hexagon_prefetch builtin to DCFETCH, as above.