As a preparation step for fast8 support, we need to update the tests
to pass in both modes. That requires generalizing the shadow width
and remove any hard coded references that assume it's always 2 bytes.
Details
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll | ||
---|---|---|
10 | Is this one testing 2x for 16bit mode? This is still useful to lock down generated IR. |
llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll | ||
---|---|---|
10 | Exactly. That instruction won't be generated with 8bit mode, which is why I removed it so that the test can work in both modes in the future. If we want to keep it, do you have any suggestions on how to make it conditional (only when SBYTES != 1)? |
llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll | ||
---|---|---|
10 | Some test cases also check the pattern of loading an i32 value like x = load y = load z = or x y The two modes have different numbers of these loads and ors. That also requires two check prefixes. |
Add conditional check for multiplication in external_mask.ll.
Also update custom_fun_varargs_attributes.ll.
llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll | ||
---|---|---|
10 | Added second prefix. |
Is this one testing 2x for 16bit mode? This is still useful to lock down generated IR.