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[dfsan] Remove hard-coded shadow width in more tests
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Authored by gbalats on Mar 3 2021, 12:36 PM.

Details

Summary

As a preparation step for fast8 support, we need to update the tests
to pass in both modes. That requires generalizing the shadow width
and remove any hard coded references that assume it's always 2 bytes.

Diff Detail

Event Timeline

gbalats requested review of this revision.Mar 3 2021, 12:36 PM
gbalats created this revision.
llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll
10

Is this one testing 2x for 16bit mode? This is still useful to lock down generated IR.

gbalats added inline comments.Mar 3 2021, 2:22 PM
llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll
10

Exactly. That instruction won't be generated with 8bit mode, which is why I removed it so that the test can work in both modes in the future. If we want to keep it, do you have any suggestions on how to make it conditional (only when SBYTES != 1)?

llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll
10

Some test cases also check the pattern of loading an i32 value like

x = load
y = load
z = or x y

The two modes have different numbers of these loads and ors. That also requires two check prefixes.

gbalats updated this revision to Diff 327924.Mar 3 2021, 2:34 PM

Add conditional check for multiplication in external_mask.ll.

Also update custom_fun_varargs_attributes.ll.

gbalats added inline comments.Mar 3 2021, 2:35 PM
llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll
10

Added second prefix.

gbalats marked 2 inline comments as done.Mar 3 2021, 2:35 PM
This revision is now accepted and ready to land.Mar 3 2021, 2:39 PM
This revision was landed with ongoing or failed builds.Mar 3 2021, 3:06 PM
This revision was automatically updated to reflect the committed changes.