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Differential D9751

Add HSAIL target
AbandonedPublic

Authored by arsenm on May 13 2015, 8:37 AM.

Details

Reviewers
• tstellarAMD
Summary

Just includes patch to add bulk of target, not tests or other prerequisite patches.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 25697.May 13 2015, 8:37 AM
arsenm retitled this revision from to Add HSAIL target.
arsenm updated this object.
arsenm edited the test plan for this revision. (Show Details)
arsenm added a subscriber: Unknown Object (MLST).
arsenm updated this revision to Diff 28070.Jun 19 2015, 6:49 PM

Update for trunk changes, plus a few bug fixes. Add new WIP set of intrinsics.

Herald added a reviewer: qcolombet. · View Herald TranscriptJun 19 2015, 6:49 PM
• rafael added a subscriber: • rafael.Jun 22 2015, 12:32 PM
• rafael added inline comments.
lib/Target/HSAIL/CMakeLists.txt
20

Please leave this out of the first version.

Having two code paths in CodeGen in pretty bad, specially when one of them depends on an external library.

arsenm updated this revision to Diff 29132.Jul 6 2015, 3:23 PM
arsenm edited edge metadata.

Remove libHSAIL option / path

• rafael added inline comments.Jul 10 2015, 1:05 PM
include/llvm/Support/ELF.h
237

I don't see these in http://www.sco.com/developers/gabi/latest/ch4.eheader.html.

lib/Target/HSAIL/CMakeLists.txt
51

No commented out code please.

lib/Target/HSAIL/HSAIL.h
70

Empty comments?

104

Don't repeat names in comments.

lib/Target/HSAIL/HSAILAlwaysInlinePass.cpp
27

please git-clang-format the patch.

59

range loop?

lib/Target/HSAIL/HSAILAsmPrinter.h
34

Start functions with lowercase letter when you can (or is this missing an override?)

lib/Target/HSAIL/HSAILSection.cpp
16

Just don't create sections instead of having empty section switching.

MatzeB added a subscriber: MatzeB.Jul 10 2015, 1:28 PM

Just some codingstyle issues I found while skimming over a few files

lib/Target/HSAIL/AMDOpenCLKernenv.h
11–13

Needs three slashes. There are similar problems in many of the other files.

17–18

Should be changed to LIB_TARGET_HSAIL_AMDOPENCLKERNELENV_H. There are similar issues in other headers.

lib/Target/HSAIL/HSAIL.h
26–44

Better use static const unsigned or enum values so debuggers can pick those constants up as well.

218–222

Could use doxygen comments here:
/// Target architectures ...
enum ... {

GENERIC, ///< No target specific flavor
...
lib/Target/HSAIL/HSAILAlwaysInlinePass.cpp
25

Would be nice to name the file like the class declared inside.

test/CodeGen/HSAIL/128bit-kernel-args.ll
2

Many of the tests define new prefixes instead of just using "CHECK" should be unnecessary if you just test for 1 variant anyway.

arsenm updated this revision to Diff 29605.Jul 13 2015, 2:18 PM

Update based on review comments.

arsenm added inline comments.Jul 13 2015, 2:22 PM
include/llvm/Support/ELF.h
237

This is being requested

lib/Target/HSAIL/HSAILAlwaysInlinePass.cpp
59

I fixed this in the AMDGPU copy of this pass, so once http://reviews.llvm.org/D11155 is in I'll just remove this file.

lib/Target/HSAIL/HSAILSection.cpp
16

These sections are created by the generic code in the AsmPrinter. This is exactly what NVPTX does currently to fix this.

test/CodeGen/HSAIL/128bit-kernel-args.ll
2

People have expressed regret as having a default of CHECK for this before. The idea is someday it might be useful to add an HSAIL64 or something like that someday.

arsenm added a comment.Jul 20 2015, 8:29 AM

ping

qcolombet resigned from this revision.Aug 5 2015, 1:19 PM
qcolombet removed a reviewer: qcolombet.
• tstellarAMD added a reviewer: • tstellarAMD.Aug 21 2015, 8:48 AM
• tstellarAMD added inline comments.Aug 21 2015, 9:40 AM
lib/Target/HSAIL/HSAILISelDAGToDAG.cpp
606–608

Does this function really need to be recursive? it seems more complicated than it needs to be.

lib/Target/HSAIL/MCTargetDesc/RawVectorOstream.h
23–25

Is there a reason this isn't in common code?

arsenm added inline comments.Aug 21 2015, 12:10 PM
lib/Target/HSAIL/HSAILISelDAGToDAG.cpp
606–608

This could probably be simplified a lot. The cases for ADD/OR looks unnecessary. It seems to mostly be to workaround the ADD -> OR combine. I don't think LDA needs to be handled here at all. I fixed it so that global addresses are handled during selection, so this shouldn't be seeing the custom node (which doesn't seem to be used anymore)

lib/Target/HSAIL/MCTargetDesc/RawVectorOstream.h
23–25

I think I can completely remove this for now since it should only be used by the BRIGAsmPrinter

vchuravy added a subscriber: vchuravy.Jan 17 2017, 8:21 AM
arsenm abandoned this revision.Jan 31 2017, 4:58 PM

Large Diff

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Diff 29605

CODE_OWNERS.TXT

docs/CompilerWriterInfo.rst

include/llvm/IR/Intrinsics.td

include/llvm/IR/IntrinsicsHSAIL.td

include/llvm/Support/ELF.h

Context not available.
// Controller // Controller
EM_CE = 119, // Freescale Communication Engine RISC core EM_CE = 119, // Freescale Communication Engine RISC core
EM_M32C = 120, // Renesas M32C series microprocessors EM_M32C = 120, // Renesas M32C series microprocessors
EM_HSAIL = 128, // HSAIL 32bit
rafaelUnsubmitted
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I don't see these in http://www.sco.com/developers/gabi/latest/ch4.eheader.html.

rafael: I don't see these in http://www.sco.com/developers/gabi/latest/ch4.eheader.html.
arsenmAuthorUnsubmitted
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This is being requested

arsenm: This is being requested
EM_HSAIL_64 = 129, // HSAIL 64bit
EM_TSK3000 = 131, // Altium TSK3000 core EM_TSK3000 = 131, // Altium TSK3000 core
EM_RS08 = 132, // Freescale RS08 embedded processor EM_RS08 = 132, // Freescale RS08 embedded processor
EM_SHARC = 133, // Analog Devices SHARC family of 32-bit DSP EM_SHARC = 133, // Analog Devices SHARC family of 32-bit DSP
Context not available.

lib/Target/HSAIL/AMDOpenCLKernenv.h

  • This file was added.
//===-- AMDOpenCLKernenv.h - HSAIL kernenv for OpenCL -----*- C++ -*---=======//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// \brief Declare OpenCL dispatch-specific constants that are passed
/// as additional arguments (the "kernenv") to the HSAIL kernel.
//
MatzeBUnsubmitted
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Needs three slashes. There are similar problems in many of the other files.

MatzeB: Needs three slashes. There are similar problems in many of the other files.
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_HSAIL_AMDOPENCLKERNENV_H
#define LLVM_LIB_TARGET_HSAIL_AMDOPENCLKERNENV_H
MatzeBUnsubmitted
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Should be changed to LIB_TARGET_HSAIL_AMDOPENCLKERNELENV_H. There are similar issues in other headers.

MatzeB: Should be changed to LIB_TARGET_HSAIL_AMDOPENCLKERNELENV_H. There are similar issues in other…
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/Support/ErrorHandling.h"
namespace llvm {
class LLVMContext;
namespace HSAIL {
enum {
KE_GOFFSET_0,
KE_GOFFSET_1,
KE_GOFFSET_2,
KE_OCL12_NUM_ARGS,
KE_PRINTF_BFR = KE_OCL12_NUM_ARGS,
KE_VQ_PTR,
KE_AQLWRAP_PTR,
KE_OCL20_NUM_ARGS,
KE_NUM_ARGS = KE_OCL20_NUM_ARGS // Always the last member.
};
}
static inline StringRef getKernenvArgName(unsigned ID) {
switch (ID) {
case HSAIL::KE_GOFFSET_0:
return "__global_offset_0";
case HSAIL::KE_GOFFSET_1:
return "__global_offset_1";
case HSAIL::KE_GOFFSET_2:
return "__global_offset_2";
case HSAIL::KE_PRINTF_BFR:
return "__printf_buffer";
case HSAIL::KE_VQ_PTR:
return "__vqueue_pointer";
case HSAIL::KE_AQLWRAP_PTR:
return "__aqlwrap_pointer";
default:
llvm_unreachable("unexpected Kernenv argument ID");
}
}
static inline Type *getKernenvArgType(unsigned ID, LLVMContext &C,
bool is64bit) {
if (ID == HSAIL::KE_PRINTF_BFR)
return Type::getInt8PtrTy(C, 1);
return (is64bit ? Type::getInt64Ty(C) : Type::getInt32Ty(C));
}
static inline StringRef getKernenvArgTypeName(unsigned ID) { return "size_t"; }
}
#endif

lib/Target/HSAIL/CMakeLists.txt

  • This file was added.
include(CMakeDependentOption)
set(LLVM_TARGET_DEFINITIONS HSAIL.td)
tablegen(LLVM HSAILGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM HSAILGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM HSAILGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HSAILGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM HSAILGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM HSAILGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM HSAILGenCallingConv.inc -gen-callingconv)
tablegen(LLVM HSAILGenIntrinsics.inc -gen-tgt-intrinsic)
add_public_tablegen_target(HSAILCommonTableGen)
add_subdirectory(HSAILUtil)
set(sources
HSAILAsmPrinter.cpp
rafaelUnsubmitted
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Please leave this out of the first version.

Having two code paths in CodeGen in pretty bad, specially when one of them depends on an external library.

rafael: Please leave this out of the first version. Having two code paths in CodeGen in pretty bad…
HSAILAlwaysInlinePass.cpp
HSAILELFTargetObjectFile.cpp
HSAILFrameLowering.cpp
HSAILInstrInfo.cpp
HSAILIntrinsicInfo.cpp
HSAILISelDAGToDAG.cpp
HSAILISelLowering.cpp
HSAILMachineFunctionInfo.cpp
HSAILMCInstLower.cpp
HSAILModuleInfo.cpp
HSAILParamManager.cpp
HSAILRegisterInfo.cpp
HSAILSection.cpp
HSAILStoreInitializer.cpp
HSAILSubtarget.cpp
HSAILTargetMachine.cpp
HSAILUtilityFunctions.cpp
HSAILOpaqueTypes.cpp
)
if( CMAKE_CL_64 )
# A workaround for a bug in cmake 2.8.3. See PR 8885.
if( CMAKE_VERSION STREQUAL "2.8.3" )
include(CMakeDetermineCompilerId)
endif()
endif()
add_llvm_target(HSAILCodeGen ${sources})
target_link_libraries(LLVMHSAILCodeGen PRIVATE LLVMHSAILUtil)
rafaelUnsubmitted
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No commented out code please.

rafael: No commented out code please.
add_subdirectory(InstPrinter)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

lib/Target/HSAIL/HSAIL.h

  • This file was added.
//===-- HSAIL.h - Top-level interface for HSAIL representation --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_HSAIL_HSAIL_H
#define LLVM_LIB_TARGET_HSAIL_HSAIL_H
#include "llvm/Support/DataTypes.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCInstrDesc.h"
#include "MCTargetDesc/HSAILMCTargetDesc.h"
namespace llvm {
class FunctionPass;
class HSAILTargetMachine;
class LoopPass;
class ModulePass;
class Target;
/// Insert kernel index metadata for device enqueue.
ModulePass *createHSAILInsertKernelIndexMetadataPass();
/// This pass converts a legalized DAG into a HSAIL-specific DAG, ready for
/// instruction scheduling.
FunctionPass *createHSAILISelDag(TargetMachine &TM);
ModulePass *createHSAILAlwaysInlinePass();
extern Target TheHSAIL_32Target, TheHSAIL_64Target;
} // End llvm namespace
namespace llvm {
namespace HSAILAS {
enum AddressSpaces {
MatzeBUnsubmitted
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Better use static const unsigned or enum values so debuggers can pick those constants up as well.

MatzeB: Better use static const unsigned or enum values so debuggers can pick those constants up as…
PRIVATE_ADDRESS = 0,
GLOBAL_ADDRESS = 1,
READONLY_ADDRESS = 2,
GROUP_ADDRESS = 3,
FLAT_ADDRESS = 4,
REGION_ADDRESS = 5,
SPILL_ADDRESS = 6,
KERNARG_ADDRESS = 7,
ARG_ADDRESS = 8,
ADDRESS_NONE = 9
};
}
// Target flags from tablegen
// See HSAILInstFormats.td
namespace HSAILInstrFlags {
enum {
// Instruction kind.
InstAddr = 1 << 3,
InstAtomic = 1 << 4,
InstBasic = 1 << 5,
InstBr = 1 << 6,
InstCmp = 1 << 7,
InstCvt = 1 << 8,
InstImage = 1 << 9,
InstLane = 1 << 10,
rafaelUnsubmitted
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Empty comments?

rafael: Empty comments?
InstMem = 1 << 11,
InstMemFence = 1 << 12,
InstMod = 1 << 13,
InstQueryImage = 1 << 14,
InstQuerySampler = 1 << 15,
InstQueue = 1 << 16,
InstSeg = 1 << 17,
InstSegCvt = 1 << 18,
InstSignal = 1 << 19,
InstSourceType = 1 << 20,
// Others.
IS_CONV = 1 << 23,
IS_IMAGEINST = 1 << 24,
// Default modifier attributes. Used for marking default values of a
// modifier for an instruction to skip printing it.
RoundAttrLo = 1 << 25, // 2 bits
RoundAttrHi = 1 << 26,
RoundAttr = RoundAttrLo | RoundAttrHi,
WidthAttrLo = 1 << 27, // 2 bits
WidthAttrHi = 1 << 28,
WidthAttr = WidthAttrLo | WidthAttrHi,
HasDefaultSegment = 1 << 29,
InstBrigOpcodeLo = UINT64_C(1) << 48,
InstBrigOpcode = UINT64_C(0xffff) << 48
};
}
namespace HSAILWidthAttrFlags {
enum {
rafaelUnsubmitted
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Don't repeat names in comments.

rafael: Don't repeat names in comments.
WidthAttrNone = 0,
WidthAttrAll = 1,
WidthAttrWaveSize = 2,
WidthAttrOne = 3
};
}
/// Enum for memory operand decoding
namespace HSAILADDRESS {
enum { BASE = 0, REG = 1, OFFSET = 2, ADDRESS_NUM_OPS };
}
/// Target architectures to optimize for
enum OptimizeForTargetArch {
GENERIC, ///< No target specific flavor
SI ///< Optimize fot Southern Islands family
};
namespace HSAIL {
enum OperandType {
/// Operand with register or immediate.
OPERAND_REG_IMM = llvm::MCOI::OPERAND_FIRST_TARGET
};
}
}
#define IMAGE_ARG_BIAS (1 << 16)
#endif
MatzeBUnsubmitted
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Could use doxygen comments here:
/// Target architectures ...
enum ... {

GENERIC, ///< No target specific flavor
...
MatzeB: Could use doxygen comments here: /// Target architectures ... enum ... { GENERIC, ///< No…

lib/Target/HSAIL/HSAIL.td

lib/Target/HSAIL/HSAILAlwaysInlinePass.cpp

  • This file was added.
//===-- HSAILAlwaysInlinePass.cpp - Promote Allocas ----------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// This pass marks all internal functions as always_inline and creates
/// duplicates of all other functions a marks the duplicates as always_inline.
//
//===----------------------------------------------------------------------===//
#include "HSAIL.h"
#include "llvm/IR/Module.h"
#include "llvm/Transforms/Utils/Cloning.h"
using namespace llvm;
namespace {
class HSAILAlwaysInline : public ModulePass {
MatzeBUnsubmitted
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Would be nice to name the file like the class declared inside.

MatzeB: Would be nice to name the file like the class declared inside.
static char ID;
rafaelUnsubmitted
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please git-clang-format the patch.

rafael: please git-clang-format the patch.
public:
HSAILAlwaysInline() : ModulePass(ID) {}
bool runOnModule(Module &M) override;
const char *getPassName() const override {
return "HSAIL Always Inline Pass";
}
};
} // End anonymous namespace
char HSAILAlwaysInline::ID = 0;
bool HSAILAlwaysInline::runOnModule(Module &M) {
std::vector<Function *> FuncsToClone;
for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {
Function &F = *I;
if (!F.hasLocalLinkage() && !F.isDeclaration() && !F.use_empty() &&
!F.hasFnAttribute(Attribute::NoInline))
FuncsToClone.push_back(&F);
}
for (Function *F : FuncsToClone) {
ValueToValueMapTy VMap;
Function *NewFunc = CloneFunction(F, VMap, false);
NewFunc->setLinkage(GlobalValue::InternalLinkage);
F->getParent()->getFunctionList().push_back(NewFunc);
F->replaceAllUsesWith(NewFunc);
}
for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {
Function &F = *I;
rafaelUnsubmitted
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range loop?

rafael: range loop?
arsenmAuthorUnsubmitted
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I fixed this in the AMDGPU copy of this pass, so once http://reviews.llvm.org/D11155 is in I'll just remove this file.

arsenm: I fixed this in the AMDGPU copy of this pass, so once http://reviews.llvm.org/D11155 is in I'll…
if (F.hasLocalLinkage() && !F.hasFnAttribute(Attribute::NoInline)) {
F.addFnAttr(Attribute::AlwaysInline);
}
}
return false;
}
ModulePass *llvm::createHSAILAlwaysInlinePass() {
return new HSAILAlwaysInline();
}

lib/Target/HSAIL/HSAILArithmetic.td

lib/Target/HSAIL/HSAILAsmPrinter.h

  • This file was added.
//===-- HSAILAsmPrinter.h - Print HSAIL assembly code -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// \brief HSAIL Assembly printer class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_HSAIL_HSAILASMPRINTER_H
#define LLVM_LIB_TARGET_HSAIL_HSAILASMPRINTER_H
#include "llvm/CodeGen/AsmPrinter.h"
namespace llvm {
class ConstantFP;
class MachineFrameInfo;
template <unsigned> class SmallString;
class HSAILAsmPrinter : public AsmPrinter {
private:
typedef std::pair<uint64_t, const MCExpr *> AddrInit;
StringRef getArgTypeName(Type *Ty, bool Signed = false) const;
void emitFunctionArgument(unsigned ParamIndex, const Argument &Arg,
bool IsKernel, bool IsSExt, raw_ostream &O) const;
rafaelUnsubmitted
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Start functions with lowercase letter when you can (or is this missing an override?)

rafael: Start functions with lowercase letter when you can (or is this missing an override?)
void emitFunctionReturn(Type *Ty, StringRef Name, bool IsKernel, bool IsSExt,
raw_ostream &O) const;
void emitFunctionLabel(const Function &F, raw_ostream &O, bool IsDecl) const;
static char getSymbolPrefixForAddressSpace(unsigned AS);
char getSymbolPrefix(const MCSymbol &S) const;
void printInitVarWithAddressPragma(StringRef VarName, uint64_t Offset,
const MCExpr *Expr, unsigned EltSize,
raw_ostream &O);
void printFloat(uint32_t, raw_ostream &O);
void printDouble(uint64_t, raw_ostream &O);
void printConstantFP(const ConstantFP *CV, raw_ostream &O);
void printScalarConstant(const Constant *CV, SmallVectorImpl<AddrInit> &Addrs,
uint64_t &TotalSizeEmitted, const DataLayout &DL,
raw_ostream &O);
void printGVInitialValue(const GlobalValue &GV, const Constant *CV,
const DataLayout &DL, raw_ostream &O);
public:
explicit HSAILAsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer);
bool doFinalization(Module &M) override;
bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const override { return "HSAIL Assembly Printer"; }
void getHSAILMangledName(SmallString<256> &Out, const GlobalValue *GV) const;
void EmitGlobalVariable(const GlobalVariable *GV) override;
void EmitStartOfAsmFile(Module &) override;
void EmitFunctionHeader() override;
void EmitFunctionEntryLabel() override;
void checkModuleSubtargetExtensions(const Module &M,
bool &IsFullProfile,
bool &IsGCN,
bool &HasImages) const;
static bool isHSAILInstrinsic(StringRef str);
void computeStackUsage(const MachineFrameInfo *MFI,
uint64_t &PrivateSize,
unsigned &PrivateAlign,
uint64_t &SpillSize,
unsigned &SpillAlign) const;
void EmitFunctionBodyStart() override;
void EmitFunctionBodyEnd() override;
void EmitInstruction(const MachineInstr *MI) override;
};
}
#endif

lib/Target/HSAIL/HSAILAsmPrinter.cpp

lib/Target/HSAIL/HSAILAtomics.td

lib/Target/HSAIL/HSAILBrig.h

lib/Target/HSAIL/HSAILBrigDefs.h

lib/Target/HSAIL/HSAILComparisons.td

lib/Target/HSAIL/HSAILControlFlow.td

lib/Target/HSAIL/HSAILConversions.td

lib/Target/HSAIL/HSAILELFTargetObjectFile.h

lib/Target/HSAIL/HSAILELFTargetObjectFile.cpp

lib/Target/HSAIL/HSAILEnums.td

lib/Target/HSAIL/HSAILFrameLowering.h

lib/Target/HSAIL/HSAILFrameLowering.cpp

lib/Target/HSAIL/HSAILFusion.td

lib/Target/HSAIL/HSAILISelDAGToDAG.cpp

  • This file was added.
//=- HSAILISelDAGToDAG.cpp - A DAG pattern matching inst selector for HSAIL -=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines a DAG pattern matching instruction selector for HSAIL,
// converting from a legalized dag to a HSAIL dag.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "hsail-isel"
#include "HSAIL.h"
#include "HSAILBrigDefs.h"
#include "HSAILInstrInfo.h"
#include "HSAILMachineFunctionInfo.h"
#include "HSAILRegisterInfo.h"
#include "HSAILSubtarget.h"
#include "HSAILTargetMachine.h"
#include "HSAILUtilityFunctions.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
// Pattern Matcher Implementation
//===----------------------------------------------------------------------===//
namespace llvm {
void initializeHSAILDAGToDAGISelPass(PassRegistry &);
}
namespace {
//===--------------------------------------------------------------------===//
/// ISel - HSAIL specific code to select HSAIL machine instructions for
/// SelectionDAG operations.
///
class HSAILDAGToDAGISel : public SelectionDAGISel {
/// Subtarget - Keep a pointer to the HSAILSubtarget around so that we can
/// make the right decision when generating code for different targets.
const HSAILSubtarget *Subtarget;
public:
explicit HSAILDAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(TM), Subtarget(nullptr) {}
virtual ~HSAILDAGToDAGISel() {}
const char *getPassName() const override {
return "HSAIL DAG->DAG Instruction Selection";
}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<HSAILSubtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
}
bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
private:
SDNode *Select(SDNode *N) override;
SDNode *SelectINTRINSIC_WO_CHAIN(SDNode *Node);
SDNode *SelectINTRINSIC_W_CHAIN(SDNode *Node);
SDNode *SelectImageIntrinsic(SDNode *Node);
SDNode *SelectActiveLaneMask(SDNode *Node);
// Helper for SelectAddrCommon
// Checks that OR operation is semantically equivalent to ADD
bool IsOREquivalentToADD(SDValue Op) const;
bool SelectAddrCommon(SDValue Addr, SDValue &Base, SDValue &Reg,
int64_t &Offset, MVT ValueType, int Depth) const;
bool SelectAddr(SDValue N, SDValue &Base, SDValue &Reg,
SDValue &Offset) const;
bool SelectLoadAddr(SDNode *ParentLoad, SDValue Addr, SDValue &Base,
SDValue &Reg, SDValue &Offset, SDValue &Segment,
SDValue &Align, SDValue &Type, SDValue &Width,
SDValue &ModifierMask) const;
bool SelectStoreAddr(SDNode *ParentStore, SDValue Addr, SDValue &Base,
SDValue &Reg, SDValue &Offset, SDValue &Segment,
SDValue &Align,
/*SDValue &Equiv,*/
SDValue &Type) const;
bool SelectAtomicAddr(SDNode *ParentLoad, SDValue Addr, SDValue &Segment,
SDValue &Order, SDValue &Scope, SDValue &Equiv,
SDValue &Base, SDValue &Reg, SDValue &Offset) const;
void SelectAddrSpaceCastCommon(const AddrSpaceCastSDNode &ASC,
SDValue &NoNull, SDValue &Ptr,
SDValue &DestType, SDValue &SrcType) const;
SDNode *SelectAddrSpaceCast(AddrSpaceCastSDNode *ASC) const;
SDNode *SelectSetCC(SDNode *SetCC) const;
SDNode *SelectArgLd(MemSDNode *SetCC) const;
SDNode *SelectArgSt(MemSDNode *SetCC) const;
bool SelectGPROrImm(SDValue In, SDValue &Src) const;
bool MemOpHasPtr32(SDNode *N) const;
bool isKernelFunc(void) const;
// Include the pieces autogenerated from the target description.
#include "HSAILGenDAGISel.inc"
};
}
static BrigType getBrigType(MVT::SimpleValueType VT, bool Signed) {
switch (VT) {
case MVT::i32:
return Signed ? BRIG_TYPE_S32 : BRIG_TYPE_U32;
case MVT::f32:
return BRIG_TYPE_F32;
case MVT::i8:
return Signed ? BRIG_TYPE_S8 : BRIG_TYPE_U8;
case MVT::i16:
return Signed ? BRIG_TYPE_S16 : BRIG_TYPE_U16;
case MVT::i64:
return Signed ? BRIG_TYPE_S64 : BRIG_TYPE_U64;
case MVT::f64:
return BRIG_TYPE_F64;
case MVT::i1:
return BRIG_TYPE_B1;
default:
llvm_unreachable("Unhandled type for MVT -> BRIG");
}
}
static BrigType getBrigTypeFromStoreType(MVT::SimpleValueType VT) {
switch (VT) {
case MVT::i32:
return BRIG_TYPE_U32;
case MVT::f32:
return BRIG_TYPE_F32;
case MVT::i8:
return BRIG_TYPE_U8;
case MVT::i16:
return BRIG_TYPE_U16;
case MVT::i64:
return BRIG_TYPE_U64;
case MVT::f64:
return BRIG_TYPE_F64;
default:
llvm_unreachable("Unhandled type for MVT -> BRIG");
}
}
bool HSAILDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
SDNode *Root) const {
return true;
}
bool HSAILDAGToDAGISel::SelectGPROrImm(SDValue In, SDValue &Src) const {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(In)) {
SDLoc SL(In);
Src = CurDAG->getTargetConstant(C->getAPIntValue(), SL, C->getValueType(0));
} else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(In)) {
SDLoc SL(In);
Src = CurDAG->getTargetConstantFP(C->getValueAPF(), SL, C->getValueType(0));
} else
Src = In;
return true;
}
bool HSAILDAGToDAGISel::isKernelFunc() const {
const MachineFunction &MF = CurDAG->getMachineFunction();
return HSAIL::isKernelFunc(MF.getFunction());
}
static unsigned getImageInstr(HSAILIntrinsic::ID intr) {
switch (intr) {
default:
llvm_unreachable("unexpected intrinsinc ID for images");
case HSAILIntrinsic::HSAIL_rd_imgf_1d_f32:
return HSAIL::rd_imgf_1d_f32;
case HSAILIntrinsic::HSAIL_rd_imgf_1d_s32:
return HSAIL::rd_imgf_1d_s32;
case HSAILIntrinsic::HSAIL_rd_imgf_1da_f32:
return HSAIL::rd_imgf_1da_f32;
case HSAILIntrinsic::HSAIL_rd_imgf_1da_s32:
return HSAIL::rd_imgf_1da_s32;
case HSAILIntrinsic::HSAIL_rd_imgf_2d_f32:
return HSAIL::rd_imgf_2d_f32;
case HSAILIntrinsic::HSAIL_rd_imgf_2d_s32:
return HSAIL::rd_imgf_2d_s32;
case HSAILIntrinsic::HSAIL_rd_imgf_2da_f32:
return HSAIL::rd_imgf_2da_f32;
case HSAILIntrinsic::HSAIL_rd_imgf_2da_s32:
return HSAIL::rd_imgf_2da_s32;
case HSAILIntrinsic::HSAIL_rd_imgf_3d_f32:
return HSAIL::rd_imgf_3d_f32;
case HSAILIntrinsic::HSAIL_rd_imgf_3d_s32:
return HSAIL::rd_imgf_3d_s32;
case HSAILIntrinsic::HSAIL_rd_imgi_1d_f32:
return HSAIL::rd_imgi_1d_f32;
case HSAILIntrinsic::HSAIL_rd_imgi_1d_s32:
return HSAIL::rd_imgi_1d_s32;
case HSAILIntrinsic::HSAIL_rd_imgi_1da_f32:
return HSAIL::rd_imgi_1da_f32;
case HSAILIntrinsic::HSAIL_rd_imgi_1da_s32:
return HSAIL::rd_imgi_1da_s32;
case HSAILIntrinsic::HSAIL_rd_imgi_2d_f32:
return HSAIL::rd_imgi_2d_f32;
case HSAILIntrinsic::HSAIL_rd_imgi_2d_s32:
return HSAIL::rd_imgi_2d_s32;
case HSAILIntrinsic::HSAIL_rd_imgi_2da_f32:
return HSAIL::rd_imgi_2da_f32;
case HSAILIntrinsic::HSAIL_rd_imgi_2da_s32:
return HSAIL::rd_imgi_2da_s32;
case HSAILIntrinsic::HSAIL_rd_imgi_3d_f32:
return HSAIL::rd_imgi_3d_f32;
case HSAILIntrinsic::HSAIL_rd_imgi_3d_s32:
return HSAIL::rd_imgi_3d_s32;
case HSAILIntrinsic::HSAIL_rd_imgui_1d_f32:
return HSAIL::rd_imgui_1d_f32;
case HSAILIntrinsic::HSAIL_rd_imgui_1d_s32:
return HSAIL::rd_imgui_1d_s32;
case HSAILIntrinsic::HSAIL_rd_imgui_1da_f32:
return HSAIL::rd_imgui_1da_f32;
case HSAILIntrinsic::HSAIL_rd_imgui_1da_s32:
return HSAIL::rd_imgui_1da_s32;
case HSAILIntrinsic::HSAIL_rd_imgui_2d_f32:
return HSAIL::rd_imgui_2d_f32;
case HSAILIntrinsic::HSAIL_rd_imgui_2d_s32:
return HSAIL::rd_imgui_2d_s32;
case HSAILIntrinsic::HSAIL_rd_imgui_2da_f32:
return HSAIL::rd_imgui_2da_f32;
case HSAILIntrinsic::HSAIL_rd_imgui_2da_s32:
return HSAIL::rd_imgui_2da_s32;
case HSAILIntrinsic::HSAIL_rd_imgui_3d_f32:
return HSAIL::rd_imgui_3d_f32;
case HSAILIntrinsic::HSAIL_rd_imgui_3d_s32:
return HSAIL::rd_imgui_3d_s32;
case HSAILIntrinsic::HSAIL_rd_imgf_2ddepth_f32:
return HSAIL::rd_imgf_2ddepth_f32;
case HSAILIntrinsic::HSAIL_rd_imgf_2ddepth_s32:
return HSAIL::rd_imgf_2ddepth_s32;
case HSAILIntrinsic::HSAIL_rd_imgf_2dadepth_f32:
return HSAIL::rd_imgf_2dadepth_f32;
case HSAILIntrinsic::HSAIL_rd_imgf_2dadepth_s32:
return HSAIL::rd_imgf_2dadepth_s32;
case HSAILIntrinsic::HSAIL_ld_imgf_1d_u32:
return HSAIL::ld_imgf_1d_u32;
case HSAILIntrinsic::HSAIL_ld_imgf_1da_u32:
return HSAIL::ld_imgf_1da_u32;
case HSAILIntrinsic::HSAIL_ld_imgf_1db_u32:
return HSAIL::ld_imgf_1db_u32;
case HSAILIntrinsic::HSAIL_ld_imgf_2d_u32:
return HSAIL::ld_imgf_2d_u32;
case HSAILIntrinsic::HSAIL_ld_imgf_2da_u32:
return HSAIL::ld_imgf_2da_u32;
case HSAILIntrinsic::HSAIL_ld_imgf_3d_u32:
return HSAIL::ld_imgf_3d_u32;
case HSAILIntrinsic::HSAIL_ld_imgi_1d_u32:
return HSAIL::ld_imgi_1d_u32;
case HSAILIntrinsic::HSAIL_ld_imgi_1da_u32:
return HSAIL::ld_imgi_1da_u32;
case HSAILIntrinsic::HSAIL_ld_imgi_1db_u32:
return HSAIL::ld_imgi_1db_u32;
case HSAILIntrinsic::HSAIL_ld_imgi_2d_u32:
return HSAIL::ld_imgi_2d_u32;
case HSAILIntrinsic::HSAIL_ld_imgi_2da_u32:
return HSAIL::ld_imgi_2da_u32;
case HSAILIntrinsic::HSAIL_ld_imgi_3d_u32:
return HSAIL::ld_imgi_3d_u32;
case HSAILIntrinsic::HSAIL_ld_imgui_1d_u32:
return HSAIL::ld_imgui_1d_u32;
case HSAILIntrinsic::HSAIL_ld_imgui_1da_u32:
return HSAIL::ld_imgui_1da_u32;
case HSAILIntrinsic::HSAIL_ld_imgui_1db_u32:
return HSAIL::ld_imgui_1db_u32;
case HSAILIntrinsic::HSAIL_ld_imgui_2d_u32:
return HSAIL::ld_imgui_2d_u32;
case HSAILIntrinsic::HSAIL_ld_imgui_2da_u32:
return HSAIL::ld_imgui_2da_u32;
case HSAILIntrinsic::HSAIL_ld_imgui_3d_u32:
return HSAIL::ld_imgui_3d_u32;
case HSAILIntrinsic::HSAIL_ld_imgf_2ddepth_u32:
return HSAIL::ld_imgf_2ddepth_u32;
case HSAILIntrinsic::HSAIL_ld_imgf_2dadepth_u32:
return HSAIL::ld_imgf_2dadepth_u32;
}
}
SDNode *HSAILDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode *Node) {
unsigned IntID = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
switch (IntID) {
case HSAILIntrinsic::HSAIL_ftz_f32: {
SDLoc SL(Node);
// This is a workaround for not being able to create fpimm in an output
// pattern.
const SDValue Ops[] = {
CurDAG->getTargetConstant(1, SL, MVT::i1), // ftz
CurDAG->getTargetConstant(BRIG_ROUND_FLOAT_DEFAULT, SL, MVT::i32), // round
Node->getOperand(1), // src0
CurDAG->getConstantFP(0.0, SL, MVT::f32), // src1
CurDAG->getTargetConstant(BRIG_TYPE_F32, SL, MVT::i32) // TypeLength
};
return CurDAG->SelectNodeTo(Node, HSAIL::ADD_F32, MVT::f32, Ops);
}
case HSAILIntrinsic::HSAIL_mul_ftz_f32: {
SDLoc SL(Node);
// This is a workaround for not being able to create fpimm in an output
// pattern.
const SDValue Ops[] = {
CurDAG->getTargetConstant(1, SL, MVT::i1), // ftz
CurDAG->getTargetConstant(BRIG_ROUND_FLOAT_DEFAULT, SL, MVT::i32), // round
Node->getOperand(1), // src0
CurDAG->getConstantFP(BitsToFloat(0x3f800000), SL, MVT::f32), // src1
CurDAG->getTargetConstant(BRIG_TYPE_F32, SL, MVT::i32) // TypeLength
};
return CurDAG->SelectNodeTo(Node, HSAIL::MUL_F32, MVT::f32, Ops);
}
default:
return SelectCode(Node);
}
}
SDNode *HSAILDAGToDAGISel::SelectINTRINSIC_W_CHAIN(SDNode *Node) {
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
if (HSAILIntrinsicInfo::isReadImage((HSAILIntrinsic::ID)IntNo) ||
HSAILIntrinsicInfo::isLoadImage((HSAILIntrinsic::ID)IntNo))
return SelectImageIntrinsic(Node);
return SelectCode(Node);
}
SDNode *HSAILDAGToDAGISel::SelectImageIntrinsic(SDNode *Node) {
SDValue Chain = Node->getOperand(0);
SDNode *ResNode;
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
bool hasSampler = false;
if (IntNo == HSAILIntrinsic::HSAIL_rd_imgf_1d_s32) {
SDLoc SL;
const SDValue Ops[] = {
CurDAG->getTargetConstant(1, SL, MVT::i1), // v4
CurDAG->getTargetConstant(BRIG_TYPE_ROIMG, SL, MVT::i32), // imageType
CurDAG->getTargetConstant(BRIG_TYPE_S32, SL, MVT::i32), // coordType
CurDAG->getTargetConstant(BRIG_GEOMETRY_1D, SL, MVT::i32), // geometry
CurDAG->getTargetConstant(0, SL, MVT::i32), // equiv
Node->getOperand(2), // image
Node->getOperand(3), // sampler
Node->getOperand(4), // coordWidth
CurDAG->getTargetConstant(BRIG_TYPE_F32, SL, MVT::i32), // destType
Chain
};
return CurDAG->SelectNodeTo(Node, HSAIL::RDIMAGE, Node->getVTList(), Ops);
}
if (HSAILIntrinsicInfo::isReadImage((HSAILIntrinsic::ID)IntNo)) {
hasSampler = true;
} else if (!HSAILIntrinsicInfo::isLoadImage((HSAILIntrinsic::ID)IntNo)) {
return SelectCode(Node);
}
if (((HSAILIntrinsic::ID)IntNo) ==
(HSAILIntrinsic::HSAIL_rd_imgf_2ddepth_f32) ||
((HSAILIntrinsic::ID)IntNo) ==
(HSAILIntrinsic::HSAIL_rd_imgf_2ddepth_s32) ||
((HSAILIntrinsic::ID)IntNo) ==
(HSAILIntrinsic::HSAIL_ld_imgf_2ddepth_u32) ||
((HSAILIntrinsic::ID)IntNo) ==
(HSAILIntrinsic::HSAIL_rd_imgf_2dadepth_f32) ||
((HSAILIntrinsic::ID)IntNo) ==
(HSAILIntrinsic::HSAIL_rd_imgf_2dadepth_s32) ||
((HSAILIntrinsic::ID)IntNo) ==
(HSAILIntrinsic::HSAIL_ld_imgf_2dadepth_u32)) {
assert(Node->getNumValues() == 2);
} else {
assert(Node->getNumValues() == 5);
}
SmallVector<SDValue, 6> NewOps;
unsigned OpIndex = 2;
SDValue Img = Node->getOperand(OpIndex++);
int ResNo = Img.getResNo();
SDValue ImgHandle = Img.getValue(ResNo);
NewOps.push_back(ImgHandle);
if (hasSampler) {
SDValue Smp = Node->getOperand(OpIndex++);
SDValue SmpHandle = Smp.getValue(Smp.getResNo());
NewOps.push_back(SmpHandle);
}
while (OpIndex < Node->getNumOperands()) {
SDValue Coord = Node->getOperand(OpIndex++);
NewOps.push_back(Coord);
}
NewOps.push_back(Chain);
ResNode = CurDAG->SelectNodeTo(Node, getImageInstr((HSAILIntrinsic::ID)IntNo),
Node->getVTList(), NewOps);
return ResNode;
}
SDNode *HSAILDAGToDAGISel::SelectActiveLaneMask(SDNode *Node) {
SDLoc SL(Node);
SDValue Ops[] = {
Node->getOperand(1), // width
Node->getOperand(2), // src0
CurDAG->getTargetConstant(BRIG_TYPE_B64, SL, MVT::i32), // TypeLength
CurDAG->getTargetConstant(BRIG_TYPE_B1, SL, MVT::i32), // sourceType
Node->getOperand(0) // Chain
};
SelectGPROrImm(Ops[1], Ops[1]);
return CurDAG->SelectNodeTo(Node, HSAIL::ACTIVELANEMASK_V4_B64_B1,
Node->getVTList(), Ops);
}
SDNode *HSAILDAGToDAGISel::Select(SDNode *Node) {
assert(Node);
EVT NVT = Node->getValueType(0);
unsigned Opcode = Node->getOpcode();
SDNode *ResNode;
DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
if (Node->isMachineOpcode()) {
DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
return nullptr; // Already selected.
}
switch (Opcode) {
default:
ResNode = SelectCode(Node);
break;
case ISD::SETCC:
ResNode = SelectSetCC(Node);
break;
case ISD::FrameIndex: {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Node)) {
SDLoc SL(Node);
SDValue Ops[] = {
CurDAG->getTargetConstant(HSAILAS::PRIVATE_ADDRESS, SL, MVT::i32),
CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32),
CurDAG->getRegister(0, NVT),
CurDAG->getTargetConstant(0, SL, NVT),
CurDAG->getTargetConstant(BRIG_TYPE_U32, SL, MVT::i32)
};
ResNode = CurDAG->SelectNodeTo(Node, HSAIL::LDA_U32, NVT, Ops);
} else {
ResNode = Node;
}
break;
}
case ISD::GlobalAddress: {
const GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Node);
const GlobalValue *GV = GSDN->getGlobal();
EVT PtrVT = Node->getValueType(0);
unsigned AS = GSDN->getAddressSpace();
SDLoc SL(Node);
BrigType BT = (PtrVT == MVT::i32) ? BRIG_TYPE_U32 : BRIG_TYPE_U64;
unsigned Opcode = (PtrVT == MVT::i32) ? HSAIL::LDA_U32 : HSAIL::LDA_U64;
const SDValue Ops[] = {
CurDAG->getTargetConstant(AS, SL, MVT::i32),
CurDAG->getTargetGlobalAddress(GV, SL, PtrVT, 0),
CurDAG->getRegister(HSAIL::NoRegister, NVT),
CurDAG->getTargetConstant(GSDN->getOffset(), SL, PtrVT),
CurDAG->getTargetConstant(BT, SL, MVT::i32)
};
ResNode = CurDAG->SelectNodeTo(Node, Opcode, PtrVT, Ops);
break;
}
case ISD::INTRINSIC_WO_CHAIN:
ResNode = SelectINTRINSIC_WO_CHAIN(Node);
break;
case ISD::INTRINSIC_W_CHAIN:
ResNode = SelectINTRINSIC_W_CHAIN(Node);
break;
case ISD::CALLSEQ_START: {
// LLVM 3.6 unable to select start/end of call sequence chained with the
// rest of the arg scope operations due to the WalkChainUsers check which
// reports it may induce a cycle in the graph, so select it manually.
ResNode = CurDAG->SelectNodeTo(Node, HSAIL::ARG_SCOPE_START, MVT::Other,
MVT::Glue,
Node->getOperand(1), // src0
Node->getOperand(0)); // Chain
break;
}
case ISD::CALLSEQ_END: {
const SDValue Ops[] = {
Node->getOperand(1), // src0
Node->getOperand(2), // src1
Node->getOperand(0), // Chain
Node->getOperand(3) // Glue
};
ResNode = CurDAG->SelectNodeTo(Node, HSAIL::ARG_SCOPE_END, MVT::Other,
MVT::Glue, Ops);
break;
}
case HSAILISD::ARG_LD: {
ResNode = SelectArgLd(cast<MemSDNode>(Node));
break;
}
case HSAILISD::ARG_ST: {
ResNode = SelectArgSt(cast<MemSDNode>(Node));
break;
}
case ISD::ADDRSPACECAST: {
ResNode = SelectAddrSpaceCast(cast<AddrSpaceCastSDNode>(Node));
break;
}
case HSAILISD::ACTIVELANEMASK:
return SelectActiveLaneMask(Node);
}
return ResNode;
}
bool HSAILDAGToDAGISel::IsOREquivalentToADD(SDValue Op) const {
assert(Op.getOpcode() == ISD::OR);
SDValue N0 = Op->getOperand(0);
SDValue N1 = Op->getOperand(1);
EVT VT = N0.getValueType();
// Highly inspired by (a|b) case in DAGCombiner::visitADD
if (VT.isInteger() && !VT.isVector()) {
APInt LHSZero, LHSOne;
APInt RHSZero, RHSOne;
CurDAG->computeKnownBits(N0, LHSZero, LHSOne);
if (LHSZero.getBoolValue()) {
CurDAG->computeKnownBits(N1, RHSZero, RHSOne);
// If all possibly-set bits on the LHS are clear on the RHS, return yes.
// If all possibly-set bits on the RHS are clear on the LHS, return yes.
if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
return true;
}
}
// Fallback to the more conservative check
return CurDAG->isBaseWithConstantOffset(Op);
}
/// \brief Return true if the pointer is 32-bit in large and small models
static bool addrSpaceHasPtr32(unsigned AS) {
switch (AS) {
default:
return false;
case HSAILAS::GROUP_ADDRESS:
case HSAILAS::ARG_ADDRESS:
case HSAILAS::PRIVATE_ADDRESS:
case HSAILAS::SPILL_ADDRESS:
return true;
}
}
/// We accept an SDNode to keep things simple in the TD files. The
/// cast to MemSDNode will never assert because this predicate is only
/// used in a pattern fragment that matches load or store nodes.
bool HSAILDAGToDAGISel::MemOpHasPtr32(SDNode *N) const {
return addrSpaceHasPtr32(cast<MemSDNode>(N)->getAddressSpace());
}
bool HSAILDAGToDAGISel::SelectAddrCommon(SDValue Addr, SDValue &Base,
SDValue &Reg, int64_t &Offset,
MVT ValueType, int Depth) const {
tstellarAMDUnsubmitted
Not Done
ReplyInline Actions

Does this function really need to be recursive? it seems more complicated than it needs to be.

tstellarAMD: Does this function really need to be recursive? it seems more complicated than it needs to be.
arsenmAuthorUnsubmitted
Not Done
ReplyInline Actions

This could probably be simplified a lot. The cases for ADD/OR looks unnecessary. It seems to mostly be to workaround the ADD -> OR combine. I don't think LDA needs to be handled here at all. I fixed it so that global addresses are handled during selection, so this shouldn't be seeing the custom node (which doesn't seem to be used anymore)

arsenm: This could probably be simplified a lot. The cases for ADD/OR looks unnecessary. It seems to…
if (Depth > 5)
return false;
SDValue backup_base = Base, backup_reg = Reg;
int64_t backup_offset = Offset;
switch (Addr.getOpcode()) {
case ISD::Constant: {
int64_t new_offset = cast<ConstantSDNode>(Addr)->getSExtValue();
// No 64 bit offsets in 32 bit target
if (Subtarget->isSmallModel() && !isInt<32>(new_offset))
return false;
Offset += new_offset;
return true;
}
case ISD::FrameIndex: {
if (Base.getNode() == 0) {
Base = CurDAG->getTargetFrameIndex(
cast<FrameIndexSDNode>(Addr)->getIndex(), ValueType);
return true;
}
break;
}
case ISD::TargetGlobalAddress:
case ISD::GlobalAddress:
case ISD::GlobalTLSAddress:
case ISD::TargetGlobalTLSAddress: {
if (Base.getNode() == 0) {
Base = CurDAG->getTargetGlobalAddress(
cast<GlobalAddressSDNode>(Addr)->getGlobal(), SDLoc(Addr), ValueType);
int64_t new_offset =
Offset + cast<GlobalAddressSDNode>(Addr)->getOffset();
if (Subtarget->isSmallModel() && !isInt<32>(new_offset))
return false;
Offset += new_offset;
return true;
}
break;
}
case ISD::TargetExternalSymbol: {
if (Base.getNode() == 0) {
Base = Addr;
return true;
}
break;
}
case ISD::OR: // Treat OR as ADD when Op1 & Op2 == 0
if (IsOREquivalentToADD(Addr)) {
bool can_selec_first_op = SelectAddrCommon(Addr.getOperand(0), Base, Reg,
Offset, ValueType, Depth + 1);
if (can_selec_first_op && SelectAddrCommon(Addr.getOperand(1), Base, Reg,
Offset, ValueType, Depth + 1))
return true;
Base = backup_base;
Reg = backup_reg;
Offset = backup_offset;
}
break;
case ISD::ADD: {
bool can_selec_first_op = SelectAddrCommon(Addr.getOperand(0), Base, Reg,
Offset, ValueType, Depth + 1);
if (can_selec_first_op && SelectAddrCommon(Addr.getOperand(1), Base, Reg,
Offset, ValueType, Depth + 1))
return true;
Base = backup_base;
Reg = backup_reg;
Offset = backup_offset;
break;
}
case HSAILISD::LDA: {
if (SelectAddrCommon(Addr.getOperand(1), Base, Reg, Offset, ValueType,
Depth + 1)) {
return true;
}
Base = backup_base;
Reg = backup_reg;
Offset = backup_offset;
break;
}
default:
break;
}
// By default generate address as register
if (Reg.getNode() == 0) {
Reg = Addr;
return true;
}
return false;
}
/// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can
/// match by reference.
///
/// Parent is the parent node of the addr operand that is being matched. It
/// is always a load, store, atomic node, or null. It is only null when
/// checking memory operands for inline asm nodes.
bool HSAILDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Reg,
SDValue &Offset) const {
MVT VT = Addr.getValueType().getSimpleVT();
assert(VT == MVT::i32 || VT == MVT::i64);
int64_t disp = 0;
if (!SelectAddrCommon(Addr, Base, Reg, disp, VT, 0))
return false;
SDLoc SL(Addr);
Offset = CurDAG->getTargetConstant(disp, SL, VT);
if (Base.getNode() == 0)
Base = CurDAG->getRegister(0, VT);
if (Reg.getNode() == 0)
Reg = CurDAG->getRegister(0, VT);
return true;
}
bool HSAILDAGToDAGISel::SelectLoadAddr(SDNode *ParentLoad, SDValue Addr,
SDValue &Base, SDValue &Reg,
SDValue &Offset, SDValue &Segment,
SDValue &Align, SDValue &Type,
SDValue &Width,
SDValue &ModifierMask) const {
const LoadSDNode *Load = cast<LoadSDNode>(ParentLoad);
assert(!Load->isIndexed());
if (!SelectAddr(Addr, Base, Reg, Offset))
return false;
unsigned AS = Load->getAddressSpace();
SDLoc SL(ParentLoad);
MVT MemVT = Load->getMemoryVT().getSimpleVT();
ISD::LoadExtType ExtTy = Load->getExtensionType();
unsigned BrigType = getBrigType(MemVT.SimpleTy, ExtTy == ISD::SEXTLOAD);
Segment = CurDAG->getTargetConstant(AS, SL, MVT::i32);
Align = CurDAG->getTargetConstant(Load->getAlignment(), SL, MVT::i32);
Type = CurDAG->getTargetConstant(BrigType, SL, MVT::i32);
Width = CurDAG->getTargetConstant(BRIG_WIDTH_1, SL, MVT::i32);
// TODO: Set if invariant.
ModifierMask = CurDAG->getTargetConstant(0, SL, MVT::i32);
return true;
}
bool HSAILDAGToDAGISel::SelectStoreAddr(SDNode *ParentStore, SDValue Addr,
SDValue &Base, SDValue &Reg,
SDValue &Offset, SDValue &Segment,
SDValue &Align,
/*SDValue &Equiv,*/
SDValue &Type) const {
const StoreSDNode *Store = cast<StoreSDNode>(ParentStore);
assert(!Store->isIndexed());
if (!SelectAddr(Addr, Base, Reg, Offset))
return false;
unsigned AS = Store->getAddressSpace();
MVT MemVT = Store->getMemoryVT().getSimpleVT();
unsigned BrigType = getBrigTypeFromStoreType(MemVT.SimpleTy);
SDLoc SL(ParentStore);
Segment = CurDAG->getTargetConstant(AS, SL, MVT::i32);
Align = CurDAG->getTargetConstant(Store->getAlignment(), SL, MVT::i32);
// Equiv = CurDAG->getTargetConstant(0, SL, MVT::i32);
Type = CurDAG->getTargetConstant(BrigType, SL, MVT::i32);
return true;
}
static BrigMemoryOrder getBrigMemoryOrder(AtomicOrdering Order) {
switch (Order) {
case Monotonic:
return BRIG_MEMORY_ORDER_RELAXED;
case Acquire:
return BRIG_MEMORY_ORDER_SC_ACQUIRE;
case Release:
return BRIG_MEMORY_ORDER_SC_RELEASE;
case AcquireRelease:
case SequentiallyConsistent:
return BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE;
default:
llvm_unreachable("unhandled memory order");
}
}
static BrigMemoryScope getBrigMemoryScope(SynchronizationScope Scope,
unsigned AS) {
switch (Scope) {
case SingleThread:
return BRIG_MEMORY_SCOPE_WORKITEM;
case CrossThread:
// FIXME: This needs to be fixed when LLVM support other scope values.
switch (AS) {
case HSAILAS::GROUP_ADDRESS:
return BRIG_MEMORY_SCOPE_WORKGROUP;
case HSAILAS::REGION_ADDRESS:
return BRIG_MEMORY_SCOPE_AGENT;
default:
return BRIG_MEMORY_SCOPE_SYSTEM;
}
}
}
bool HSAILDAGToDAGISel::SelectAtomicAddr(SDNode *ParentAtomic, SDValue Addr,
SDValue &Segment, SDValue &Order,
SDValue &Scope, SDValue &Equiv,
SDValue &Base, SDValue &Reg,
SDValue &Offset) const {
if (!SelectAddr(Addr, Base, Reg, Offset))
return false;
const AtomicSDNode *Atomic = cast<AtomicSDNode>(ParentAtomic);
// XXX - What do we do with the failure ordering?
AtomicOrdering SuccOrder = Atomic->getSuccessOrdering();
SynchronizationScope SyncScope = Atomic->getSynchScope();
unsigned AS = Atomic->getAddressSpace();
SDLoc SL(ParentAtomic);
Segment = CurDAG->getTargetConstant(AS, SL, MVT::i32);
Order = CurDAG->getTargetConstant(getBrigMemoryOrder(SuccOrder), SL, MVT::i32);
Scope =
CurDAG->getTargetConstant(getBrigMemoryScope(SyncScope, AS), SL, MVT::i32);
Equiv = CurDAG->getTargetConstant(0, SL, MVT::i32);
return true;
}
void HSAILDAGToDAGISel::SelectAddrSpaceCastCommon(
const AddrSpaceCastSDNode &ASC, SDValue &NoNull, SDValue &Ptr,
SDValue &DestType, SDValue &SrcType) const {
SDLoc SL(&ASC);
SelectGPROrImm(ASC.getOperand(0), Ptr);
NoNull = CurDAG->getTargetConstant(0, SL, MVT::i1);
BrigType DestBT =
getBrigType(ASC.getValueType(0).getSimpleVT().SimpleTy, false);
BrigType SrcBT =
getBrigType(Ptr.getValueType().getSimpleVT().SimpleTy, false);
DestType = CurDAG->getTargetConstant(DestBT, SL, MVT::i32);
SrcType = CurDAG->getTargetConstant(SrcBT, SL, MVT::i32);
}
SDNode *HSAILDAGToDAGISel::SelectAddrSpaceCast(AddrSpaceCastSDNode *ASC) const {
SDValue Cast(ASC, 0);
unsigned DstAS = ASC->getDestAddressSpace();
unsigned SrcAS = ASC->getSrcAddressSpace();
EVT DestVT = ASC->getValueType(0);
EVT SrcVT = ASC->getOperand(0).getValueType();
bool Src32 = (SrcVT == MVT::i32);
bool Dst32 = (DestVT == MVT::i32);
unsigned Opcode;
SDValue Segment, NoNull, Ptr, DestType, SrcType;
SDLoc SL(ASC);
if (SrcAS == HSAILAS::FLAT_ADDRESS) {
if (Src32 && Dst32)
Opcode = HSAIL::FTOS_U32_U32;
else if (Src32 && !Dst32)
llvm_unreachable("Pointer size combination should not happen");
else if (!Src32 && Dst32)
Opcode = HSAIL::FTOS_U32_U64;
else
Opcode = HSAIL::FTOS_U64_U64;
Segment = CurDAG->getTargetConstant(DstAS, SL, MVT::i32);
SelectAddrSpaceCastCommon(*ASC, NoNull, Ptr, DestType, SrcType);
} else if (DstAS == HSAILAS::FLAT_ADDRESS) {
if (Src32 && Dst32)
Opcode = HSAIL::STOF_U32_U32;
else if (Src32 && !Dst32)
Opcode = HSAIL::STOF_U64_U32;
else if (!Src32 && Dst32)
llvm_unreachable("Pointer size combination should not happen");
else
Opcode = HSAIL::STOF_U64_U64;
Segment = CurDAG->getTargetConstant(SrcAS, SL, MVT::i32);
SelectAddrSpaceCastCommon(*ASC, NoNull, Ptr, DestType, SrcType);
} else
return nullptr;
const SDValue Ops[] = {Segment, NoNull, Ptr, DestType, SrcType};
return CurDAG->SelectNodeTo(ASC, Opcode, DestVT, Ops);
}
static BrigCompareOperation getBrigIntCompare(ISD::CondCode CC, bool &Signed) {
switch (CC) {
case ISD::SETUEQ:
Signed = true; // Sign is irrelevant, use to be consistent.
return BRIG_COMPARE_EQ;
case ISD::SETUGT:
return BRIG_COMPARE_GT;
case ISD::SETUGE:
return BRIG_COMPARE_GE;
case ISD::SETULT:
return BRIG_COMPARE_LT;
case ISD::SETULE:
return BRIG_COMPARE_LE;
case ISD::SETUNE:
Signed = true; // Sign is irrelevant, use to be consistent.
return BRIG_COMPARE_NE;
case ISD::SETEQ:
Signed = true;
return BRIG_COMPARE_EQ;
case ISD::SETGT:
Signed = true;
return BRIG_COMPARE_GT;
case ISD::SETGE:
Signed = true;
return BRIG_COMPARE_GE;
case ISD::SETLT:
Signed = true;
return BRIG_COMPARE_LT;
case ISD::SETLE:
Signed = true;
return BRIG_COMPARE_LE;
case ISD::SETNE:
Signed = true;
return BRIG_COMPARE_NE;
default:
llvm_unreachable("unhandled cond code");
}
}
static BrigCompareOperation getBrigFPCompare(ISD::CondCode CC) {
switch (CC) {
case ISD::SETOEQ:
case ISD::SETEQ:
return BRIG_COMPARE_EQ;
case ISD::SETOGT:
case ISD::SETGT:
return BRIG_COMPARE_GT;
case ISD::SETOGE:
case ISD::SETGE:
return BRIG_COMPARE_GE;
case ISD::SETOLT:
case ISD::SETLT:
return BRIG_COMPARE_LT;
case ISD::SETOLE:
case ISD::SETLE:
return BRIG_COMPARE_LE;
case ISD::SETONE:
case ISD::SETNE:
return BRIG_COMPARE_NE;
case ISD::SETO:
return BRIG_COMPARE_NUM;
case ISD::SETUO:
return BRIG_COMPARE_NAN;
case ISD::SETUEQ:
return BRIG_COMPARE_EQU;
case ISD::SETUGT:
return BRIG_COMPARE_GTU;
case ISD::SETUGE:
return BRIG_COMPARE_GEU;
case ISD::SETULT:
return BRIG_COMPARE_LTU;
case ISD::SETULE:
return BRIG_COMPARE_LEU;
case ISD::SETUNE:
return BRIG_COMPARE_NEU;
default:
llvm_unreachable("unhandled cond code");
}
}
static unsigned getCmpOpcode(BrigType SrcBT) {
switch (SrcBT) {
case BRIG_TYPE_B1:
return HSAIL::CMP_B1_B1;
case BRIG_TYPE_S32:
return HSAIL::CMP_B1_S32;
case BRIG_TYPE_U32:
return HSAIL::CMP_B1_U32;
case BRIG_TYPE_S64:
return HSAIL::CMP_B1_S64;
case BRIG_TYPE_U64:
return HSAIL::CMP_B1_U64;
case BRIG_TYPE_F32:
return HSAIL::CMP_B1_F32;
case BRIG_TYPE_F64:
return HSAIL::CMP_B1_F64;
default:
llvm_unreachable("Compare of type not supported");
}
}
SDNode *HSAILDAGToDAGISel::SelectSetCC(SDNode *SetCC) const {
SDValue LHS, RHS;
if (!SelectGPROrImm(SetCC->getOperand(0), LHS))
return nullptr;
if (!SelectGPROrImm(SetCC->getOperand(1), RHS))
return nullptr;
MVT VT = LHS.getValueType().getSimpleVT();
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
bool Signed = false;
BrigCompareOperation BrigCmp;
if (VT.isFloatingPoint())
BrigCmp = getBrigFPCompare(CC);
else
BrigCmp = getBrigIntCompare(CC, Signed);
SDLoc SL(SetCC);
SDValue CmpOp = CurDAG->getTargetConstant(BrigCmp, SL, MVT::i32);
SDValue FTZ = CurDAG->getTargetConstant(VT == MVT::f32, SL, MVT::i1);
// TODO: Should be able to fold conversions into this instead.
SDValue DestType = CurDAG->getTargetConstant(BRIG_TYPE_B1, SL, MVT::i32);
BrigType SrcBT = getBrigType(VT.SimpleTy, Signed);
SDValue SrcType = CurDAG->getTargetConstant(SrcBT, SL, MVT::i32);
const SDValue Ops[] = {CmpOp, FTZ, LHS, RHS, DestType, SrcType};
return CurDAG->SelectNodeTo(SetCC, getCmpOpcode(SrcBT), MVT::i1, Ops);
}
static unsigned getLoadBrigOpcode(BrigType BT) {
switch (BT) {
case BRIG_TYPE_U32:
return HSAIL::LD_U32;
case BRIG_TYPE_S32:
return HSAIL::LD_S32;
case BRIG_TYPE_F32:
return HSAIL::LD_F32;
case BRIG_TYPE_U64:
return HSAIL::LD_U64;
case BRIG_TYPE_S64:
return HSAIL::LD_S64;
case BRIG_TYPE_F64:
return HSAIL::LD_F64;
case BRIG_TYPE_U8:
return HSAIL::LD_U8;
case BRIG_TYPE_S8:
return HSAIL::LD_S8;
case BRIG_TYPE_U16:
return HSAIL::LD_U16;
case BRIG_TYPE_S16:
return HSAIL::LD_S16;
default:
llvm_unreachable("Unhandled load type");
}
}
static unsigned getRArgLoadBrigOpcode(BrigType BT) {
switch (BT) {
case BRIG_TYPE_U32:
return HSAIL::RARG_LD_U32;
case BRIG_TYPE_S32:
return HSAIL::RARG_LD_S32;
case BRIG_TYPE_F32:
return HSAIL::RARG_LD_F32;
case BRIG_TYPE_U64:
return HSAIL::RARG_LD_U64;
case BRIG_TYPE_S64:
return HSAIL::RARG_LD_S64;
case BRIG_TYPE_F64:
return HSAIL::RARG_LD_F64;
case BRIG_TYPE_U8:
return HSAIL::RARG_LD_U8;
case BRIG_TYPE_S8:
return HSAIL::RARG_LD_S8;
case BRIG_TYPE_U16:
return HSAIL::RARG_LD_U16;
case BRIG_TYPE_S16:
return HSAIL::RARG_LD_S16;
default:
llvm_unreachable("Unhandled load type");
}
}
static unsigned getStoreBrigOpcode(BrigType BT) {
switch (BT) {
case BRIG_TYPE_U32:
return HSAIL::ST_U32;
case BRIG_TYPE_F32:
return HSAIL::ST_F32;
case BRIG_TYPE_U64:
return HSAIL::ST_U64;
case BRIG_TYPE_F64:
return HSAIL::ST_F64;
case BRIG_TYPE_U8:
return HSAIL::ST_U8;
case BRIG_TYPE_U16:
return HSAIL::ST_U16;
default:
llvm_unreachable("Unhandled load type");
}
}
SDNode *HSAILDAGToDAGISel::SelectArgLd(MemSDNode *Node) const {
bool IsRetLd = Node->getConstantOperandVal(3);
bool IsSext = Node->getConstantOperandVal(4);
SDValue Base, Reg, Offset;
if (!SelectAddr(Node->getOperand(1), Base, Reg, Offset))
return nullptr;
MVT MemVT = Node->getMemoryVT().getSimpleVT();
BrigType BT = getBrigType(MemVT.SimpleTy, IsSext);
SDLoc SL(Node);
SDValue Ops[10] = {
Base, Reg, Offset,
CurDAG->getTargetConstant(BT, SL, MVT::i32), // TypeLength
CurDAG->getTargetConstant(Node->getAddressSpace(), SL, MVT::i32), // segment
CurDAG->getTargetConstant(Node->getAlignment(), SL, MVT::i32), // align
Node->getOperand(2), // width
CurDAG->getTargetConstant(0, SL, MVT::i1), // mask
Node->getOperand(0), // Chain
SDValue()
};
ArrayRef<SDValue> OpsArr = makeArrayRef(Ops);
if (Node->getNumOperands() == 6)
Ops[9] = Node->getOperand(5);
else
OpsArr = OpsArr.drop_back(1);
unsigned Opcode = IsRetLd ? getRArgLoadBrigOpcode(BT) : getLoadBrigOpcode(BT);
return CurDAG->SelectNodeTo(Node, Opcode, Node->getVTList(), OpsArr);
}
SDNode *HSAILDAGToDAGISel::SelectArgSt(MemSDNode *Node) const {
SDValue Base, Reg, Offset;
if (!SelectAddr(Node->getOperand(2), Base, Reg, Offset))
return nullptr;
SDLoc SL(Node);
MVT MemVT = Node->getMemoryVT().getSimpleVT();
BrigType BT = getBrigType(MemVT.SimpleTy, false);
SDValue Ops[9] = {
Node->getOperand(1),
Base, Reg, Offset,
CurDAG->getTargetConstant(BT, SL, MVT::i32), // TypeLength
CurDAG->getTargetConstant(Node->getAddressSpace(), SL, MVT::i32), // segment
CurDAG->getTargetConstant(Node->getAlignment(), SL, MVT::i32), // align
Node->getOperand(0), // Chain
SDValue()
};
ArrayRef<SDValue> OpsArr = makeArrayRef(Ops);
if (Node->getNumOperands() == 4)
Ops[8] = Node->getOperand(3);
else
OpsArr = OpsArr.drop_back(1);
return CurDAG->SelectNodeTo(Node, getStoreBrigOpcode(BT), Node->getVTList(),
OpsArr);
}
FunctionPass *llvm::createHSAILISelDag(TargetMachine &TM) {
return new HSAILDAGToDAGISel(TM);
}

lib/Target/HSAIL/HSAILISelLowering.h

lib/Target/HSAIL/HSAILISelLowering.cpp

lib/Target/HSAIL/HSAILImages.td

lib/Target/HSAIL/HSAILInstrFormats.td

lib/Target/HSAIL/HSAILInstrInfo.h

lib/Target/HSAIL/HSAILInstrInfo.cpp

lib/Target/HSAIL/HSAILInstrInfo.td

lib/Target/HSAIL/HSAILInstructions.td

lib/Target/HSAIL/HSAILIntrinsicInfo.h

lib/Target/HSAIL/HSAILIntrinsicInfo.cpp

lib/Target/HSAIL/HSAILIntrinsics.td

lib/Target/HSAIL/HSAILKernel.h

lib/Target/HSAIL/HSAILLoadStore.td

lib/Target/HSAIL/HSAILMCInstLower.h

lib/Target/HSAIL/HSAILMCInstLower.cpp

lib/Target/HSAIL/HSAILMachineFunctionInfo.h

lib/Target/HSAIL/HSAILMachineFunctionInfo.cpp

lib/Target/HSAIL/HSAILMetadata.hpp

lib/Target/HSAIL/HSAILModuleInfo.h

lib/Target/HSAIL/HSAILModuleInfo.cpp

lib/Target/HSAIL/HSAILNodes.td

lib/Target/HSAIL/HSAILOpaqueTypes.h

lib/Target/HSAIL/HSAILOpaqueTypes.cpp

lib/Target/HSAIL/HSAILOperands.td

lib/Target/HSAIL/HSAILParamManager.h

lib/Target/HSAIL/HSAILParamManager.cpp

lib/Target/HSAIL/HSAILPatterns.td

lib/Target/HSAIL/HSAILProfiles.td

lib/Target/HSAIL/HSAILRegisterInfo.h

lib/Target/HSAIL/HSAILRegisterInfo.cpp

lib/Target/HSAIL/HSAILRegisterInfo.td

lib/Target/HSAIL/HSAILSection.h

lib/Target/HSAIL/HSAILSection.cpp

  • This file was added.
//===- HSAILSection.cpp -----------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "HSAILSection.h"
using namespace llvm;
void HSAILSection::PrintSwitchToSection(const MCAsmInfo &MAI,
raw_ostream &OS,
rafaelUnsubmitted
Not Done
ReplyInline Actions

Just don't create sections instead of having empty section switching.

rafael: Just don't create sections instead of having empty section switching.
arsenmAuthorUnsubmitted
Not Done
ReplyInline Actions

These sections are created by the generic code in the AsmPrinter. This is exactly what NVPTX does currently to fix this.

arsenm: These sections are created by the generic code in the AsmPrinter. This is exactly what NVPTX…
const MCExpr *Subsection) const {
// Do nothing. There are no sections
}
HSAILSection::~HSAILSection() {
}

lib/Target/HSAIL/HSAILSpecial.td

lib/Target/HSAIL/HSAILStoreInitializer.h

lib/Target/HSAIL/HSAILStoreInitializer.cpp

lib/Target/HSAIL/HSAILSubtarget.h

lib/Target/HSAIL/HSAILSubtarget.cpp

lib/Target/HSAIL/HSAILTargetMachine.h

lib/Target/HSAIL/HSAILTargetMachine.cpp

lib/Target/HSAIL/HSAILUtil/CMakeLists.txt

lib/Target/HSAIL/HSAILUtil/HSAILUtil.cpp

lib/Target/HSAIL/HSAILUtilityFunctions.h

lib/Target/HSAIL/HSAILUtilityFunctions.cpp

lib/Target/HSAIL/InstPrinter/CMakeLists.txt

lib/Target/HSAIL/InstPrinter/HSAILInstPrinter.h

lib/Target/HSAIL/InstPrinter/HSAILInstPrinter.cpp

lib/Target/HSAIL/InstPrinter/LLVMBuild.txt

lib/Target/HSAIL/LLVMBuild.txt

lib/Target/HSAIL/MCTargetDesc/BRIGDwarfStreamer.h

lib/Target/HSAIL/MCTargetDesc/BRIGDwarfStreamer.cpp

lib/Target/HSAIL/MCTargetDesc/CMakeLists.txt

lib/Target/HSAIL/MCTargetDesc/HSAILAsmBackend.h

lib/Target/HSAIL/MCTargetDesc/HSAILAsmBackend.cpp

lib/Target/HSAIL/MCTargetDesc/HSAILELFObjectWriter.h

lib/Target/HSAIL/MCTargetDesc/HSAILELFObjectWriter.cpp

lib/Target/HSAIL/MCTargetDesc/HSAILMCAsmInfo.h

lib/Target/HSAIL/MCTargetDesc/HSAILMCAsmInfo.cpp

lib/Target/HSAIL/MCTargetDesc/HSAILMCCodeEmitter.h

lib/Target/HSAIL/MCTargetDesc/HSAILMCCodeEmitter.cpp

lib/Target/HSAIL/MCTargetDesc/HSAILMCTargetDesc.h

lib/Target/HSAIL/MCTargetDesc/HSAILMCTargetDesc.cpp

lib/Target/HSAIL/MCTargetDesc/HSAILTargetStreamer.h

lib/Target/HSAIL/MCTargetDesc/HSAILTargetStreamer.cpp

lib/Target/HSAIL/MCTargetDesc/LLVMBuild.txt

lib/Target/HSAIL/MCTargetDesc/RawVectorOstream.h

  • This file was added.
//===-- RawVectorOstream.h --------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// Interface for RawVectorOstream which is used for capturing DWARF data from
/// MC
/// layer
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_HSAIL_MCTARGETDESC_RAWVECTOROSTREAM_H
#define LLVM_LIB_TARGET_HSAIL_MCTARGETDESC_RAWVECTOROSTREAM_H
#include "llvm/Support/raw_ostream.h"
#include <vector>
namespace llvm {
class RawVectorOstream : public raw_pwrite_stream {
tstellarAMDUnsubmitted
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Is there a reason this isn't in common code?

tstellarAMD: Is there a reason this isn't in common code?
arsenmAuthorUnsubmitted
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I think I can completely remove this for now since it should only be used by the BRIGAsmPrinter

arsenm: I think I can completely remove this for now since it should only be used by the BRIGAsmPrinter
static const size_t AllocationChunk = 1024;
std::vector<char> Data;
std::vector<char>::size_type Position;
raw_pwrite_stream *Other;
void write_impl(const char *Ptr, size_t Size) override;
void pwrite_impl(const char *Ptr, size_t Size, uint64_t Offset) override;
uint64_t current_pos() const override;
public:
explicit RawVectorOstream(raw_pwrite_stream *other);
virtual ~RawVectorOstream();
StringRef getData() const {
return StringRef(Data.data(), Data.size());
}
void releaseStream();
// Other stream is the stream that is used to forward all data written to the
// instance of RawVectorOstream. If other stream is NULL then RawVectorOstream
// does not forward captured data to any other stream, it just stores captured
// data in the internal memory buffer.
raw_ostream *getOtherStream() {
return Other;
}
void setOtherStream(raw_pwrite_stream *Other);
};
}
#endif

lib/Target/HSAIL/MCTargetDesc/RawVectorOstream.cpp

lib/Target/HSAIL/TargetInfo/CMakeLists.txt

lib/Target/HSAIL/TargetInfo/HSAILTargetInfo.cpp

lib/Target/HSAIL/TargetInfo/LLVMBuild.txt

lib/Target/LLVMBuild.txt

test/CodeGen/HSAIL/128bit-kernel-args.ll

  • This file was added.
; RUN: llc -march=hsail < %s | FileCheck -check-prefix=HSAIL -check-prefix=FUNC %s
MatzeBUnsubmitted
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Many of the tests define new prefixes instead of just using "CHECK" should be unnecessary if you just test for 1 variant anyway.

MatzeB: Many of the tests define new prefixes instead of just using "CHECK" should be unnecessary if…
arsenmAuthorUnsubmitted
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People have expressed regret as having a default of CHECK for this before. The idea is someday it might be useful to add an HSAIL64 or something like that someday.

arsenm: People have expressed regret as having a default of CHECK for this before. The idea is someday…
; FUNC-LABEL: {{^}}prog function &v4i32_kernel_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: st_global
; HSAIL-DAG: st_global
; HSAIL-DAG: st_global
; HSAIL-DAG: st_global
; HSAIL: ret;
define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
entry:
store <4 x i32> %in, <4 x i32> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}prog function &v4f32_kernel_args
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: ld_arg
; HSAIL-DAG: st_global
; HSAIL-DAG: st_global
; HSAIL-DAG: st_global
; HSAIL-DAG: st_global
; HSAIL: ret;
define void @v4f32_kernel_args(<4 x float> addrspace(1)* %out, <4 x float> %in) {
entry:
store <4 x float> %in, <4 x float> addrspace(1)* %out
ret void
}

test/CodeGen/HSAIL/32-bit-local-address-space.ll

test/CodeGen/HSAIL/64bit-kernel-args.ll

test/CodeGen/HSAIL/abs.ll

test/CodeGen/HSAIL/activelanecount.ll

test/CodeGen/HSAIL/activelaneid.ll

test/CodeGen/HSAIL/activelanemask.ll

test/CodeGen/HSAIL/activelanepermute.ll

test/CodeGen/HSAIL/add.ll

test/CodeGen/HSAIL/addressing-modes.ll

test/CodeGen/HSAIL/addrspacecast.ll

test/CodeGen/HSAIL/and1.ll

test/CodeGen/HSAIL/anonymous-gv-names.ll

test/CodeGen/HSAIL/anonymous-parameters.ll

test/CodeGen/HSAIL/anyext.ll

test/CodeGen/HSAIL/atomic_cmp_swap_group.ll

test/CodeGen/HSAIL/basic-branch.ll

test/CodeGen/HSAIL/basic-loop.ll

test/CodeGen/HSAIL/bitalign_opt.ll

test/CodeGen/HSAIL/bitcast.ll

test/CodeGen/HSAIL/bitextract_opt.ll

test/CodeGen/HSAIL/bitselect_opt.ll

test/CodeGen/HSAIL/broken-chain-retval.ll

test/CodeGen/HSAIL/build_vector.ll

test/CodeGen/HSAIL/call.ll

test/CodeGen/HSAIL/conversion_intrinsics.ll

test/CodeGen/HSAIL/conversion_patterns.ll

test/CodeGen/HSAIL/copy-illegal-type.ll

test/CodeGen/HSAIL/ctlz.ll

test/CodeGen/HSAIL/ctlz_zero_undef.ll

test/CodeGen/HSAIL/ctpop.ll

test/CodeGen/HSAIL/cttz.ll

test/CodeGen/HSAIL/cttz_zero_undef.ll

test/CodeGen/HSAIL/cvt_f32_ubyte.ll

test/CodeGen/HSAIL/dagcombiner-bug-illegal-vec4-int-to-fp.ll

test/CodeGen/HSAIL/ds-negative-offset-addressing-mode-loop.ll

test/CodeGen/HSAIL/empty-function.ll

test/CodeGen/HSAIL/empty-functions.ll

test/CodeGen/HSAIL/ext-args.ll

test/CodeGen/HSAIL/extension-features.ll

test/CodeGen/HSAIL/extract_vector_elt_i16.ll

test/CodeGen/HSAIL/fabs.ll

test/CodeGen/HSAIL/fadd.ll

test/CodeGen/HSAIL/fceil.ll

test/CodeGen/HSAIL/fcmp-cnd.ll

test/CodeGen/HSAIL/fcmp-cnde-int-args.ll

test/CodeGen/HSAIL/fcmp.ll

test/CodeGen/HSAIL/fconst64.ll

test/CodeGen/HSAIL/fcopysign.ll

test/CodeGen/HSAIL/fdiv.ll

test/CodeGen/HSAIL/ffloor.ll

test/CodeGen/HSAIL/flat-atomics.ll

test/CodeGen/HSAIL/fma.ll

test/CodeGen/HSAIL/fmaxnum.ll

test/CodeGen/HSAIL/fminnum.ll

test/CodeGen/HSAIL/fmuladd.ll

test/CodeGen/HSAIL/fneg.ll

test/CodeGen/HSAIL/fp64_to_sint.ll

test/CodeGen/HSAIL/fp_to_sint.ll

test/CodeGen/HSAIL/fp_to_uint.ll

test/CodeGen/HSAIL/fpext.ll

test/CodeGen/HSAIL/fptrunc.ll

test/CodeGen/HSAIL/fsub.ll

test/CodeGen/HSAIL/ftrunc.ll

test/CodeGen/HSAIL/function-args.ll

test/CodeGen/HSAIL/generic-address-bug9899.ll

test/CodeGen/HSAIL/global-atomics.ll

test/CodeGen/HSAIL/global-i1.ll

test/CodeGen/HSAIL/global-variable-alias.ll

test/CodeGen/HSAIL/group-atomics.ll

test/CodeGen/HSAIL/gv-const-addrspace.ll

test/CodeGen/HSAIL/gv-global-addrspace.ll

test/CodeGen/HSAIL/gv-group-addrspace.ll

test/CodeGen/HSAIL/gv-symbol-initializer.ll

test/CodeGen/HSAIL/hypen-in-func-name.ll

test/CodeGen/HSAIL/i1-argument-ext.ll

test/CodeGen/HSAIL/i1-argument.ll

test/CodeGen/HSAIL/i8-to-double-to-float.ll

test/CodeGen/HSAIL/icmp-select-sete-reverse-args.ll

test/CodeGen/HSAIL/icmp64.ll

test/CodeGen/HSAIL/imm.ll

test/CodeGen/HSAIL/indent-call.ll

test/CodeGen/HSAIL/ineg.ll

test/CodeGen/HSAIL/infinite-loop.ll

test/CodeGen/HSAIL/int32to64.ll

test/CodeGen/HSAIL/kernarg-align.ll

test/CodeGen/HSAIL/kernel-args.ll

test/CodeGen/HSAIL/linkage-types.ll

test/CodeGen/HSAIL/lit.local.cfg

test/CodeGen/HSAIL/llvm.hsail.barrier.ll

test/CodeGen/HSAIL/llvm.hsail.bitalign.ll

test/CodeGen/HSAIL/llvm.hsail.bitmask.ll

test/CodeGen/HSAIL/llvm.hsail.bitrev.ll

test/CodeGen/HSAIL/llvm.hsail.bitselect.ll

test/CodeGen/HSAIL/llvm.hsail.bytealign.ll

test/CodeGen/HSAIL/llvm.hsail.clock.ll

test/CodeGen/HSAIL/llvm.hsail.cuid.ll

test/CodeGen/HSAIL/llvm.hsail.currentworkgroupsize.ll

test/CodeGen/HSAIL/llvm.hsail.currentworkitemflatid.ll

test/CodeGen/HSAIL/llvm.hsail.dim.ll

test/CodeGen/HSAIL/llvm.hsail.fadd.ll

test/CodeGen/HSAIL/llvm.hsail.fdiv.ll

test/CodeGen/HSAIL/llvm.hsail.fmul.ll

test/CodeGen/HSAIL/llvm.hsail.fsqrt.ll

test/CodeGen/HSAIL/llvm.hsail.fsub.ll

test/CodeGen/HSAIL/llvm.hsail.gcn.bfm.ll

test/CodeGen/HSAIL/llvm.hsail.gcn.mqsad.ll

test/CodeGen/HSAIL/llvm.hsail.gcn.msad.ll

test/CodeGen/HSAIL/llvm.hsail.gcn.qsad.ll

test/CodeGen/HSAIL/llvm.hsail.gcn.sadd.ll

test/CodeGen/HSAIL/llvm.hsail.gcn.sadw.ll

test/CodeGen/HSAIL/llvm.hsail.gridgroups.ll

test/CodeGen/HSAIL/llvm.hsail.gridsize.ll

test/CodeGen/HSAIL/llvm.hsail.groupbaseptr.ll

test/CodeGen/HSAIL/llvm.hsail.imagefence.ll

test/CodeGen/HSAIL/llvm.hsail.kernargbaseptr.ll

test/CodeGen/HSAIL/llvm.hsail.laneid.ll

test/CodeGen/HSAIL/llvm.hsail.lastbit.ll

test/CodeGen/HSAIL/llvm.hsail.lerp.ll

test/CodeGen/HSAIL/llvm.hsail.maxcuid.ll

test/CodeGen/HSAIL/llvm.hsail.maxwaveid.ll

test/CodeGen/HSAIL/llvm.hsail.memfence.ll

test/CodeGen/HSAIL/llvm.hsail.ncos.ll

test/CodeGen/HSAIL/llvm.hsail.nexp2.ll

test/CodeGen/HSAIL/llvm.hsail.nfma.ll

test/CodeGen/HSAIL/llvm.hsail.nlog2.ll

test/CodeGen/HSAIL/llvm.hsail.nrcp.ll

test/CodeGen/HSAIL/llvm.hsail.nrsqrt.ll

test/CodeGen/HSAIL/llvm.hsail.nsin.ll

test/CodeGen/HSAIL/llvm.hsail.nsqrt.ll

test/CodeGen/HSAIL/llvm.hsail.packcvt.ll

test/CodeGen/HSAIL/llvm.hsail.packetid.ll

test/CodeGen/HSAIL/llvm.hsail.sad.u32.u16x2.ll

test/CodeGen/HSAIL/llvm.hsail.sad.u32.u32.ll

test/CodeGen/HSAIL/llvm.hsail.sad.u32.u8x4.ll

test/CodeGen/HSAIL/llvm.hsail.sadhi.ll

test/CodeGen/HSAIL/llvm.hsail.sbitextract.ll

test/CodeGen/HSAIL/llvm.hsail.sbitinsert.ll

test/CodeGen/HSAIL/llvm.hsail.segmentp.ll

test/CodeGen/HSAIL/llvm.hsail.sfirstbit.ll

test/CodeGen/HSAIL/llvm.hsail.smad24.ll

test/CodeGen/HSAIL/llvm.hsail.smul24.ll

test/CodeGen/HSAIL/llvm.hsail.ubitextract.ll

test/CodeGen/HSAIL/llvm.hsail.ubitinsert.ll

test/CodeGen/HSAIL/llvm.hsail.ufirstbit.ll

test/CodeGen/HSAIL/llvm.hsail.umad24.ll

test/CodeGen/HSAIL/llvm.hsail.umul24.ll

test/CodeGen/HSAIL/llvm.hsail.unpackcvt.ll

test/CodeGen/HSAIL/llvm.hsail.wavebarrier.ll

test/CodeGen/HSAIL/llvm.hsail.waveid.ll

test/CodeGen/HSAIL/llvm.hsail.workgroupid.ll

test/CodeGen/HSAIL/llvm.hsail.workgroupsize.ll

test/CodeGen/HSAIL/llvm.hsail.workitemabsid.ll

test/CodeGen/HSAIL/llvm.hsail.workitemflatabsid.ll

test/CodeGen/HSAIL/llvm.hsail.workitemflatid.ll

test/CodeGen/HSAIL/llvm.hsail.workitemid.ll

test/CodeGen/HSAIL/llvm.HSAIL.class.ll

test/CodeGen/HSAIL/llvm.HSAIL.div.ll

test/CodeGen/HSAIL/llvm.HSAIL.fmax3.ll

test/CodeGen/HSAIL/llvm.HSAIL.fmed3.ll

test/CodeGen/HSAIL/llvm.HSAIL.fmin3.ll

test/CodeGen/HSAIL/llvm.HSAIL.fract.ll

test/CodeGen/HSAIL/llvm.HSAIL.ftz.ll

test/CodeGen/HSAIL/llvm.HSAIL.gcn.atomic.append.ll

test/CodeGen/HSAIL/llvm.HSAIL.gcn.atomic.consume.ll

test/CodeGen/HSAIL/llvm.HSAIL.gcn.fldexp.ll

test/CodeGen/HSAIL/llvm.HSAIL.imax3.ll

test/CodeGen/HSAIL/llvm.HSAIL.imed3.ll

test/CodeGen/HSAIL/llvm.HSAIL.imin3.ll

test/CodeGen/HSAIL/llvm.HSAIL.ld.kernarg.ll

test/CodeGen/HSAIL/llvm.HSAIL.mad.ll

test/CodeGen/HSAIL/llvm.HSAIL.max.ll

test/CodeGen/HSAIL/llvm.HSAIL.min.ll

test/CodeGen/HSAIL/llvm.HSAIL.mul.ftz.ll

test/CodeGen/HSAIL/llvm.HSAIL.nullptr.ll

test/CodeGen/HSAIL/llvm.HSAIL.sqrt.ll

test/CodeGen/HSAIL/llvm.HSAIL.umax3.ll

test/CodeGen/HSAIL/llvm.HSAIL.umed3.ll

test/CodeGen/HSAIL/llvm.HSAIL.umin3.ll

test/CodeGen/HSAIL/llvm.rint.ll

test/CodeGen/HSAIL/load-i1.ll

test/CodeGen/HSAIL/load.ll

test/CodeGen/HSAIL/local-memory.ll

test/CodeGen/HSAIL/max.ll

test/CodeGen/HSAIL/min.ll

test/CodeGen/HSAIL/module-statement.ll

test/CodeGen/HSAIL/mul.ll

test/CodeGen/HSAIL/mulhs.ll

test/CodeGen/HSAIL/mulhu.ll

test/CodeGen/HSAIL/noinline.ll

test/CodeGen/HSAIL/or.ll

test/CodeGen/HSAIL/pack_opt.ll

test/CodeGen/HSAIL/private-memory.ll

test/CodeGen/HSAIL/ptrtoint-constantexpr-initializer-broken.ll

test/CodeGen/HSAIL/ptrtoint-constantexpr-initializer32.ll

test/CodeGen/HSAIL/ptrtoint-constantexpr-initializer64.ll

test/CodeGen/HSAIL/reg-coalescer-assert.ll

test/CodeGen/HSAIL/return-value.ll

test/CodeGen/HSAIL/reverse-branch-condition.ll

test/CodeGen/HSAIL/rotl.ll

test/CodeGen/HSAIL/rotr.ll

test/CodeGen/HSAIL/rsqrt.ll

test/CodeGen/HSAIL/same-reg-vect.ll

test/CodeGen/HSAIL/sdiv.ll

test/CodeGen/HSAIL/select-i1.ll

test/CodeGen/HSAIL/selectcc-cnd.ll

test/CodeGen/HSAIL/selectcc-cnde-int.ll

test/CodeGen/HSAIL/setcc-i1-assert.ll

test/CodeGen/HSAIL/setcc.ll

test/CodeGen/HSAIL/shift64.ll

test/CodeGen/HSAIL/sint_to_fp.ll

test/CodeGen/HSAIL/spill-cond-reg-with-scavenging.ll

test/CodeGen/HSAIL/spill-cond-reg.ll

test/CodeGen/HSAIL/spill.ll

test/CodeGen/HSAIL/sra.ll

test/CodeGen/HSAIL/srem.ll

test/CodeGen/HSAIL/srl.ll

test/CodeGen/HSAIL/stimm.ll

test/CodeGen/HSAIL/store.ll

test/CodeGen/HSAIL/sub.ll

test/CodeGen/HSAIL/trunc-store-i1.ll

test/CodeGen/HSAIL/trunc.ll

test/CodeGen/HSAIL/uint_to_fp.ll

test/CodeGen/HSAIL/unbound-label-exception.ll

test/CodeGen/HSAIL/urem.ll

test/CodeGen/HSAIL/v1i64-kernel-arg.ll

test/CodeGen/HSAIL/v_cndmask.ll

test/CodeGen/HSAIL/vselect64.ll

test/CodeGen/HSAIL/work-item-intrinsics.ll

test/CodeGen/HSAIL/xor.ll

test/CodeGen/HSAIL/zero_extend.ll