[AVR] Only support sp, r0 and r1 in llvm.read_register

[aykevl]

Summary

Most other registers are allocatable and therefore cannot be used.

This issue was flagged by the machine verifier, because reading other registers is considered reading from an undefined register.

While working on this, I noticed that writing the stack pointer produced invalid code. But I figured that is a different issue (and I'm not sure whether it happens in practice).

[aykevl]

• fix lint warnings

[benshi001]

there is a lint warning.

[aykevl]

• fix lint warning

llvm/lib/Target/AVR/AVRISelLowering.cpp

 }
 
 Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                               const MachineFunction &MF) const {
   Register Reg;
 
   if (VT == LLT::scalar(8)) {
     Reg = StringSwitch<unsigned>(RegName)
-      .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
-      .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
-      .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
-      .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
-      .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
-      .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
-      .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
-      .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
-      .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
-      .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
-      .Case("r30", AVR::R30).Case("r31", AVR::R31)
-      .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
+              .Case("r0", AVR::R0)
+              .Case("r1", AVR::R1)
               .Default(0);
   } else {
     Reg = StringSwitch<unsigned>(RegName)
-      .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
-      .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
-      .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
-      .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
-      .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
-      .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
-      .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
-      .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
-      .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
+              .Case("r0", AVR::R1R0)
+              .Case("sp", AVR::SP)
               .Default(0);
   }
 
   if (Reg)
     return Reg;
 
-  report_fatal_error("Invalid register name global variable");
+  report_fatal_error(
+      Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
 }
 
 } // end of namespace llvm

llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll

+; RUN: not --crash llc -O0 < %s -march=avr 2>&1 | FileCheck %s
+
+define void @foo() {
+entry:
+; CHECK: Invalid register name "r28".
+  %val1 = call i8 @llvm.read_register.i8(metadata !0)
+  ret void
+}
+
+declare i8 @llvm.read_register.i8(metadata)
+
+!0 = !{!"r28"}

llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll

+; RUN: llc -O0 < %s -march=avr | FileCheck %s
+
+; CHECK-LABEL: read_sp:
+; CHECK: in r24, 61
+; CHECK: in r25, 62
+define i16 @read_sp() {
+entry:
+  %sp = call i16 @llvm.read_register.i16(metadata !0)
+  ret i16 %sp
+}
+
+; CHECK-LABEL: read_r0:
+; CHECK: mov r24, r0
+define i8 @read_r0() {
+entry:
+  %r0 = call i8 @llvm.read_register.i8(metadata !1)
+  ret i8 %r0
+}
+
+; CHECK-LABEL: read_r1:
+; CHECK: mov r24, r1
+define i8 @read_r1() {
+entry:
+  %r1 = call i8 @llvm.read_register.i8(metadata !2)
+  ret i8 %r1
+}
+
+; CHECK-LABEL: read_r1r0:
+; CHECK: mov r24, r0
+; CHECK: mov r25, r1
+define i16 @read_r1r0() {
+entry:
+  %r1r0 = call i16 @llvm.read_register.i16(metadata !1)
+  ret i16 %r1r0
+}
+
+declare i16 @llvm.read_register.i16(metadata)
+declare i8 @llvm.read_register.i8(metadata)
+
+!0 = !{!"sp"}
+!1 = !{!"r0"}
+!2 = !{!"r1"}

llvm/test/CodeGen/AVR/intrinsics/read_register.ll

-; RUN: llc -O0 < %s -march=avr | FileCheck %s
-
-; CHECK-LABEL: foo
-define void @foo() {
-entry:
-  %val1 = call i16 @llvm.read_register.i16(metadata !0)
-  %val2 = call i16 @llvm.read_register.i16(metadata !1)
-  %val3 = call i8 @llvm.read_register.i8(metadata !2)
-  ret void
-}
-
-declare i8 @llvm.read_register.i8(metadata)
-declare i16 @llvm.read_register.i16(metadata)
-
-!0 = !{!"r28"}
-!1 = !{!"Z"}
-!2 = !{!"r0"}