[mips] [IAS] Add partial support for the ULHU pseudo-instruction.

[tomatabacu]

Summary

This only adds support for ULHU of an immediate address with/without a source register.
It does not include support for ULHU of the address of a symbol.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2191–2192

Nit: We're going to end up writing this a lot. It would be good to factor it out.

2208–2209

For '.set noat' mode we currently give up here before discovering whether we need AT or not.

2215

What happens if OffsetValue is -32769? OffsetValue+1 will fit but we still need AT for OffsetValue

2230–2242

Shouldn't endianness have some effect on the expansion?

2231–2247

Nit: There's some repetition in the ternary operators. Could you factor out the repeated ones into variables?

2297

I'm not sure why this is needed.

[tomatabacu]

Addressed review comments.
Moved generation of (D)ADDu locally in order to closer match GAS' output.
Added .set nomacro warning and test.
Reformatted mips-expansions.s.
Removed some generation checks to fix mips-expansions-bad.s issues caused by rebase.
Rebased.

[tomatabacu]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2191–2192

Done in rL237780.

2208–2209

We always need AT for ULHU, as it is always used as the source register for one of the LBu's.
I added a code comment with this explanation.

2215

Fixed and added as test case in mips-expansions.s.
Also added a test case for the inverse case, when OffsetValue fits but OffsetValue+1 doesn't (OffsetValue is 32767).

2230–2242

Yes, it should. Fixed and added checks for both endian in mips-expansions.s.

2231–2247

Done.

2297

Because otherwise we would always generate ADDu, and GAS generates a DADDu for MIPS64.
The reason why it's in this patch is because this is where we have a concrete test case for it.

[tomatabacu]

Rebased.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2208–2209

Ah yes, it looked like one path didn't use it but that's not the case.

2231

Nit: I believe Fst should be First and Snd should be Second. Likewise below

FWIW, I'd usually spell them 'TmpReg1' and 'TmpReg2'. There's often little description you can give to scratch registers.

2297

Hmm.. This patch uses loadImmediate() is to load an offset into a register. In this context, we don't want to test for 64-bit GPR's but rather for 64-bit pointers (see MipsABIInfo::GetPtrAddiuOp()). However, loadImmediate() is also used for the 'li' instruction where we do want the test to be for 64-bit GPR's.

You'll need to separate the two contexts somehow. I think line 2197 ought to be:

if (loadImmediate(OffsetValue, ATReg, SrcReg, ABI.ArePtrs64bit(), IDLoc,
                  Instructions))

and the Is32bitImm argument to loadImmediate() needs to determine whether you get ADDu or DADDu

[tomatabacu]

Addressed review comments (one of them resulted in D10568).
Added a code comment with an example of why we add the SrcReg locally.
Fixed mistake in test/MC/Mips/set-nomacro.s caused by a previous rebase.

[dsanders]

I agree we've covered all the comments. LGTM

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2224–2226

I found this clarification a bit confusing at first. It might be better to write out the instructions.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

class MipsAsmParser : public MCTargetAsmParser {
 
   MCSubtargetInfo &STI;
   MipsABIInfo ABI;
   SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions;
   MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
                        // nullptr, which indicates that no function is currently
                        // selected. This usually happens after an '.end func'
                        // directive.
+  bool IsLittleEndian;
 
   // Print a warning along with its fix-it message at the given range.
   void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg,
                              SMRange Range, bool ShowColors = true);
 
 #define GET_ASSEMBLER_HEADER
 #include "MipsGenAsmMatcher.inc"
 
#include "MipsGenAsmMatcher.inc"
 
   void expandMemInst(MCInst &Inst, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions, bool isLoad,
                      bool isImmOpnd);
 
   bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandUlhu(MCInst &Inst, SMLoc IDLoc,
+                  SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   SmallVectorImpl<MCInst> &Instructions);
 
   bool reportParseError(Twine ErrorMsg);
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
AssemblerOptions.push_back(
                      make_unique<MipsAssemblerOptions>(getAvailableFeatures()));
 
     getTargetStreamer().updateABIInfo(*this);
 
     if (!isABI_O32() && !useOddSPReg() != 0)
       report_fatal_error("-mno-odd-spreg requires the O32 ABI");
 
     CurrentFn = nullptr;
+
+    Triple TheTriple(sti.getTargetTriple());
+    if ((TheTriple.getArch() == Triple::mips) ||
+        (TheTriple.getArch() == Triple::mips64))
+      IsLittleEndian = false;
+    else
+      IsLittleEndian = true;
   }
 
   /// True if all of $fcc0 - $fcc7 exist for the current ISA.
   bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
 
   bool isGP64bit() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
   bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit; }
   const MipsABIInfo &getABI() const { return ABI; }
#undef GET_OPERAND_DIAGNOSTIC_TYPES
   bool useSoftFloat() const {
     return (STI.getFeatureBits() & Mips::FeatureSoftFloat);
   }
 
   /// Warn if RegIndex is the same as the current AT.
   void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
 
   void warnIfNoMacro(SMLoc Loc);
+
+  bool isLittle() const { return IsLittleEndian; }
 };
 }
 
 namespace {
 
 /// MipsOperand - Instances of this class represent a parsed Mips machine
 /// instruction.
 class MipsOperand : public MCParsedAsmOperand {
bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::LoadImm64:
   case Mips::LoadAddrImm32:
   case Mips::LoadAddrReg32:
   case Mips::B_MM_Pseudo:
   case Mips::LWM_MM:
   case Mips::SWM_MM:
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
+  case Mips::Ulhu:
     return true;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::B_MM_Pseudo:
     return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);
   case Mips::SWM_MM:
   case Mips::LWM_MM:
     return expandLoadStoreMultiple(Inst, IDLoc, Instructions);
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
     return expandJalWithRegs(Inst, IDLoc, Instructions);
+  case Mips::Ulhu:
+    return expandUlhu(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <unsigned ShiftAmount>
 void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
     // It can be implemented as SWM16 or LWM16 instruction.
     NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
 
   Inst.setOpcode(NewOpcode);
   Instructions.push_back(Inst);
   return false;
 }
 
+bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc,
+                               SmallVectorImpl<MCInst> &Instructions) {
+  if (hasMips32r6() || hasMips64r6()) {
+    Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
+    return false;
+  }
+
+  warnIfNoMacro(IDLoc);
+
+  const MCOperand &DstRegOp = Inst.getOperand(0);
+  assert(DstRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &SrcRegOp = Inst.getOperand(1);
+  assert(SrcRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &OffsetImmOp = Inst.getOperand(2);
+  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
+
+  unsigned DstReg = DstRegOp.getReg();
+  unsigned SrcReg = SrcRegOp.getReg();
+  int64_t OffsetValue = OffsetImmOp.getImm();
+
+  // NOTE: We always need AT for ULHU, as it is always used as the source
+  // register for one of the LBu's.
+  unsigned ATReg = getATReg(IDLoc);
+  if (!ATReg)
+    return true;
+
+  // When the value of offset+1 does not fit in 16 bits, we have to load the
+  // offset in AT, (D)ADDu the original source register (if there was one), and
+  // then use AT as the source register for the 2 generated LBu's.
+  bool LoadedOffsetInAT = false;
+  if (!isInt<16>(OffsetValue + 1) || !isInt<16>(OffsetValue)) {
+    LoadedOffsetInAT = true;
+
+    if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !isGP64bit(), IDLoc,
+                      Instructions))
+      return true;
+
+    // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate()
+    // because it will make our output more similar to GAS'.
+    // NOTE: If there is no source register specified in the ULHU, the parser
+    // will interpret it as $0.
+    if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
+      createAddu(ATReg, ATReg, SrcReg, Instructions);
+  }
+
+  unsigned FstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg;
+  unsigned SndLbuDstReg = LoadedOffsetInAT ? ATReg : DstReg;
+  unsigned LbuSrcReg = LoadedOffsetInAT ? ATReg : SrcReg;
+
+  int64_t FstLbuOffset = 0, SndLbuOffset = 0;
+  if (isLittle()) {
+    FstLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1);
+    SndLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue;
+  } else {
+    FstLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue;
+    SndLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1);
+  }
+
+  unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg;
+
+  MCInst TmpInst;
+  TmpInst.setOpcode(Mips::LBu);
+  TmpInst.addOperand(MCOperand::createReg(FstLbuDstReg));
+  TmpInst.addOperand(MCOperand::createReg(LbuSrcReg));
+  TmpInst.addOperand(MCOperand::createImm(FstLbuOffset));
+  Instructions.push_back(TmpInst);
+
+  TmpInst.clear();
+  TmpInst.setOpcode(Mips::LBu);
+  TmpInst.addOperand(MCOperand::createReg(SndLbuDstReg));
+  TmpInst.addOperand(MCOperand::createReg(LbuSrcReg));
+  TmpInst.addOperand(MCOperand::createImm(SndLbuOffset));
+  Instructions.push_back(TmpInst);
+
+  TmpInst.clear();
+  TmpInst.setOpcode(Mips::SLL);
+  TmpInst.addOperand(MCOperand::createReg(SllReg));
+  TmpInst.addOperand(MCOperand::createReg(SllReg));
+  TmpInst.addOperand(MCOperand::createImm(8));
+  Instructions.push_back(TmpInst);
+
+  TmpInst.clear();
+  TmpInst.setOpcode(Mips::OR);
+  TmpInst.addOperand(MCOperand::createReg(DstReg));
+  TmpInst.addOperand(MCOperand::createReg(DstReg));
+  TmpInst.addOperand(MCOperand::createReg(ATReg));
+  Instructions.push_back(TmpInst);
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   MCInst NopInst;
   if (hasShortDelaySlot) {
     NopInst.setOpcode(Mips::MOVE16_MM);
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
   } else {
     NopInst.setOpcode(Mips::SLL);
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::createImm(0));
   }
   Instructions.push_back(NopInst);
 }
 
 void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
                                unsigned TrgReg,
                                SmallVectorImpl<MCInst> &Instructions) {
   MCInst AdduInst;
-  AdduInst.setOpcode(Mips::ADDu);
+  AdduInst.setOpcode(isGP64bit() ? Mips::DADDu : Mips::ADDu);
   AdduInst.addOperand(MCOperand::createReg(DstReg));
   AdduInst.addOperand(MCOperand::createReg(SrcReg));
   AdduInst.addOperand(MCOperand::createReg(TrgReg));
   Instructions.push_back(AdduInst);
 }
 
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // As described by the Mips32r2 spec, the registers Rd and Rs for

lib/Target/Mips/MipsInstrInfo.td

MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
                      !strconcat(instr_asm, "\t$rt, $imm32")> ;
 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
 
 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
                       "jal\t$rd, $rs"> ;
 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
                       "jal\t$rs"> ;
 
+def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
+                             "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
 // Load/store pattern templates.
 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
   MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
 

test/MC/Mips/mips-expansions-bad.s

# RUN:   FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY
   # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
   # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
   la $5, 0x100000000($6)
   # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
   # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
   la $5, symbol
   # N64-ONLY: :[[@LINE-1]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol
   # N32-ONLY-NOT: :[[@LINE-2]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol
-  # 64-BIT: lui $5, %hi(symbol)
-  # 64-BIT: ori $5, $5, %lo(symbol)
   dli $5, 1
   # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
+
+  .set mips32r6
+  ulhu $5, 0
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+  .set mips32
+  ulhu $5, 1
+  # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+  .set mips64r6
+  ulhu $5, 2
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6

test/MC/Mips/mips-expansions.s

-# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
+# RUN:   FileCheck %s --check-prefix=CHECK-LE
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \
+# RUN:   FileCheck %s --check-prefix=CHECK-BE
 # Check that the assembler can handle the documented syntax
 # for macro instructions
 #------------------------------------------------------------------------------
 # Load immediate instructions
 #------------------------------------------------------------------------------
-# CHECK:     ori     $5, $zero, 123   # encoding: [0x7b,0x00,0x05,0x34]
-# CHECK:     addiu   $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24]
-# CHECK:     lui     $7, 1            # encoding: [0x01,0x00,0x07,0x3c]
-# CHECK:     ori     $7, $7, 2        # encoding: [0x02,0x00,0xe7,0x34]
-# CHECK:     addiu   $8, $zero, -8    # encoding: [0xf8,0xff,0x08,0x24]
-# CHECK:     lui     $9, 1            # encoding: [0x01,0x00,0x09,0x3c]
-# CHECK-NOT: ori $9, $9, 0            # encoding: [0x00,0x00,0x29,0x35]
-# CHECK:     lui     $10, 65519       # encoding: [0xef,0xff,0x0a,0x3c]
-# CHECK:     ori     $10, $10, 61423  # encoding: [0xef,0xef,0x4a,0x35]
-
-# CHECK: ori     $4, $zero, 20       # encoding: [0x14,0x00,0x04,0x34]
-# CHECK: lui     $7, 1               # encoding: [0x01,0x00,0x07,0x3c]
-# CHECK: ori     $7, $7, 2           # encoding: [0x02,0x00,0xe7,0x34]
-# CHECK: ori     $4, $5, 20          # encoding: [0x14,0x00,0xa4,0x34]
-# CHECK: lui     $7, 1               # encoding: [0x01,0x00,0x07,0x3c]
-# CHECK: ori     $7, $7, 2           # encoding: [0x02,0x00,0xe7,0x34]
-# CHECK: addu    $7, $7, $8          # encoding: [0x21,0x38,0xe8,0x00]
-# CHECK: lui     $8, %hi(symbol)     # encoding: [A,A,0x08,0x3c]
-# CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
-# CHECK: ori     $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35]
-# CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
-# CHECK: lui     $10, %hi(symbol)        # encoding: [A,A,0x0a,0x3c]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
-# CHECK: addu    $10, $10, $4            # encoding: [0x21,0x50,0x44,0x01]
-# CHECK: lw      $10, %lo(symbol)($10)   # encoding: [A,A,0x4a,0x8d]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
-# CHECK: lui     $1, %hi(symbol)         # encoding: [A,A,0x01,0x3c]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
-# CHECK: addu    $1, $1, $9              # encoding: [0x21,0x08,0x29,0x00]
-# CHECK: sw      $10, %lo(symbol)($1)    # encoding: [A,A,0x2a,0xac]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
-# CHECK: lui     $10, 10                 # encoding: [0x0a,0x00,0x0a,0x3c]
-# CHECK: addu    $10, $10, $4            # encoding: [0x21,0x50,0x44,0x01]
-# CHECK: lw      $10, 123($10)           # encoding: [0x7b,0x00,0x4a,0x8d]
-# CHECK: lui     $1, 2                   # encoding: [0x02,0x00,0x01,0x3c]
-# CHECK: addu    $1, $1, $9              # encoding: [0x21,0x08,0x29,0x00]
-# CHECK: sw      $10, 57920($1)          # encoding: [0x40,0xe2,0x2a,0xac]
-
-# CHECK:     lui     $8, %hi(symbol)     # encoding: [A,A,0x08,0x3c]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
-# CHECK-NOT: move    $8, $8              # encoding: [0x21,0x40,0x00,0x01]
-# CHECK:     lw      $8, %lo(symbol)($8) # encoding: [A,A,0x08,0x8d]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
-# CHECK:     lui     $1, %hi(symbol)     # encoding: [A,A,0x01,0x3c]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
-# CHECK-NOT: move    $1, $1              # encoding: [0x21,0x08,0x20,0x00]
-# CHECK:     sw      $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac]
-# CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
-
-# CHECK: lui     $1, %hi(symbol)
-# CHECK: ldc1    $f0, %lo(symbol)($1)
-# CHECK: lui     $1, %hi(symbol)
-# CHECK: sdc1    $f0, %lo(symbol)($1)
+# CHECK-LE:     ori     $5, $zero, 123   # encoding: [0x7b,0x00,0x05,0x34]
+# CHECK-LE:     addiu   $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24]
+# CHECK-LE:     lui     $7, 1            # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK-LE:     ori     $7, $7, 2        # encoding: [0x02,0x00,0xe7,0x34]
+# CHECK-LE:     addiu   $8, $zero, -8    # encoding: [0xf8,0xff,0x08,0x24]
+# CHECK-LE:     lui     $9, 1            # encoding: [0x01,0x00,0x09,0x3c]
+# CHECK-LE-NOT: ori $9, $9, 0            # encoding: [0x00,0x00,0x29,0x35]
+# CHECK-LE:     lui     $10, 65519       # encoding: [0xef,0xff,0x0a,0x3c]
+# CHECK-LE:     ori     $10, $10, 61423  # encoding: [0xef,0xef,0x4a,0x35]
+
+# CHECK-LE: ori     $4, $zero, 20           # encoding: [0x14,0x00,0x04,0x34]
+# CHECK-LE: lui     $7, 1                   # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK-LE: ori     $7, $7, 2               # encoding: [0x02,0x00,0xe7,0x34]
+# CHECK-LE: ori     $4, $5, 20              # encoding: [0x14,0x00,0xa4,0x34]
+# CHECK-LE: lui     $7, 1                   # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK-LE: ori     $7, $7, 2               # encoding: [0x02,0x00,0xe7,0x34]
+# CHECK-LE: addu    $7, $7, $8              # encoding: [0x21,0x38,0xe8,0x00]
+# CHECK-LE: lui     $8, %hi(symbol)         # encoding: [A,A,0x08,0x3c]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK-LE: ori     $8, $8, %lo(symbol)     # encoding: [A,A,0x08,0x35]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK-LE: lui     $10, %hi(symbol)        # encoding: [A,A,0x0a,0x3c]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK-LE: addu    $10, $10, $4            # encoding: [0x21,0x50,0x44,0x01]
+# CHECK-LE: lw      $10, %lo(symbol)($10)   # encoding: [A,A,0x4a,0x8d]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK-LE: lui     $1, %hi(symbol)         # encoding: [A,A,0x01,0x3c]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK-LE: addu    $1, $1, $9              # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: sw      $10, %lo(symbol)($1)    # encoding: [A,A,0x2a,0xac]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK-LE: lui     $10, 10                 # encoding: [0x0a,0x00,0x0a,0x3c]
+# CHECK-LE: addu    $10, $10, $4            # encoding: [0x21,0x50,0x44,0x01]
+# CHECK-LE: lw      $10, 123($10)           # encoding: [0x7b,0x00,0x4a,0x8d]
+# CHECK-LE: lui     $1, 2                   # encoding: [0x02,0x00,0x01,0x3c]
+# CHECK-LE: addu    $1, $1, $9              # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: sw      $10, 57920($1)          # encoding: [0x40,0xe2,0x2a,0xac]
+
+# CHECK-LE:     lui     $8, %hi(symbol)     # encoding: [A,A,0x08,0x3c]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK-LE-NOT: move    $8, $8              # encoding: [0x21,0x40,0x00,0x01]
+# CHECK-LE:     lw      $8, %lo(symbol)($8) # encoding: [A,A,0x08,0x8d]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK-LE:     lui     $1, %hi(symbol)     # encoding: [A,A,0x01,0x3c]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK-LE-NOT: move    $1, $1              # encoding: [0x21,0x08,0x20,0x00]
+# CHECK-LE:     sw      $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac]
+# CHECK-LE:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+
+# CHECK-LE: lui     $1, %hi(symbol)
+# CHECK-LE: ldc1    $f0, %lo(symbol)($1)
+# CHECK-LE: lui     $1, %hi(symbol)
+# CHECK-LE: sdc1    $f0, %lo(symbol)($1)
+
+# CHECK-BE: lbu  $1, 0($zero)      # encoding: [0x90,0x01,0x00,0x00]
+# CHECK-BE: lbu  $8, 1($zero)      # encoding: [0x90,0x08,0x00,0x01]
+# CHECK-BE: sll  $1, $1, 8         # encoding: [0x00,0x01,0x0a,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lbu  $1, 2($zero)      # encoding: [0x90,0x01,0x00,0x02]
+# CHECK-BE: lbu  $8, 3($zero)      # encoding: [0x90,0x08,0x00,0x03]
+# CHECK-BE: sll  $1, $1, 8         # encoding: [0x00,0x01,0x0a,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lbu  $1, -32768($zero) # encoding: [0x90,0x01,0x80,0x00]
+# CHECK-BE: lbu  $8, -32767($zero) # encoding: [0x90,0x08,0x80,0x01]
+# CHECK-BE: sll  $1, $1, 8         # encoding: [0x00,0x01,0x0a,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: ori  $1, $1, 34952     # encoding: [0x34,0x21,0x88,0x88]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lui  $1, 65535         # encoding: [0x3c,0x01,0xff,0xff]
+# CHECK-BE: ori  $1, $1, 32767     # encoding: [0x34,0x21,0x7f,0xff]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: ori  $1, $zero, 32767  # encoding: [0x34,0x01,0x7f,0xff]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+
+# CHECK-BE: lbu  $1, 0($9)         # encoding: [0x91,0x21,0x00,0x00]
+# CHECK-BE: lbu  $8, 1($9)         # encoding: [0x91,0x28,0x00,0x01]
+# CHECK-BE: sll  $1, $1, 8         # encoding: [0x00,0x01,0x0a,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lbu  $1, 2($9)         # encoding: [0x91,0x21,0x00,0x02]
+# CHECK-BE: lbu  $8, 3($9)         # encoding: [0x91,0x28,0x00,0x03]
+# CHECK-BE: sll  $1, $1, 8         # encoding: [0x00,0x01,0x0a,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lbu  $1, -32768($9)    # encoding: [0x91,0x21,0x80,0x00]
+# CHECK-BE: lbu  $8, -32767($9)    # encoding: [0x91,0x28,0x80,0x01]
+# CHECK-BE: sll  $1, $1, 8         # encoding: [0x00,0x01,0x0a,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: ori  $1, $1, 34952     # encoding: [0x34,0x21,0x88,0x88]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: lui  $1, 65535         # encoding: [0x3c,0x01,0xff,0xff]
+# CHECK-BE: ori  $1, $1, 32767     # encoding: [0x34,0x21,0x7f,0xff]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+# CHECK-BE: ori  $1, $zero, 32767  # encoding: [0x34,0x01,0x7f,0xff]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lbu  $8, 0($1)         # encoding: [0x90,0x28,0x00,0x00]
+# CHECK-BE: lbu  $1, 1($1)         # encoding: [0x90,0x21,0x00,0x01]
+# CHECK-BE: sll  $8, $8, 8         # encoding: [0x00,0x08,0x42,0x00]
+# CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
+
+# CHECK-LE: lbu  $1, 1($zero)      # encoding: [0x01,0x00,0x01,0x90]
+# CHECK-LE: lbu  $8, 0($zero)      # encoding: [0x00,0x00,0x08,0x90]
+# CHECK-LE: sll  $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lbu  $1, 3($zero)      # encoding: [0x03,0x00,0x01,0x90]
+# CHECK-LE: lbu  $8, 2($zero)      # encoding: [0x02,0x00,0x08,0x90]
+# CHECK-LE: sll  $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: ori  $1, $zero, 32768  # encoding: [0x00,0x80,0x01,0x34]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lbu  $1, -32767($zero) # encoding: [0x01,0x80,0x01,0x90]
+# CHECK-LE: lbu  $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x90]
+# CHECK-LE: sll  $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 34952     # encoding: [0x88,0x88,0x21,0x34]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lui  $1, 65535         # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 32767     # encoding: [0xff,0x7f,0x21,0x34]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: ori  $1, $zero, 32767  # encoding: [0xff,0x7f,0x01,0x34]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+
+# CHECK-LE: lbu  $1, 1($9)         # encoding: [0x01,0x00,0x21,0x91]
+# CHECK-LE: lbu  $8, 0($9)         # encoding: [0x00,0x00,0x28,0x91]
+# CHECK-LE: sll  $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lbu  $1, 3($9)         # encoding: [0x03,0x00,0x21,0x91]
+# CHECK-LE: lbu  $8, 2($9)         # encoding: [0x02,0x00,0x28,0x91]
+# CHECK-LE: sll  $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: ori  $1, $zero, 32768  # encoding: [0x00,0x80,0x01,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lbu  $1, -32767($9)    # encoding: [0x01,0x80,0x21,0x91]
+# CHECK-LE: lbu  $8, -32768($9)    # encoding: [0x00,0x80,0x28,0x91]
+# CHECK-LE: sll  $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 34952     # encoding: [0x88,0x88,0x21,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: lui  $1, 65535         # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 32767     # encoding: [0xff,0x7f,0x21,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK-LE: ori  $1, $zero, 32767  # encoding: [0xff,0x7f,0x01,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
+# CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
+# CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
 
     li $5,123
     li $6,-2345
     li $7,65538
     li $8, ~7
     li $9, 0x10000
     li $10, ~(0x101010)
 
# CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
     lw  $t2, 655483($a0)
     sw  $t2, 123456($t1)
 
     lw  $8, symbol
     sw  $8, symbol
 
     ldc1 $f0, symbol
     sdc1 $f0, symbol
+
+    ulhu $8, 0
+    ulhu $8, 2
+    ulhu $8, 0x8000
+    ulhu $8, -0x8000
+    ulhu $8, 0x10000
+    ulhu $8, 0x18888
+    ulhu $8, -32769
+    ulhu $8, 32767
+
+    ulhu $8, 0($9)
+    ulhu $8, 2($9)
+    ulhu $8, 0x8000($9)
+    ulhu $8, -0x8000($9)
+    ulhu $8, 0x10000($9)
+    ulhu $8, 0x18888($9)
+    ulhu $8, -32769($9)
+    ulhu $8, 32767($9)

test/MC/Mips/mips64-expansions.s

# CHECK-NOT: dsll
   dli $10, ~(0x202020)
 # CHECK: lui $10, 65503        # encoding: [0xdf,0xff,0x0a,0x3c]
 # CHECK: ori $10, $10, 57311   # encoding: [0xdf,0xdf,0x4a,0x35]
 # CHECK-NOT: dsll
 
   dli $9, 0x80000000
 # CHECK: ori  $9, $zero, 32768 # encoding: [0x00,0x80,0x09,0x34]
 # CHECK: dsll $9, $9, 16       # encoding: [0x38,0x4c,0x09,0x00]
+
+# Test ulhu with 64-bit immediate addresses.
+
+  ulhu $8, 0x100010001
+# CHECK: lui  $1, 1            # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lbu  $8, 1($1)        # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu  $1, 0($1)        # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, 0x1000100010001
+# CHECK: lui  $1, 1            # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lbu  $8, 1($1)        # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu  $1, 0($1)        # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x100010001
+# CHECK: lui  $1, 65535        # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535    # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lbu  $8, 1($1)        # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu  $1, 0($1)        # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x1000100010001
+# CHECK: lui  $1, 65534        # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535    # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lbu  $8, 1($1)        # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu  $1, 0($1)        # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+# Test ulhu with source register and 64-bit immediate offset.
+
+  ulhu $8, 0x100010001($9)
+# CHECK: lui   $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 1($1)       # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu   $1, 0($1)       # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, 0x1000100010001($9)
+# CHECK: lui   $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 1($1)       # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu   $1, 0($1)       # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x100010001($9)
+# CHECK: lui   $1, 65535       # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 1($1)       # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu   $1, 0($1)       # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x1000100010001($9)
+# CHECK: lui   $1, 65534       # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 1($1)       # encoding: [0x01,0x00,0x28,0x90]
+# CHECK: lbu   $1, 0($1)       # encoding: [0x00,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]

test/MC/Mips/set-nomacro.s

# CHECK-NOT: warning: macro instruction expanded into multiple instructions
   la  $8, 161616
   la  $8, 16($9)
   la  $8, 161616($9)
   la  $8, symbol
 
   jal $25
   jal $4, $25
 
+  ulhu $5, 0
+
   add $4, $5, $6
 
   .set noreorder
   .set nomacro
   li  $8, -16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   li  $8, 16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   la  $8, symbol
 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
   jal $25
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   jal $4, $25
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
+  ulhu $5, 0
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
   add $4, $5, $6
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions