[mips] [IAS] Add partial support for the ULHU pseudo-instruction.

[tomatabacu]

Summary

This only adds support for ULHU of an immediate address with/without a source register.
It does not include support for ULHU of the address of a symbol.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2164–2165

Nit: We're going to end up writing this a lot. It would be good to factor it out.

2181–2182

For '.set noat' mode we currently give up here before discovering whether we need AT or not.

2188

What happens if OffsetValue is -32769? OffsetValue+1 will fit but we still need AT for OffsetValue

2203–2215

Shouldn't endianness have some effect on the expansion?

2204–2220

Nit: There's some repetition in the ternary operators. Could you factor out the repeated ones into variables?

2254

I'm not sure why this is needed.

[tomatabacu]

Addressed review comments.
Moved generation of (D)ADDu locally in order to closer match GAS' output.
Added .set nomacro warning and test.
Reformatted mips-expansions.s.
Removed some generation checks to fix mips-expansions-bad.s issues caused by rebase.
Rebased.

[tomatabacu]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2164–2165

Done in rL237780.

2181–2182

We always need AT for ULHU, as it is always used as the source register for one of the LBu's.
I added a code comment with this explanation.

2188

Fixed and added as test case in mips-expansions.s.
Also added a test case for the inverse case, when OffsetValue fits but OffsetValue+1 doesn't (OffsetValue is 32767).

2203–2215

Yes, it should. Fixed and added checks for both endian in mips-expansions.s.

2204–2220

Done.

2254

Because otherwise we would always generate ADDu, and GAS generates a DADDu for MIPS64.
The reason why it's in this patch is because this is where we have a concrete test case for it.

[tomatabacu]

Rebased.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2181–2182

Ah yes, it looked like one path didn't use it but that's not the case.

2204

Nit: I believe Fst should be First and Snd should be Second. Likewise below

FWIW, I'd usually spell them 'TmpReg1' and 'TmpReg2'. There's often little description you can give to scratch registers.

2254

Hmm.. This patch uses loadImmediate() is to load an offset into a register. In this context, we don't want to test for 64-bit GPR's but rather for 64-bit pointers (see MipsABIInfo::GetPtrAddiuOp()). However, loadImmediate() is also used for the 'li' instruction where we do want the test to be for 64-bit GPR's.

You'll need to separate the two contexts somehow. I think line 2197 ought to be:

if (loadImmediate(OffsetValue, ATReg, SrcReg, ABI.ArePtrs64bit(), IDLoc,
                  Instructions))

and the Is32bitImm argument to loadImmediate() needs to determine whether you get ADDu or DADDu

[tomatabacu]

Addressed review comments (one of them resulted in D10568).
Added a code comment with an example of why we add the SrcReg locally.
Fixed mistake in test/MC/Mips/set-nomacro.s caused by a previous rebase.

[dsanders]

I agree we've covered all the comments. LGTM

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2197–2199

I found this clarification a bit confusing at first. It might be better to write out the instructions.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
 
   void expandMemInst(MCInst &Inst, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions, bool isLoad,
                      bool isImmOpnd);
 
   bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandUlhu(MCInst &Inst, SMLoc IDLoc,
+                  SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   SmallVectorImpl<MCInst> &Instructions);
 
   bool reportParseError(Twine ErrorMsg);
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::LoadImm64:
   case Mips::LoadAddrImm32:
   case Mips::LoadAddrReg32:
   case Mips::B_MM_Pseudo:
   case Mips::LWM_MM:
   case Mips::SWM_MM:
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
+  case Mips::Ulhu:
     return true;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::B_MM_Pseudo:
     return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);
   case Mips::SWM_MM:
   case Mips::LWM_MM:
     return expandLoadStoreMultiple(Inst, IDLoc, Instructions);
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
     return expandJalWithRegs(Inst, IDLoc, Instructions);
+  case Mips::Ulhu:
+    return expandUlhu(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <unsigned ShiftAmount>
 void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
     // It can be implemented as SWM16 or LWM16 instruction.
     NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
 
   Inst.setOpcode(NewOpcode);
   Instructions.push_back(Inst);
   return false;
 }
 
+bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc,
+                               SmallVectorImpl<MCInst> &Instructions) {
+  if (hasMips32r6() || hasMips64r6()) {
+    Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
+    return false;
+  }
+
+  if (!AssemblerOptions.back()->isMacro())
+    Warning(IDLoc, "macro instruction expanded into multiple instructions");
+
+  const MCOperand &DstRegOp = Inst.getOperand(0);
+  assert(DstRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &SrcRegOp = Inst.getOperand(1);
+  assert(SrcRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &OffsetImmOp = Inst.getOperand(2);
+  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
+
+  unsigned DstReg = DstRegOp.getReg();
+  unsigned SrcReg = SrcRegOp.getReg();
+  int64_t OffsetValue = OffsetImmOp.getImm();
+
+  unsigned ATReg = getATReg(IDLoc);
+  if (!ATReg)
+    return true;
+
+  // When the value of offset+1 does not fit in 16 bits, we have to load the
+  // offset in AT, (D)ADDu the original source register (if there was one), and
+  // then use AT as the source register for the 2 generated LBu's.
+  bool LoadedOffsetInAT = false;
+  if (!isInt<16>(OffsetValue + 1)) {
+    LoadedOffsetInAT = true;
+
+    // NOTE: If there is no source register specified in the ULHU, the parser
+    // will interpret it as $0. However, in order to tell loadImmediate() not to
+    // use a source register we need to pass it a Mips::NoRegister.
+    if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64)
+      SrcReg = Mips::NoRegister;
+
+    if (loadImmediate(OffsetValue, ATReg, SrcReg, !isGP64bit(), IDLoc,
+                      Instructions))
+      return true;
+  }
+
+  MCInst TmpInst;
+  TmpInst.setOpcode(Mips::LBu);
+  TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? DstReg : ATReg));
+  TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? ATReg : SrcReg));
+  TmpInst.addOperand(MCOperand::CreateImm(LoadedOffsetInAT ? 0 : OffsetValue));
+  Instructions.push_back(TmpInst);
+
+  TmpInst.clear();
+  TmpInst.setOpcode(Mips::LBu);
+  TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? ATReg : DstReg));
+  TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? ATReg : SrcReg));
+  TmpInst.addOperand(
+      MCOperand::CreateImm(LoadedOffsetInAT ? 1 : (OffsetValue + 1)));
+  Instructions.push_back(TmpInst);
+
+  TmpInst.clear();
+  TmpInst.setOpcode(Mips::SLL);
+  TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? DstReg : ATReg));
+  TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? DstReg : ATReg));
+  TmpInst.addOperand(MCOperand::CreateImm(8));
+  Instructions.push_back(TmpInst);
+
+  TmpInst.clear();
+  TmpInst.setOpcode(Mips::OR);
+  TmpInst.addOperand(MCOperand::CreateReg(DstReg));
+  TmpInst.addOperand(MCOperand::CreateReg(DstReg));
+  TmpInst.addOperand(MCOperand::CreateReg(ATReg));
+  Instructions.push_back(TmpInst);
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   MCInst NopInst;
   if (hasShortDelaySlot) {
     NopInst.setOpcode(Mips::MOVE16_MM);
     NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
   } else {
     NopInst.setOpcode(Mips::SLL);
     NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::CreateImm(0));
   }
   Instructions.push_back(NopInst);
 }
 
 void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
                                unsigned TrgReg,
                                SmallVectorImpl<MCInst> &Instructions) {
   MCInst AdduInst;
-  AdduInst.setOpcode(Mips::ADDu);
+  AdduInst.setOpcode(isGP64bit() ? Mips::DADDu : Mips::ADDu);
   AdduInst.addOperand(MCOperand::CreateReg(DstReg));
   AdduInst.addOperand(MCOperand::CreateReg(SrcReg));
   AdduInst.addOperand(MCOperand::CreateReg(TrgReg));
   Instructions.push_back(AdduInst);
 }
 
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // As described by the Mips32r2 spec, the registers Rd and Rs for

lib/Target/Mips/MipsInstrInfo.td

MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
                      !strconcat(instr_asm, "\t$rt, $imm32")> ;
 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
 
 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
                       "jal\t$rd, $rs"> ;
 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
                       "jal\t$rs"> ;
 
+def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
+                             "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
 // Load/store pattern templates.
 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
   MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
 

test/MC/Mips/mips-expansions-bad.s

# RUN:   FileCheck %s --check-prefix=64-BIT
   la $5, 0x100000000
   # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
   # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
   la $5, 0x100000000($6)
   # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
   # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
   dli $5, 1
   # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
+
+ .set mips32r6
+  ulhu $5, 0
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+ .set mips32
+  ulhu $5, 1
+  # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+ .set mips64r6
+  ulhu $5, 2
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6

test/MC/Mips/mips-expansions.s

 # CHECK:     sw      $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac]
 # CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
 
 # CHECK: lui     $1, %hi(symbol)
 # CHECK: ldc1    $f0, %lo(symbol)($1)
 # CHECK: lui     $1, %hi(symbol)
 # CHECK: sdc1    $f0, %lo(symbol)($1)
 
+# CHECK: lbu $1, 0($zero)      # encoding: [0x00,0x00,0x01,0x90]
+# CHECK: lbu $8, 1($zero)      # encoding: [0x01,0x00,0x08,0x90]
+# CHECK: sll $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lbu $1, 2($zero)      # encoding: [0x02,0x00,0x01,0x90]
+# CHECK: lbu $8, 3($zero)      # encoding: [0x03,0x00,0x08,0x90]
+# CHECK: sll $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: ori $1, $zero, 32768  # encoding: [0x00,0x80,0x01,0x34]
+# CHECK: lbu $8, 0($1)         # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu $1, 1($1)         # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lbu $1, -32768($zero) # encoding: [0x00,0x80,0x01,0x90]
+# CHECK: lbu $8, -32767($zero) # encoding: [0x01,0x80,0x08,0x90]
+# CHECK: sll $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lui $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: lbu $8, 0($1)         # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu $1, 1($1)         # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lui $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori $1, $1, 34952     # encoding: [0x88,0x88,0x21,0x34]
+# CHECK: lbu $8, 0($1)         # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu $1, 1($1)         # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+
+# CHECK: lbu $1, 0($9)         # encoding: [0x00,0x00,0x21,0x91]
+# CHECK: lbu $8, 1($9)         # encoding: [0x01,0x00,0x28,0x91]
+# CHECK: sll $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lbu $1, 2($9)         # encoding: [0x02,0x00,0x21,0x91]
+# CHECK: lbu $8, 3($9)         # encoding: [0x03,0x00,0x28,0x91]
+# CHECK: sll $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: ori $1, $9, 32768     # encoding: [0x00,0x80,0x21,0x35]
+# CHECK: lbu $8, 0($1)         # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu $1, 1($1)         # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lbu $1, -32768($9)    # encoding: [0x00,0x80,0x21,0x91]
+# CHECK: lbu $8, -32767($9)    # encoding: [0x01,0x80,0x28,0x91]
+# CHECK: sll $1, $1, 8         # encoding: [0x00,0x0a,0x01,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lui $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: addu    $1, $1, $9    # encoding: [0x21,0x08,0x29,0x00]
+# CHECK: lbu $8, 0($1)         # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu $1, 1($1)         # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+# CHECK: lui $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori $1, $1, 34952     # encoding: [0x88,0x88,0x21,0x34]
+# CHECK: addu    $1, $1, $9    # encoding: [0x21,0x08,0x29,0x00]
+# CHECK: lbu $8, 0($1)         # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu $1, 1($1)         # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
+
     li $5,123
     li $6,-2345
     li $7,65538
     li $8, ~7
     li $9, 0x10000
 
     la $a0, 20
     la $7,65538
# CHECK: or  $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
     lw  $t2, 655483($a0)
     sw  $t2, 123456($t1)
 
     lw  $8, symbol
     sw  $8, symbol
 
     ldc1 $f0, symbol
     sdc1 $f0, symbol
+
+    ulhu $8, 0
+    ulhu $8, 2
+    ulhu $8, 0x8000
+    ulhu $8, -0x8000
+    ulhu $8, 0x10000
+    ulhu $8, 0x18888
+
+    ulhu $8, 0($9)
+    ulhu $8, 2($9)
+    ulhu $8, 0x8000($9)
+    ulhu $8, -0x8000($9)
+    ulhu $8, 0x10000($9)
+    ulhu $8, 0x18888($9)

test/MC/Mips/mips64-expansions.s

# CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
 
   dli $8, -0x1000100010001
 # CHECK: lui    $8, 65534           # encoding: [0xfe,0xff,0x08,0x3c]
 # CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
 # CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
 # CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
 # CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
 # CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+# Test ulhu with 64-bit immediate addresses.
+
+  ulhu $8, 0x100010001
+# CHECK: lui  $1, 1            # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lbu  $8, 0($1)        # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu  $1, 1($1)        # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, 0x1000100010001
+# CHECK: lui  $1, 1            # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1        # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lbu  $8, 0($1)        # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu  $1, 1($1)        # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x100010001
+# CHECK: lui  $1, 65535        # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535    # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lbu  $8, 0($1)        # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu  $1, 1($1)        # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x1000100010001
+# CHECK: lui  $1, 65534        # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534    # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16       # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535    # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lbu  $8, 0($1)        # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu  $1, 1($1)        # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll  $8, $8, 8        # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or   $8, $8, $1       # encoding: [0x25,0x40,0x01,0x01]
+
+# Test ulhu with source register and 64-bit immediate offset.
+
+  ulhu $8, 0x100010001($9)
+# CHECK: lui   $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 0($1)       # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu   $1, 1($1)       # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, 0x1000100010001($9)
+# CHECK: lui   $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 0($1)       # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu   $1, 1($1)       # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x100010001($9)
+# CHECK: lui   $1, 65535       # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 0($1)       # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu   $1, 1($1)       # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+  ulhu $8, -0x1000100010001($9)
+# CHECK: lui   $1, 65534       # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lbu   $8, 0($1)       # encoding: [0x00,0x00,0x28,0x90]
+# CHECK: lbu   $1, 1($1)       # encoding: [0x01,0x00,0x21,0x90]
+# CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
+# CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]