[mips] [IAS] Add partial support for the ULW pseudo-instruction.

[tomatabacu]

Summary

This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

[tomatabacu]

Rebased on top of D9671 (because of the similarities between them).
Made expansion take into account endianness.
Fixed handling of some offset values and added test cases for them.
Moved generation of (D)ADDu locally in order to closer match GAS' output.
Added .set nomacro warning and test.
Refactored repetitive uses of the ternary operator.

[tomatabacu]

Rebased.

[dsanders]

expandUlw() looks very similar to expandUlh(). Could we share code between them?

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2627–2632

Could you tell me the cases where this matters? loadImmediate() will usually emit the same thing here.

[tomatabacu]

Merged expandUlw() and expandUlhu() together.
Rebased top of the updated D9671.

[tomatabacu]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2627–2632

For example:

ulw/ulhu $8, 0x8000($9)

If we give the SrcReg to loadImmediate, we generate:

ori   $1, $9, 32768

If we do the addd locally, we generate:

ori   $1, $zero, 32768
addu  $1, $1, $9

GAS generates:

addiu $1, $zero, 32768
addu  $1, $1, $9

I added a code comment with this example to D9671.

[dsanders]

expandUlw() looks very similar to expandUlh(). Could we share code between them?

That's not nearly as similar as I thought it was. I thought it was >90% similar with just the odd line or two different but it is actually ~90% different with the odd similar chunk. Sorry to mess you about but could you roll back to the separated version in the previous diff?

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2627–2632

Thanks. One thing to point out. This:

ori   $1, $zero, 32768
addu  $1, $1, $9

is not equivalent to:

addiu $1, $zero, 32768
addu  $1, $1, $9

because addiu uses a simm16 (giving 0xffff8000) and ori uses a uimm16 (giving 0x00008000). I suspect we have a bug in loadImmediate(). GAS probably shouldn't silently change 32768 to -32768 either though.

test/MC/Mips/mips-expansions-bad.s

40

Nit: Indentation, likewise for the other .set's

[tomatabacu]

Addressed review comments.
Updated an explanation in a comment.

[tomatabacu]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2627–2632

Turns out I was wrong: GAS does indeed generate an ORi not an ADDiu in that case.
Sorry about that.

test/MC/Mips/mips-expansions-bad.s

40

Fixed.

[dsanders]

LGTM. Thanks

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool expandBranchImm(MCInst &Inst, SMLoc IDLoc,
                        SmallVectorImpl<MCInst> &Instructions);
 
   bool expandCondBranches(MCInst &Inst, SMLoc IDLoc,
                           SmallVectorImpl<MCInst> &Instructions);
 
   bool expandUlhu(MCInst &Inst, SMLoc IDLoc,
                   SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandUlw(MCInst &Inst, SMLoc IDLoc,
+                 SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   bool Is64Bit, SmallVectorImpl<MCInst> &Instructions);
 
   bool reportParseError(Twine ErrorMsg);
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::BLE:
   case Mips::BGE:
   case Mips::BGT:
   case Mips::BLTU:
   case Mips::BLEU:
   case Mips::BGEU:
   case Mips::BGTU:
   case Mips::Ulhu:
+  case Mips::Ulw:
     return true;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::BGT:
   case Mips::BLTU:
   case Mips::BLEU:
   case Mips::BGEU:
   case Mips::BGTU:
     return expandCondBranches(Inst, IDLoc, Instructions);
   case Mips::Ulhu:
     return expandUlhu(Inst, IDLoc, Instructions);
+  case Mips::Ulw:
+    return expandUlw(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <unsigned ShiftAmount>
 void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc,
   TmpInst.addOperand(MCOperand::createReg(DstReg));
   TmpInst.addOperand(MCOperand::createReg(DstReg));
   TmpInst.addOperand(MCOperand::createReg(ATReg));
   Instructions.push_back(TmpInst);
 
   return false;
 }
 
+bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc,
+                              SmallVectorImpl<MCInst> &Instructions) {
+  if (hasMips32r6() || hasMips64r6()) {
+    Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
+    return false;
+  }
+
+  const MCOperand &DstRegOp = Inst.getOperand(0);
+  assert(DstRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &SrcRegOp = Inst.getOperand(1);
+  assert(SrcRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &OffsetImmOp = Inst.getOperand(2);
+  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
+
+  unsigned SrcReg = SrcRegOp.getReg();
+  int64_t OffsetValue = OffsetImmOp.getImm();
+  unsigned ATReg = 0;
+
+  // When the value of offset+3 does not fit in 16 bits, we have to load the
+  // offset in AT, (D)ADDu the original source register (if there was one), and
+  // then use AT as the source register for the generated LWL and LWR.
+  bool LoadedOffsetInAT = false;
+  if (!isInt<16>(OffsetValue + 3) || !isInt<16>(OffsetValue)) {
+    ATReg = getATReg(IDLoc);
+    if (!ATReg)
+      return true;
+    LoadedOffsetInAT = true;
+
+    warnIfNoMacro(IDLoc);
+
+    if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(),
+                      IDLoc, Instructions))
+      return true;
+
+    // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate()
+    // because it will make our output more similar to GAS'. For example,
+    // generating an "ori $1, $zero, 32768" followed by an "addu $1, $1, $9",
+    // instead of just an "ori $1, $9, 32768".
+    // NOTE: If there is no source register specified in the ULW, the parser
+    // will interpret it as $0.
+    if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
+      createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Instructions);
+  }
+
+  unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg;
+  int64_t LeftLoadOffset = 0, RightLoadOffset  = 0;
+  if (isLittle()) {
+    LeftLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3);
+    RightLoadOffset  = LoadedOffsetInAT ? 0 : OffsetValue;
+  } else {
+    LeftLoadOffset = LoadedOffsetInAT ? 0 : OffsetValue;
+    RightLoadOffset  = LoadedOffsetInAT ? 3 : (OffsetValue + 3);
+  }
+
+  MCInst LeftLoadInst;
+  LeftLoadInst.setOpcode(Mips::LWL);
+  LeftLoadInst.addOperand(DstRegOp);
+  LeftLoadInst.addOperand(MCOperand::createReg(FinalSrcReg));
+  LeftLoadInst.addOperand(MCOperand::createImm(LeftLoadOffset));
+  Instructions.push_back(LeftLoadInst);
+
+  MCInst RightLoadInst;
+  RightLoadInst.setOpcode(Mips::LWR);
+  RightLoadInst.addOperand(DstRegOp);
+  RightLoadInst.addOperand(MCOperand::createReg(FinalSrcReg));
+  RightLoadInst.addOperand(MCOperand::createImm(RightLoadOffset ));
+  Instructions.push_back(RightLoadInst);
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   MCInst NopInst;
   if (hasShortDelaySlot) {
     NopInst.setOpcode(Mips::MOVE16_MM);
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
   } else {

lib/Target/Mips/MipsInstrInfo.td

 def BLTU : CondBranchPseudo<"bltu">;
 def BLEU : CondBranchPseudo<"bleu">;
 def BGEU : CondBranchPseudo<"bgeu">;
 def BGTU : CondBranchPseudo<"bgtu">;
 
 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
                              "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
 
+def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
+                            "ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
 // Load/store pattern templates.
 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
   MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
 

test/MC/Mips/mips-expansions-bad.s

# RUN:   FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY
   .set mips32
   ulhu $5, 1
   # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
   # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
   .set mips64r6
   ulhu $5, 2
   # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
   # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+
+  .set mips32r6
+  ulw $5, 0
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+  .set mips32
+  ulw $5, 1
+  # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+  .set mips64r6
+  ulw $5, 2
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6

test/MC/Mips/mips-expansions.s

 # CHECK-BE: or   $8, $8, $1        # encoding: [0x01,0x01,0x40,0x25]
 # CHECK-LE: ori  $1, $zero, 32767  # encoding: [0xff,0x7f,0x01,0x34]
 # CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
 # CHECK-LE: lbu  $8, 1($1)         # encoding: [0x01,0x00,0x28,0x90]
 # CHECK-LE: lbu  $1, 0($1)         # encoding: [0x00,0x00,0x21,0x90]
 # CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
 # CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
 
+# Test ULW with immediate operand.
+  ulw $8, 0
+# CHECK-BE: lwl  $8, 0($zero)      # encoding: [0x88,0x08,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($zero)      # encoding: [0x98,0x08,0x00,0x03]
+# CHECK-LE: lwl $8, 3($zero)       # encoding: [0x03,0x00,0x08,0x88]
+# CHECK-LE: lwr $8, 0($zero)       # encoding: [0x00,0x00,0x08,0x98]
+
+  ulw $8, 2
+# CHECK-BE: lwl  $8, 2($zero)      # encoding: [0x88,0x08,0x00,0x02]
+# CHECK-BE: lwr  $8, 5($zero)      # encoding: [0x98,0x08,0x00,0x05]
+# CHECK-LE: lwl $8, 5($zero)       # encoding: [0x05,0x00,0x08,0x88]
+# CHECK-LE: lwr $8, 2($zero)       # encoding: [0x02,0x00,0x08,0x98]
+
+  ulw $8, 0x8000
+# CHECK-BE: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori $1, $zero, 32768   # encoding: [0x00,0x80,0x01,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x8000
+# CHECK-BE: lwl  $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00]
+# CHECK-BE: lwr  $8, -32765($zero) # encoding: [0x98,0x08,0x80,0x03]
+# CHECK-LE: lwl $8, -32765($zero)  # encoding: [0x03,0x80,0x08,0x88]
+# CHECK-LE: lwr $8, -32768($zero)  # encoding: [0x00,0x80,0x08,0x98]
+
+  ulw $8, 0x10000
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui $1, 1              # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x18888
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: ori  $1, $1, 34952     # encoding: [0x34,0x21,0x88,0x88]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui $1, 1              # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: ori $1, $1, 34952      # encoding: [0x88,0x88,0x21,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -32771
+# CHECK-BE: lui  $1, 65535         # encoding: [0x3c,0x01,0xff,0xff]
+# CHECK-BE: ori  $1, $1, 32765     # encoding: [0x34,0x21,0x7f,0xfd]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui $1, 65535          # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK-LE: ori $1, $1, 32765      # encoding: [0xfd,0x7f,0x21,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 32765
+# CHECK-BE: ori  $1, $zero, 32765  # encoding: [0x34,0x01,0x7f,0xfd]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori $1, $zero, 32765   # encoding: [0xfd,0x7f,0x01,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+# Test ULW with immediate offset and a source register operand.
+  ulw $8, 0($9)
+# CHECK-BE: lwl  $8, 0($9)         # encoding: [0x89,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($9)         # encoding: [0x99,0x28,0x00,0x03]
+# CHECK-LE: lwl  $8, 3($9)         # encoding: [0x03,0x00,0x28,0x89]
+# CHECK-LE: lwr  $8, 0($9)         # encoding: [0x00,0x00,0x28,0x99]
+
+  ulw $8, 2($9)
+# CHECK-BE: lwl  $8, 2($9)         # encoding: [0x89,0x28,0x00,0x02]
+# CHECK-BE: lwr  $8, 5($9)         # encoding: [0x99,0x28,0x00,0x05]
+# CHECK-LE: lwl  $8, 5($9)         # encoding: [0x05,0x00,0x28,0x89]
+# CHECK-LE: lwr  $8, 2($9)         # encoding: [0x02,0x00,0x28,0x99]
+
+  ulw $8, 0x8000($9)
+# CHECK-BE: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori  $1, $zero, 32768  # encoding: [0x00,0x80,0x01,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x8000($9)
+# CHECK-BE: lwl  $8, -32768($9)    # encoding: [0x89,0x28,0x80,0x00]
+# CHECK-BE: lwr  $8, -32765($9)    # encoding: [0x99,0x28,0x80,0x03]
+# CHECK-LE: lwl  $8, -32765($9)    # encoding: [0x03,0x80,0x28,0x89]
+# CHECK-LE: lwr  $8, -32768($9)    # encoding: [0x00,0x80,0x28,0x99]
+
+  ulw $8, 0x10000($9)
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x18888($9)
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: ori  $1, $1, 34952     # encoding: [0x34,0x21,0x88,0x88]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 34952     # encoding: [0x88,0x88,0x21,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -32771($9)
+# CHECK-BE: lui  $1, 65535         # encoding: [0x3c,0x01,0xff,0xff]
+# CHECK-BE: ori  $1, $1, 32765     # encoding: [0x34,0x21,0x7f,0xfd]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui  $1, 65535         # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 32765     # encoding: [0xfd,0x7f,0x21,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 32765($9)
+# CHECK-BE: ori  $1, $zero, 32765  # encoding: [0x34,0x01,0x7f,0xfd]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori  $1, $zero, 32765  # encoding: [0xfd,0x7f,0x01,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
 1:
   add $4, $4, $4

test/MC/Mips/mips64-expansions.s

 # CHECK: ori   $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
 # CHECK: dsll  $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
 # CHECK: ori   $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
 # CHECK: daddu $1, $1, $9      # encoding: [0x2d,0x08,0x29,0x00]
 # CHECK: lbu   $8, 1($1)       # encoding: [0x01,0x00,0x28,0x90]
 # CHECK: lbu   $1, 0($1)       # encoding: [0x00,0x00,0x21,0x90]
 # CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
 # CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+# Test ulw with 64-bit immediate addresses.
+  ulw $8, 0x100010001
+# CHECK: lui  $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x1000100010001
+# CHECK: lui  $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x100010001
+# CHECK: lui  $1, 65535       # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x1000100010001
+# CHECK: lui  $1, 65534       # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+# Test ulw with source register and 64-bit immediate offset.
+  ulw $8, 0x100010001($9)
+# CHECK: lui   $1, 1          # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x1000100010001($9)
+# CHECK: lui   $1, 1          # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x100010001($9)
+# CHECK: lui   $1, 65535      # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535  # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x1000100010001($9)
+# CHECK: lui   $1, 65534      # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535  # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]

test/MC/Mips/set-nomacro.s

# CHECK-NOT: warning: macro instruction expanded into multiple instructions
 
   bgtu $7, $8, local_label
   bgtu $7, $0, local_label
   bgtu $0, $8, local_label
   bgtu $0, $0, local_label
 
   ulhu $5, 0
 
+  ulw $8, 2
+  ulw $8, 0x8000
+  ulw $8, 2($9)
+  ulw $8, 0x8000($9)
+
   add $4, $5, $6
 
   .set noreorder
   .set nomacro
   li  $8, -16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   li  $8, 16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   bgtu $0, $8, local_label
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   bgtu $0, $0, local_label
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
   ulhu $5, 0
 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
+  ulw $8, 2
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ulw $8, 0x8000
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ulw $8, 2($9)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ulw $8, 0x8000($9)
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
   add $4, $5, $6
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions