[mips] [IAS] Add support for BNE and BEQ with an immediate operand.

[tomatabacu]

Summary

For some branches, GAS accepts an immediate instead of the 2nd register operand.
We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed.

[dsanders]

LGTM with the correct operand.

lib/Target/Mips/MipsInstrInfo.td

1676 ↗

(On Diff #25476)

I don't think you mean uimm5 here. Doesn't this accept a 32-bit immediate?

1679 ↗

(On Diff #25476)

Likewise

[tomatabacu]

Replied to inline comment.

lib/Target/Mips/MipsInstrInfo.td

1676 ↗

(On Diff #25476)

I'm not sure what to put here. I chose uimm5 because that's what LoadImm32 and LoadAddrImm32 use.

[dsanders]

lib/Target/Mips/MipsInstrInfo.td

1676 ↗

(On Diff #25476)

They will need correcting too at some point. At the moment we get away with a fair bit because we don't do range checking on assembly immediates.

For 32-bit immediates, you need to define a simm32 and use that. If this accepts 64-bit immediates as well then define simm64 instead.

[tomatabacu]

lib/Target/Mips/MipsInstrInfo.td

1676 ↗

(On Diff #25476)

AFAICT simm32 or simm64 are not defined anywhere.
There's an imm64 in Mips64InstrInfo.td, so I could move the defs in there and use that.
These instructions are supposed to accept 64-bit immediates on 64-bit archs.

Also, I forgot to add a test case in mips-expansions-bad.s for using these with 64-bit immediates on 32-bit archs.

[dsanders]

lib/Target/Mips/MipsInstrInfo.td

1676 ↗

(On Diff #25476)

AFAICT simm32 or simm64 are not defined anywhere.

That's correct, you'll need to define them.

[tomatabacu]

Switched to using (the already defined) imm64 in TableGen definitions.
Added test case for the 64-bit immediates on 32-bit architectures warning.
Added .set nomacro warning & test case.
Rebased.

Please review again.

[tomatabacu]

Rebased.

[dsanders]

lib/Target/Mips/Mips64InstrInfo.td

631–638

I'm not sure why you moved this to Mips64InstrInfo.td and changed the GPR32's to GPR64's. You only needed to change uimm5 to imm64.

It will LGTM with this put back in MipsInstrInfo.td and the GPR64's reverted to GPR32's.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
 
   void expandMemInst(MCInst &Inst, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions, bool isLoad,
                      bool isImmOpnd);
 
   bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandBranchImm(MCInst &Inst, SMLoc IDLoc,
+                       SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   SmallVectorImpl<MCInst> &Instructions);
 
   bool reportParseError(Twine ErrorMsg);
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::LoadImm64:
   case Mips::LoadAddrImm32:
   case Mips::LoadAddrReg32:
   case Mips::B_MM_Pseudo:
   case Mips::LWM_MM:
   case Mips::SWM_MM:
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
+  case Mips::BneImm:
+  case Mips::BeqImm:
     return true;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::B_MM_Pseudo:
     return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);
   case Mips::SWM_MM:
   case Mips::LWM_MM:
     return expandLoadStoreMultiple(Inst, IDLoc, Instructions);
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
     return expandJalWithRegs(Inst, IDLoc, Instructions);
+  case Mips::BneImm:
+  case Mips::BeqImm:
+    return expandBranchImm(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <unsigned ShiftAmount>
 void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
bool MipsAsmParser::expandUncondBranchMMPseudo(
 
   // If .set reorder is active, emit a NOP after the branch instruction.
   if (AssemblerOptions.back()->isReorder())
     createNop(true, IDLoc, Instructions);
 
   return false;
 }
 
+bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc,
+                                    SmallVectorImpl<MCInst> &Instructions) {
+  const MCOperand &DstRegOp = Inst.getOperand(0);
+  assert(DstRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &ImmOp = Inst.getOperand(1);
+  assert(ImmOp.isImm() && "expected immediate operand kind");
+
+  const MCOperand &MemOffsetOp = Inst.getOperand(2);
+  assert(MemOffsetOp.isImm() && "expected immediate operand kind");
+
+  unsigned OpCode = 0;
+  switch(Inst.getOpcode()) {
+    case Mips::BneImm:
+      OpCode = Mips::BNE;
+      break;
+    case Mips::BeqImm:
+      OpCode = Mips::BEQ;
+      break;
+    default:
+      llvm_unreachable("Unknown immediate branch pseudo-instruction.");
+      break;
+  }
+
+  int64_t ImmValue = ImmOp.getImm();
+  if (ImmValue == 0) {
+    MCInst BranchInst;
+    BranchInst.setOpcode(OpCode);
+    BranchInst.addOperand(DstRegOp);
+    BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+    BranchInst.addOperand(MemOffsetOp);
+    Instructions.push_back(BranchInst);
+  } else {
+    warnIfNoMacro(IDLoc);
+
+    unsigned ATReg = getATReg(IDLoc);
+    if (!ATReg)
+      return true;
+
+    if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), IDLoc,
+                      Instructions))
+      return true;
+
+    MCInst BranchInst;
+    BranchInst.setOpcode(OpCode);
+    BranchInst.addOperand(DstRegOp);
+    BranchInst.addOperand(MCOperand::createReg(ATReg));
+    BranchInst.addOperand(MemOffsetOp);
+    Instructions.push_back(BranchInst);
+  }
+  return false;
+}
+
 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions,
                                   bool isLoad, bool isImmOpnd) {
   const MCSymbolRefExpr *SR;
   MCInst TempInst;
   unsigned ImmOffset, HiOffset, LoOffset;
   const MCExpr *ExprOffset;
   unsigned TmpRegNum;

lib/Target/Mips/Mips64InstrInfo.td

 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
   MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
                      !strconcat(instr_asm, "\t$rt, $imm64")> ;
 def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>;
+
+let hasDelaySlot = 1 in {
+def BneImm : MipsAsmPseudoInst<(outs GPR64Opnd:$rt),
+                               (ins imm64:$imm64, brtarget:$offset),
+                               "bne\t$rt, $imm64, $offset">;
+def BeqImm : MipsAsmPseudoInst<(outs GPR64Opnd:$rt),
+                               (ins imm64:$imm64, brtarget:$offset),
+                               "beq\t$rt, $imm64, $offset">;
+}

test/MC/Mips/mips-expansions-bad.s

# RUN:   FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY
   # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
   la $5, symbol
   # N64-ONLY: :[[@LINE-1]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol
   # N32-ONLY-NOT: :[[@LINE-2]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol
   # 64-BIT: lui $5, %hi(symbol)
   # 64-BIT: ori $5, $5, %lo(symbol)
   dli $5, 1
   # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
+  bne $2, 0x100010001, 1332
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
+  beq $2, 0x100010001, 1332
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate

test/MC/Mips/mips-expansions.s

 # CHECK:     sw      $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac]
 # CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
 
 # CHECK: lui     $1, %hi(symbol)
 # CHECK: ldc1    $f0, %lo(symbol)($1)
 # CHECK: lui     $1, %hi(symbol)
 # CHECK: sdc1    $f0, %lo(symbol)($1)
 
+# CHECK: bnez  $2, 1332          # encoding: [0x4d,0x01,0x40,0x14]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: ori   $1, $zero, 123    # encoding: [0x7b,0x00,0x01,0x34]
+# CHECK: bne   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: addiu $1, $zero, -2345  # encoding: [0xd7,0xf6,0x01,0x24]
+# CHECK: bne   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lui   $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 2         # encoding: [0x02,0x00,0x21,0x34]
+# CHECK: bne   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: addiu $1, $zero, -8     # encoding: [0xf8,0xff,0x01,0x24]
+# CHECK: bne   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lui   $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: bne   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+
+# CHECK: beqz  $2, 1332          # encoding: [0x4d,0x01,0x40,0x10]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: ori   $1, $zero, 123    # encoding: [0x7b,0x00,0x01,0x34]
+# CHECK: beq   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: addiu $1, $zero, -2345  # encoding: [0xd7,0xf6,0x01,0x24]
+# CHECK: beq   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lui   $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 2         # encoding: [0x02,0x00,0x21,0x34]
+# CHECK: beq   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: addiu $1, $zero, -8     # encoding: [0xf8,0xff,0x01,0x24]
+# CHECK: beq   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lui   $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: beq   $2, $1, 1332      # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
+
     li $5,123
     li $6,-2345
     li $7,65538
     li $8, ~7
     li $9, 0x10000
     li $10, ~(0x101010)
 
     la $a0, 20
# CHECK: nop                     # encoding: [0x00,0x00,0x00,0x00]
     lw  $t2, 655483($a0)
     sw  $t2, 123456($t1)
 
     lw  $8, symbol
     sw  $8, symbol
 
     ldc1 $f0, symbol
     sdc1 $f0, symbol
+
+    bne $2, 0,       1332
+    bne $2, 123,     1332
+    bne $2, -2345,   1332
+    bne $2, 65538,   1332
+    bne $2, ~7,      1332
+    bne $2, 0x10000, 1332
+
+    beq $2, 0,       1332
+    beq $2, 123,     1332
+    beq $2, -2345,   1332
+    beq $2, 65538,   1332
+    beq $2, ~7,      1332
+    beq $2, 0x10000, 1332

test/MC/Mips/mips64-expansions.s

# CHECK-NOT: dsll
   dli $10, ~(0x202020)
 # CHECK: lui $10, 65503        # encoding: [0xdf,0xff,0x0a,0x3c]
 # CHECK: ori $10, $10, 57311   # encoding: [0xdf,0xdf,0x4a,0x35]
 # CHECK-NOT: dsll
 
   dli $9, 0x80000000
 # CHECK: ori  $9, $zero, 32768 # encoding: [0x00,0x80,0x09,0x34]
 # CHECK: dsll $9, $9, 16       # encoding: [0x38,0x4c,0x09,0x00]
+
+# Test bne with an immediate as the 2nd operand.
+  bne $2, 0x100010001, 1332
+# CHECK: lui  $1, 1                 # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: bne  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]
+
+  bne $2, 0x1000100010001, 1332
+# CHECK: lui  $1, 1                 # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: bne  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]
+
+  bne $2, -0x100010001, 1332
+# CHECK: lui  $1, 65535             # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535         # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: bne  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]
+
+  bne $2, -0x1000100010001, 1332
+# CHECK: lui  $1, 65534             # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535         # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: bne  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x14]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]
+
+# Test beq with an immediate as the 2nd operand.
+  beq $2, 0x100010001, 1332
+# CHECK: lui  $1, 1                 # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: beq  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]
+
+  beq $2, 0x1000100010001, 1332
+# CHECK: lui  $1, 1                 # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1             # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: beq  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]
+
+  beq $2, -0x100010001, 1332
+# CHECK: lui  $1, 65535             # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535         # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: beq  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]
+
+  beq $2, -0x1000100010001, 1332
+# CHECK: lui  $1, 65534             # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534         # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16            # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535         # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: beq  $2, $1, 1332          # encoding: [0x4d,0x01,0x41,0x10]
+# CHECK: nop                        # encoding: [0x00,0x00,0x00,0x00]

test/MC/Mips/set-nomacro.s

# CHECK-NOT: warning: macro instruction expanded into multiple instructions
   la  $8, 161616
   la  $8, 16($9)
   la  $8, 161616($9)
   la  $8, symbol
 
   jal $25
   jal $4, $25
 
+  bne $2, 0, 1332
+  bne $2, 1, 1332
+  beq $2, 0, 1332
+  beq $2, 1, 1332
+
   add $4, $5, $6
 
   .set noreorder
   .set nomacro
   li  $8, -16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   li  $8, 16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   la  $8, symbol
 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
   jal $25
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   jal $4, $25
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
+  bne $2, 0, 1332
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bne $2, 1, 1332
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  beq $2, 0, 1332
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  beq $2, 1, 1332
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
   add $4, $5, $6
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions