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Differential D9658

[mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions
ClosedPublic

Authored by zbuljan on May 11 2015, 5:16 AM.

Details

Reviewers
dsanders
zoran.jovanovic
hvarga
Commits
rL247880: [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions
Summary

The patch implements microMIPSr6 TEQ, TGE, TGEU, TLT, TLTU and TNE instructions.

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 25459.May 11 2015, 5:16 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions.
zbuljan updated this object.
zbuljan edited the test plan for this revision. (Show Details)
zbuljan added reviewers: jkolek, zoran.jovanovic, dsanders.
zbuljan added subscribers: petarj, Unknown Object (MLST).
zbuljan updated this revision to Diff 34016.Sep 4 2015, 12:34 AM
zbuljan edited reviewers, added: hvarga; removed: jkolek.

Removed unnecessary implementation for microMIPS32R6 (and microMIPS64R6).
Added tests for microMIPS64R6.

dsanders accepted this revision.Sep 4 2015, 2:12 AM
dsanders edited edge metadata.

LGTM

This revision is now accepted and ready to land.Sep 4 2015, 2:12 AM
Closed by commit rL247880: [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions (authored by zjovanovic). · Explain WhySep 17 2015, 3:15 AM
This revision was automatically updated to reflect the committed changes.
zbuljan removed a child revision: D9824: [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions.Sep 17 2015, 5:49 AM

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
6 lines
Disassembler/
13 lines
12 lines
42 lines
test/
MC/
Disassembler/
Mips/
12 lines
24 lines
24 lines
12 lines
Mips/
micromips32r6/
24 lines
12 lines
micromips64r6/
24 lines
12 lines

Diff 34016

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 1,731 Lines • ▼ Show 20 Lines switch (Inst.getOpcode()) {
case Mips::LBU16_MM: case Mips::LBU16_MM:
Opnd = Inst.getOperand(2); Opnd = Inst.getOperand(2);
if (!Opnd.isImm()) if (!Opnd.isImm())
return Error(IDLoc, "expected immediate operand kind"); return Error(IDLoc, "expected immediate operand kind");
Imm = Opnd.getImm(); Imm = Opnd.getImm();
if (Imm < -1 || Imm > 14) if (Imm < -1 || Imm > 14)
return Error(IDLoc, "immediate operand value out of range"); return Error(IDLoc, "immediate operand value out of range");
break; break;
case Mips::TEQ_MM:
case Mips::TGE_MM:
case Mips::TGEU_MM:
case Mips::TLT_MM:
case Mips::TLTU_MM:
case Mips::TNE_MM:
case Mips::SB16_MM: case Mips::SB16_MM:
Opnd = Inst.getOperand(2); Opnd = Inst.getOperand(2);
if (!Opnd.isImm()) if (!Opnd.isImm())
return Error(IDLoc, "expected immediate operand kind"); return Error(IDLoc, "expected immediate operand kind");
Imm = Opnd.getImm(); Imm = Opnd.getImm();
if (Imm < 0 || Imm > 15) if (Imm < 0 || Imm > 15)
return Error(IDLoc, "immediate operand value out of range"); return Error(IDLoc, "immediate operand value out of range");
break; break;
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lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 848 Lines • ▼ Show 20 Lines if (IsMicroMips) {
if (Result == MCDisassembler::Fail) if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (hasMips32r6()) { if (hasMips32r6()) {
DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
// Calling the auto-generated decoder function. // Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
this, STI); this, STI);
} else { if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
}
DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
// Calling the auto-generated decoder function. // Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
this, STI); this, STI);
}
if (Result != MCDisassembler::Fail) { if (Result != MCDisassembler::Fail) {
Size = 4; Size = 4;
return Result; return Result;
} }
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
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lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 931 Lines • ▼ Show 20 Linesclass UncondBranchMMPseudo<string opstr> :
def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>; def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>; def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
} }
let Predicates = [InMicroMips] in { let Predicates = [InMicroMips] in {
def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tge $rs, $rt",
(TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tgeu $rs, $rt",
(TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tlt $rs, $rt",
(TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tltu $rs, $rt",
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
} }

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,264 Lines • ▼ Show 20 Lineslet DecoderNamespace = "COP3_" in {
def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
ISA_MIPS2; ISA_MIPS2;
} }
} }
def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32; def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
let AdditionalPredicates = [NotInMicroMips] in {
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2; def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2; def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2; def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2; def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2; def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2; def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
}
def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
ISA_MIPS2_NOT_32R6_64R6; ISA_MIPS2_NOT_32R6_64R6;
def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
ISA_MIPS2_NOT_32R6_64R6; ISA_MIPS2_NOT_32R6_64R6;
def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
ISA_MIPS2_NOT_32R6_64R6; ISA_MIPS2_NOT_32R6_64R6;
def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
▲ Show 20 Lines • Show All 359 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
} }
def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"teq $rs, $rt", def : MipsInstAlias<"teq $rs, $rt",
(TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tge $rs, $rt", def : MipsInstAlias<"tge $rs, $rt",
(TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tgeu $rs, $rt", def : MipsInstAlias<"tgeu $rs, $rt",
(TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tlt $rs, $rt", def : MipsInstAlias<"tlt $rs, $rt",
(TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tltu $rs, $rt", def : MipsInstAlias<"tltu $rs, $rt",
(TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tne $rs, $rt", def : MipsInstAlias<"tne $rs, $rt",
(TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
}
def : MipsInstAlias<"sll $rd, $rt, $rs", def : MipsInstAlias<"sll $rd, $rt, $rs",
(SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sub, $rd, $rs, $imm", def : MipsInstAlias<"sub, $rd, $rs, $imm",
(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"sub $rs, $imm", def : MipsInstAlias<"sub $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
0>, ISA_MIPS1_NOT_32R6_64R6; 0>, ISA_MIPS1_NOT_32R6_64R6;
▲ Show 20 Lines • Show All 317 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips.txt

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
0x40 0xc6 0x02 0x9a # CHECK: bgtz $6, 1332 0x40 0xc6 0x02 0x9a # CHECK: bgtz $6, 1332
0x40 0x86 0x02 0x9a # CHECK: blez $6, 1332 0x40 0x86 0x02 0x9a # CHECK: blez $6, 1332
0xb4 0xc9 0x02 0x9a # CHECK: bne $9, $6, 1332 0xb4 0xc9 0x02 0x9a # CHECK: bne $9, $6, 1332
0x40 0x06 0x02 0x9a # CHECK: bltz $6, 1332 0x40 0x06 0x02 0x9a # CHECK: bltz $6, 1332
0x01 0x28 0x00 0x3c # CHECK: teq $8, $9, 0 0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
0x01 0x28 0x02 0x3c # CHECK: tge $8, $9, 0 0x01 0x28 0x02 0x3c # CHECK: tge $8, $9
0x01 0x28 0x04 0x3c # CHECK: tgeu $8, $9, 0 0x01 0x28 0x04 0x3c # CHECK: tgeu $8, $9
0x01 0x28 0x08 0x3c # CHECK: tlt $8, $9, 0 0x01 0x28 0x08 0x3c # CHECK: tlt $8, $9
0x01 0x28 0x0a 0x3c # CHECK: tltu $8, $9, 0 0x01 0x28 0x0a 0x3c # CHECK: tltu $8, $9
0x01 0x28 0x0c 0x3c # CHECK: tne $8, $9, 0 0x01 0x28 0x0c 0x3c # CHECK: tne $8, $9
0x41,0xc9,0x45,0x67 # CHECK: teqi $9, 17767 0x41,0xc9,0x45,0x67 # CHECK: teqi $9, 17767
0x41 0x29 0x45 0x67 # CHECK: tgei $9, 17767 0x41 0x29 0x45 0x67 # CHECK: tgei $9, 17767
0x41 0x69 0x45 0x67 # CHECK: tgeiu $9, 17767 0x41 0x69 0x45 0x67 # CHECK: tgeiu $9, 17767
0x41 0x09 0x45 0x67 # CHECK: tlti $9, 17767 0x41 0x09 0x45 0x67 # CHECK: tlti $9, 17767
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r6.txt

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4 0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4
0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4 0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4
0xf8,0xa6,0x00,0x04 # CHECK: sw $5, 4($6) 0xf8,0xa6,0x00,0x04 # CHECK: sw $5, 4($6)
0x60,0xa4,0xae,0x08 # CHECK: swe $5, 8($4) 0x60,0xa4,0xae,0x08 # CHECK: swe $5, 8($4)
0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
0x00 0xe5 0xf0 0x3c # CHECK: teq $5, $7, 15
0x01 0x47 0x02 0x3c # CHECK: tge $7, $10
0x02 0x67 0xf2 0x3c # CHECK: tge $7, $19, 15
0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15

test/MC/Disassembler/Mips/micromips64r6.txt

Show All 33 Lines
0x58 0x64 0x29 0x18 # CHECK: ddiv $3, $4, $5 0x58 0x64 0x29 0x18 # CHECK: ddiv $3, $4, $5
0x58 0x64 0x29 0x58 # CHECK: dmod $3, $4, $5 0x58 0x64 0x29 0x58 # CHECK: dmod $3, $4, $5
0x58 0x64 0x29 0x98 # CHECK: ddivu $3, $4, $5 0x58 0x64 0x29 0x98 # CHECK: ddivu $3, $4, $5
0x58 0x64 0x29 0xd8 # CHECK: dmodu $3, $4, $5 0x58 0x64 0x29 0xd8 # CHECK: dmodu $3, $4, $5
0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
0x00 0xe5 0xf0 0x3c # CHECK: teq $5, $7, 15
0x01 0x47 0x02 0x3c # CHECK: tge $7, $10
0x02 0x67 0xf2 0x3c # CHECK: tge $7, $19, 15
0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15

test/MC/Disassembler/Mips/micromips_le.txt

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
0xc6 0x40 0x9a 0x02 # CHECK: bgtz $6, 1332 0xc6 0x40 0x9a 0x02 # CHECK: bgtz $6, 1332
0x86 0x40 0x9a 0x02 # CHECK: blez $6, 1332 0x86 0x40 0x9a 0x02 # CHECK: blez $6, 1332
0xc9 0xb4 0x9a 0x02 # CHECK: bne $9, $6, 1332 0xc9 0xb4 0x9a 0x02 # CHECK: bne $9, $6, 1332
0x06 0x40 0x9a 0x02 # CHECK: bltz $6, 1332 0x06 0x40 0x9a 0x02 # CHECK: bltz $6, 1332
0x28 0x01 0x3c 0x00 # CHECK: teq $8, $9, 0 0x28 0x01 0x3c 0x00 # CHECK: teq $8, $9
0x28 0x01 0x3c 0x02 # CHECK: tge $8, $9, 0 0x28 0x01 0x3c 0x02 # CHECK: tge $8, $9
0x28 0x01 0x3c 0x04 # CHECK: tgeu $8, $9, 0 0x28 0x01 0x3c 0x04 # CHECK: tgeu $8, $9
0x28 0x01 0x3c 0x08 # CHECK: tlt $8, $9, 0 0x28 0x01 0x3c 0x08 # CHECK: tlt $8, $9
0x28 0x01 0x3c 0x0a # CHECK: tltu $8, $9, 0 0x28 0x01 0x3c 0x0a # CHECK: tltu $8, $9
0x28 0x01 0x3c 0x0c # CHECK: tne $8, $9, 0 0x28 0x01 0x3c 0x0c # CHECK: tne $8, $9
0xc9 0x41 0x67 0x45 # CHECK: teqi $9, 17767 0xc9 0x41 0x67 0x45 # CHECK: teqi $9, 17767
0x29 0x41 0x67 0x45 # CHECK: tgei $9, 17767 0x29 0x41 0x67 0x45 # CHECK: tgei $9, 17767
0x69 0x41 0x67 0x45 # CHECK: tgeiu $9, 17767 0x69 0x41 0x67 0x45 # CHECK: tgeiu $9, 17767
0x09 0x41 0x67 0x45 # CHECK: tlti $9, 17767 0x09 0x41 0x67 0x45 # CHECK: tlti $9, 17767
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test/MC/Mips/micromips32r6/invalid.s

# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
addiur1sp $7, 260 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur1sp $7, 260 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addiur1sp $7, 241 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value addiur1sp $7, 241 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value
addiur1sp $8, 240 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur1sp $8, 240 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addius5 $7, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addius5 $7, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swe $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swe $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swe $5, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swe $5, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swe $5, 512($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swe $5, 512($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80]
sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00] sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90] sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90]
subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0] subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2] xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08] swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
teq $8, $9 # CHECK: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
teq $5, $7, 15 # CHECK: teq $5, $7, 15 # encoding: [0x00,0xe5,0xf0,0x3c]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x01,0x47,0x02,0x3c]
tge $7, $19, 15 # CHECK: tge $7, $19, 15 # encoding: [0x02,0x67,0xf2,0x3c]
tgeu $22, $gp # CHECK: tgeu $22, $gp # encoding: [0x03,0x96,0x04,0x3c]
tgeu $20, $14, 15 # CHECK: tgeu $20, $14, 15 # encoding: [0x01,0xd4,0xf4,0x3c]
tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
tltu $11, $16 # CHECK: tltu $11, $16 # encoding: [0x02,0x0b,0x0a,0x3c]
tltu $16, $sp, 15 # CHECK: tltu $16, $sp, 15 # encoding: [0x03,0xb0,0xfa,0x3c]
tne $6, $17 # CHECK: tne $6, $17 # encoding: [0x02,0x26,0x0c,0x3c]
tne $7, $8, 15 # CHECK: tne $7, $8, 15 # encoding: [0x01,0x07,0xfc,0x3c]

test/MC/Mips/micromips64r6/invalid.s

Show All 14 Lines# RUN: FileCheck %s < %t1
dmod $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmod $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dmod $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmod $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ddivu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ddivu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ddivu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ddivu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ddivu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ddivu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dmodu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmodu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dmodu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmodu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dmodu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction dmodu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips64r6/valid.s

Show All 15 Linesa:
dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec] dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec]
dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4] dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4]
dextu $9, $6, 3, 7 # CHECK: dextu $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xd4] dextu $9, $6, 3, 7 # CHECK: dextu $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xd4]
dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c] dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c]
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0x64,0x29,0x18] ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0x64,0x29,0x18]
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0x64,0x29,0x58] dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0x64,0x29,0x58]
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0x64,0x29,0x98] ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0x64,0x29,0x98]
dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0x64,0x29,0xd8] dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0x64,0x29,0xd8]
teq $8, $9 # CHECK: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
teq $5, $7, 15 # CHECK: teq $5, $7, 15 # encoding: [0x00,0xe5,0xf0,0x3c]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x01,0x47,0x02,0x3c]
tge $7, $19, 15 # CHECK: tge $7, $19, 15 # encoding: [0x02,0x67,0xf2,0x3c]
tgeu $22, $gp # CHECK: tgeu $22, $gp # encoding: [0x03,0x96,0x04,0x3c]
tgeu $20, $14, 15 # CHECK: tgeu $20, $14, 15 # encoding: [0x01,0xd4,0xf4,0x3c]
tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
tltu $11, $16 # CHECK: tltu $11, $16 # encoding: [0x02,0x0b,0x0a,0x3c]
tltu $16, $sp, 15 # CHECK: tltu $16, $sp, 15 # encoding: [0x03,0xb0,0xfa,0x3c]
tne $6, $17 # CHECK: tne $6, $17 # encoding: [0x02,0x26,0x0c,0x3c]
tne $7, $8, 15 # CHECK: tne $7, $8, 15 # encoding: [0x01,0x07,0xfc,0x3c]
1: 1: