[AVR] Add register aliases XL, YH, etc

[aykevl]

Summary

These aliases are sometimes used in assembly code and make the code more readable. They are supported by avr-gcc too.

[benshi001]

llvm/lib/Target/AVR/AVRRegisterInfo.td

70

how about also add alias __tmp_reg__ for R0 and __zero_reg__ for R1 as avr-gcc does?

[aykevl]

llvm/lib/Target/AVR/AVRRegisterInfo.td

70

I _think_ this is implemented slightly differently in GCC. For example, if you take a look here (https://godbolt.org/z/sdEcc7) you can see that it defines __tmp_reg__ separately. Also, note that these two registers (__tmp_reg__ and __zero_reg__) are different on "reduced tiny" chips, see https://gcc.gnu.org/wiki/avr-gcc#Reduced_Tiny - I'm not sure this difference can be easily expressed in this register file description.

[benshi001]

llvm/lib/Target/AVR/AVRRegisterInfo.td

70

I see. Thanks.

llvm/lib/Target/AVR/AVRRegisterInfo.td

 def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>;
 def R19 : AVRReg<19, "r19">, DwarfRegNum<[19]>;
 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>;
 def R21 : AVRReg<21, "r21">, DwarfRegNum<[21]>;
 def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>;
 def R23 : AVRReg<23, "r23">, DwarfRegNum<[23]>;
 def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>;
 def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>;
-def R26 : AVRReg<26, "r26">, DwarfRegNum<[26]>;
-def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>;
-def R28 : AVRReg<28, "r28">, DwarfRegNum<[28]>;
-def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>;
-def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>;
-def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
+def R26 : AVRReg<26, "r26", [], ["xl"]>, DwarfRegNum<[26]>;
+def R27 : AVRReg<27, "r27", [], ["xh"]>, DwarfRegNum<[27]>;
+def R28 : AVRReg<28, "r28", [], ["yl"]>, DwarfRegNum<[28]>;
+def R29 : AVRReg<29, "r29", [], ["yh"]>, DwarfRegNum<[29]>;
+def R30 : AVRReg<30, "r30", [], ["zl"]>, DwarfRegNum<[30]>;
+def R31 : AVRReg<31, "r31", [], ["zh"]>, DwarfRegNum<[31]>;
 def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>;
 def SPH : AVRReg<33, "SPH">, DwarfRegNum<[33]>;
 
 let SubRegIndices = [sub_lo, sub_hi],
 CoveredBySubRegs = 1 in
 {
   // 16 bit GPR pairs.
   def SP     : AVRReg<32, "SP",      [SPL, SPH]>, DwarfRegNum<[32]>;

llvm/test/MC/AVR/registers.s

+; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+
+; Test register aliases: the upper 6 registers have aliases that can be used in
+; assembly.
+
+foo:
+  inc xl
+  inc xh
+  inc yl
+  inc yh
+  inc zl
+  inc zh
+
+  inc XL ; test uppercase
+
+; CHECK: inc r26                    ; encoding: [0xa3,0x95]
+; CHECK: inc r27                    ; encoding: [0xb3,0x95]
+; CHECK: inc r28                    ; encoding: [0xc3,0x95]
+; CHECK: inc r29                    ; encoding: [0xd3,0x95]
+; CHECK: inc r30                    ; encoding: [0xe3,0x95]
+; CHECK: inc r31                    ; encoding: [0xf3,0x95]
+
+; CHECK: inc r26                    ; encoding: [0xa3,0x95]
+
+; CHECK-INST: inc r26
+; CHECK-INST: inc r27
+; CHECK-INST: inc r28
+; CHECK-INST: inc r29
+; CHECK-INST: inc r30
+; CHECK-INST: inc r31
+
+; CHECK-INST: inc r26