This is an archive of the discontinued LLVM Phabricator instance.

[AVR] Add register aliases XL, YH, etc
ClosedPublic

Authored by aykevl on Feb 11 2021, 5:11 AM.

Details

Summary

These aliases are sometimes used in assembly code and make the code more readable. They are supported by avr-gcc too.

Diff Detail

Event Timeline

aykevl created this revision.Feb 11 2021, 5:11 AM
aykevl requested review of this revision.Feb 11 2021, 5:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 11 2021, 5:11 AM
benshi001 added inline comments.
llvm/lib/Target/AVR/AVRRegisterInfo.td
70

how about also add alias __tmp_reg__ for R0 and __zero_reg__ for R1 as avr-gcc does?

aykevl added inline comments.Feb 20 2021, 2:41 PM
llvm/lib/Target/AVR/AVRRegisterInfo.td
70

I _think_ this is implemented slightly differently in GCC. For example, if you take a look here (https://godbolt.org/z/sdEcc7) you can see that it defines __tmp_reg__ separately. Also, note that these two registers (__tmp_reg__ and __zero_reg__) are different on "reduced tiny" chips, see https://gcc.gnu.org/wiki/avr-gcc#Reduced_Tiny - I'm not sure this difference can be easily expressed in this register file description.

benshi001 added inline comments.Feb 21 2021, 6:03 AM
llvm/lib/Target/AVR/AVRRegisterInfo.td
70

I see. Thanks.

benshi001 accepted this revision.Feb 21 2021, 6:05 AM
This revision is now accepted and ready to land.Feb 21 2021, 6:05 AM
This revision was landed with ongoing or failed builds.Mar 3 2021, 6:36 AM
This revision was automatically updated to reflect the committed changes.