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Differential D96226

AMDGPU: Stop adding stack passed wide arguments to call conv handler
ClosedPublic

Authored by arsenm on Feb 7 2021, 1:09 PM.

Details

Reviewers
rampitec
Flakebi
madhur13490
Summary

The generated calling convention code shouldn't see these types since
we split large types into 32-bit chunks before the calling convention
code is triggered.




GlobalISel ends up directly calls the generated CC code before

checking for the register count breakdown. Arguably this difference is

a bug, but this was dead code for the DAG anyway.
Diff Detail
Event Timeline
arsenm created this revision.Feb 7 2021, 1:09 PM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others.  ·  View Herald TranscriptFeb 7 2021, 1:09 PM
arsenm requested review of this revision.Feb 7 2021, 1:09 PM
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rampitec accepted this revision.Feb 8 2021, 10:38 AM
This revision is now accepted and ready to land.Feb 8 2021, 10:38 AM
arsenm closed this revision.Feb 8 2021, 2:09 PM
bcf723b2fd6d92e7dd0d7cf4a645a2b1cb974966
Revision Contents
PathSize
llvm/
lib/
Target/
AMDGPU/
24 lines
Diff 322003
llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
Show All 28 Linesdef CC_SI_Gfx : CallingConv<[




  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[

    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,

    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,

    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,

    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31

  ]>>>,
  ]>>>,




  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>

  CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,

  CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,

  CCIfType<[v4i32, v4f32, v2i64, v2f64], CCAssignToStack<16, 4>>,

  CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,

  CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,

  CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>

]>;
]>;




def RetCC_SI_Gfx : CallingConv<[
def RetCC_SI_Gfx : CallingConv<[

  // 0-3 are reserved for the stack buffer descriptor
  // 0-3 are reserved for the stack buffer descriptor

  // 32 is reserved for the stack pointer
  // 32 is reserved for the stack pointer

  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[

    SGPR4, SGPR5, SGPR6, SGPR7,
    SGPR4, SGPR5, SGPR6, SGPR7,

    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,

Show All 18 Lines  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[

    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,

    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,

    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,

    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,

    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,

    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135

  ]>>>,
  ]>>>,




  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>

  CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,

  CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,

  CCIfType<[v4i32, v4f32, v2i64, v2f64], CCAssignToStack<16, 4>>,

  CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,

  CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,

  CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>

]>;
]>;




def CC_SI_SHADER : CallingConv<[
def CC_SI_SHADER : CallingConv<[




  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[

    SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
    SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,

    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,

    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,

▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Linesdef CC_AMDGPU_Func : CallingConv<[

  CCIfByVal<CCPassByVal<4, 4>>,
  CCIfByVal<CCPassByVal<4, 4>>,

  CCIfType<[i1], CCPromoteToType<i32>>,
  CCIfType<[i1], CCPromoteToType<i32>>,

  CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
  CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,

  CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
  CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[

    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,

    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,

    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,

    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,

  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>

  CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,

  CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,

  CCIfType<[v4i32, v4f32, v2i64, v2f64], CCAssignToStack<16, 4>>,

  CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,

  CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,

  CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>

]>;
]>;




// Calling convention for leaf functions
// Calling convention for leaf functions

def RetCC_AMDGPU_Func : CallingConv<[
def RetCC_AMDGPU_Func : CallingConv<[

  CCIfType<[i1], CCPromoteToType<i32>>,
  CCIfType<[i1], CCPromoteToType<i32>>,

  CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
  CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,

  CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[
  CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[

    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,

Show All 15 Lines