Disable Jump Threading for the targets with divergent control flow

[alex-t]

Summary

Details: Jump Threading does not make sense for the targets with divergent CF

since they do not use branch prediction for speculative execution.
Also in the high level IR there is no enough information to conclude that the branch is divergent or uniform.
This may cause errors in further CF lowering.

[rampitec]

Needs test in Transforms/JumpThreading.
Typo in the commit message "unniform".

Otherwise LGTM.

[alex-t]

Test that ensures optimization disabled for the target with divergent CF and enabled otherwise.

[nikic]

llvm/test/Transforms/JumpThreading/divergent-target-test.ll

3

You probably need some REQUIRES for x86 & amdgpu here, otherwise the test may fail if these targets are not built.

[alex-t]

REUIRES x86 && amdgpu clause added in test

[rampitec]

LGTM, but please fix typo in the commit message before submit: "unniform".

llvm/lib/Transforms/Scalar/JumpThreading.cpp

 #include "llvm/Analysis/DomTreeUpdater.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/GuardUtils.h"
 #include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Analysis/LazyValueInfo.h"
 #include "llvm/Analysis/Loads.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/CFG.h"
 #include "llvm/IR/Constant.h"
 #include "llvm/IR/ConstantRange.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Dominators.h"
public:
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<DominatorTreeWrapperPass>();
       AU.addPreserved<DominatorTreeWrapperPass>();
       AU.addRequired<AAResultsWrapperPass>();
       AU.addRequired<LazyValueInfoWrapperPass>();
       AU.addPreserved<LazyValueInfoWrapperPass>();
       AU.addPreserved<GlobalsAAWrapperPass>();
       AU.addRequired<TargetLibraryInfoWrapperPass>();
+      AU.addRequired<TargetTransformInfoWrapperPass>();
     }
 
     void releaseMemory() override { Impl.releaseMemory(); }
   };
 
 } // end anonymous namespace
 
 char JumpThreading::ID = 0;
PredBr->setMetadata(LLVMContext::MD_prof,
                             .createBranchWeights(Weights));
   }
 }
 
 /// runOnFunction - Toplevel algorithm.
 bool JumpThreading::runOnFunction(Function &F) {
   if (skipFunction(F))
     return false;
+  auto TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
+  // Jump Threading has no sense for the targets with divergent CF
+  if (TTI->hasBranchDivergence())
+    return false;
   auto TLI = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
   auto DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
   auto LVI = &getAnalysis<LazyValueInfoWrapperPass>().getLVI();
   auto AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
   DomTreeUpdater DTU(*DT, DomTreeUpdater::UpdateStrategy::Lazy);
   std::unique_ptr<BlockFrequencyInfo> BFI;
   std::unique_ptr<BranchProbabilityInfo> BPI;
   if (F.hasProfileData()) {

llvm/test/Transforms/JumpThreading/divergent-target-test.ll

+; REQUIRES: amdgpu-registered-target && x86-registered-target
+; RUN: opt < %s -mtriple=amdgcn -jump-threading -S | FileCheck %s  -check-prefixes=CHECK,DIVERGENT
+; RUN: opt < %s -mtriple=x86_64 -jump-threading -S | FileCheck %s  -check-prefixes=CHECK,UNIFORM
+
+; Here we assure that for the target with no branch divergence usual Jump Threading optimization performed
+; For target with branch divergence - no optimization, so the IR is unchanged.
+
+declare i32 @f1()
+declare i32 @f2()
+declare void @f3()
+
+define i32 @test(i1 %cond) {
+; CHECK: test
+  br i1 %cond, label %T1, label %F1
+
+; DIVERGENT:   T1
+; UNIFORM-NOT: T1
+T1:
+  %v1 = call i32 @f1()
+  br label %Merge
+; DIVERGENT:   F1
+; UNIFORM-NOT: F1
+F1:
+  %v2 = call i32 @f2()
+  br label %Merge
+; DIVERGENT:   Merge
+; UNIFORM-NOT: Merge
+Merge:
+  %A = phi i1 [true, %T1], [false, %F1]
+  %B = phi i32 [%v1, %T1], [%v2, %F1]
+  br i1 %A, label %T2, label %F2
+
+; DIVERGENT:   T2
+T2:
+; UNIFORM: T2:
+; UNIFORM: %v1 = call i32 @f1()
+; UNIFORM: call void @f3()
+; UNIFORM: ret i32 %v1
+  call void @f3()
+  ret i32 %B
+; DIVERGENT:   F2
+F2:
+; UNIFORM: F2:
+; UNIFORM: %v2 = call i32 @f2()
+; UNIFORM: ret i32 %v2
+  ret i32 %B
+}