[GlobalISel] Avoid asserting when SizeOp0 isn't an exact multiple of NarrowSize

[nikic]

Summary

Addresses https://bugs.llvm.org/show_bug.cgi?id=48188

[shepmaster]

Ideally, this would target the 11.x branch as I'd like to cherry-pick it into the Rust project to address our upstream issue (https://github.com/rust-lang/rust/issues/78881)

[arsenm]

Needs testcase

[shepmaster]

There’s an LLVM IR attached to the big report that crashes, but I don’t know how to create a test case from it.

It also seems like it’s brittle because the test passes on the current development branch even though no apparent relevant code change has occurred.

I’m seeking advice on how to create the test.

[nikic]

Add test case. As we're testing SDAG fallback here, I assumed that an IR test case is appropriate.

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

case TargetOpcode::G_PTRTOINT:
     if (TypeIdx != 0)
       return UnableToLegalize;
 
     Observer.changingInstr(MI);
     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
     Observer.changedInstr(MI);
     return Legalized;
   case TargetOpcode::G_PHI: {
+    // FIXME: add support for when SizeOp0 isn't an exact multiple of
+    // NarrowSize.
+    if (SizeOp0 % NarrowSize != 0)
+      return UnableToLegalize;
+
     unsigned NumParts = SizeOp0 / NarrowSize;
     SmallVector<Register, 2> DstRegs(NumParts);
     SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2);
     Observer.changingInstr(MI);
     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,

llvm/test/CodeGen/AArch64/pr48188.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+
+; GlobalISel cannot legalize this phi, so we fall back to SDAG.
+define void @test() nounwind {
+; CHECK-LABEL: test:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sub sp, sp, #16 // =16
+; CHECK-NEXT:    mov x1, xzr
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    str x1, [sp] // 8-byte Folded Spill
+; CHECK-NEXT:    str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-NEXT:    b .LBB0_1
+; CHECK-NEXT:  .LBB0_1: // %loop
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-NEXT:    ldr x1, [sp] // 8-byte Folded Reload
+; CHECK-NEXT:    str x1, [sp] // 8-byte Folded Spill
+; CHECK-NEXT:    str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-NEXT:    b .LBB0_1
+entry:
+  br label %loop
+
+loop:
+  %p = phi i72 [ 0, %entry ], [ %p, %loop ]
+  br label %loop
+}