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Differential D92313

[VE] Optimize prologue/epilogue instructions about GOT
ClosedPublic

Authored by kaz7 on Nov 30 2020, 5:33 AM.

Details

Reviewers
simoll
k-ishizaka
Commits
rG6834b3d6d52a: [VE] Optimize prologue/epilogue instructions about GOT
Summary

Optimize prologue/epilogue instructions if a given function use GOT but
do not call other functions by eliminating FP. Previously, we had wrong
implementations taken from other architectures. Update regression tests
also.

Diff Detail

Event Timeline

kaz7 created this revision.Nov 30 2020, 5:33 AM
Herald added subscribers: llvm-commits, hiraditya. · View Herald TranscriptNov 30 2020, 5:33 AM
kaz7 requested review of this revision.Nov 30 2020, 5:33 AM
simoll accepted this revision.Nov 30 2020, 5:55 AM
This revision is now accepted and ready to land.Nov 30 2020, 5:55 AM
Harbormaster completed remote builds in B80516: Diff 308336.Nov 30 2020, 6:09 AM
Closed by commit rG6834b3d6d52a: [VE] Optimize prologue/epilogue instructions about GOT (authored by kaz7). · Explain WhyNov 30 2020, 9:22 AM
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rG6834b3d6d52a: [VE] Optimize prologue/epilogue instructions about GOT.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
4 lines
test/
CodeGen/
VE/
Scalar/
32 lines
18 lines
8 lines
8 lines
31 lines

Diff 308396

llvm/lib/Target/VE/VEISelLowering.cpp

Show First 20 Lines • Show All 907 Lines • ▼ Show 20 Lines
// Build SDNodes for producing an address from a GlobalAddress, ConstantPool, // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
// or ExternalSymbol SDNode. // or ExternalSymbol SDNode.
SDValue VETargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { SDValue VETargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
EVT PtrVT = Op.getValueType(); EVT PtrVT = Op.getValueType();
// Handle PIC mode first. VE needs a got load for every variable! // Handle PIC mode first. VE needs a got load for every variable!
if (isPositionIndependent()) { if (isPositionIndependent()) {
// GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
// function has calls.
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
MFI.setHasCalls(true);
auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op); auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op);
if (isa<ConstantPoolSDNode>(Op) || isa<JumpTableSDNode>(Op) || if (isa<ConstantPoolSDNode>(Op) || isa<JumpTableSDNode>(Op) ||
(GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) { (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
// Create following instructions for local linkage PIC code. // Create following instructions for local linkage PIC code.
// lea %reg, label@gotoff_lo // lea %reg, label@gotoff_lo
// and %reg, %reg, (32)0 // and %reg, %reg, (32)0
// lea.sl %reg, label@gotoff_hi(%reg, %got) // lea.sl %reg, label@gotoff_hi(%reg, %got)
▲ Show 20 Lines • Show All 807 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/Scalar/br_jt.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lea.sl %s1, .Lswitch.table.br_jt4@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, .Lswitch.table.br_jt4@hi(, %s1)
; CHECK-NEXT: ldl.sx %s0, (%s0, %s1) ; CHECK-NEXT: ldl.sx %s0, (%s0, %s1)
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; ;
; PIC-LABEL: br_jt4: ; PIC-LABEL: br_jt4:
; PIC: .LBB{{[0-9]+}}_5: ; PIC: # %bb.0:
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: and %s0, %s0, (32)0 ; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: adds.w.sx %s1, -1, %s0 ; PIC-NEXT: adds.w.sx %s1, -1, %s0
; PIC-NEXT: cmpu.w %s2, 3, %s1 ; PIC-NEXT: cmpu.w %s2, 3, %s1
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16 ; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: brgt.w 0, %s2, .LBB1_2 ; PIC-NEXT: brgt.w 0, %s2, .LBB1_2
; PIC-NEXT: # %bb.1: ; PIC-NEXT: # %bb.1:
; PIC-NEXT: adds.w.sx %s0, %s1, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s1, (0)1
; PIC-NEXT: sll %s0, %s0, 2 ; PIC-NEXT: sll %s0, %s0, 2
; PIC-NEXT: lea %s1, .Lswitch.table.br_jt4@gotoff_lo ; PIC-NEXT: lea %s1, .Lswitch.table.br_jt4@gotoff_lo
; PIC-NEXT: and %s1, %s1, (32)0 ; PIC-NEXT: and %s1, %s1, (32)0
; PIC-NEXT: lea.sl %s1, .Lswitch.table.br_jt4@gotoff_hi(%s1, %s15) ; PIC-NEXT: lea.sl %s1, .Lswitch.table.br_jt4@gotoff_hi(%s1, %s15)
; PIC-NEXT: ldl.sx %s0, (%s0, %s1) ; PIC-NEXT: ldl.sx %s0, (%s0, %s1)
; PIC-NEXT: br.l.t .LBB1_3 ; PIC-NEXT: br.l.t .LBB1_3
; PIC-NEXT: .LBB1_2: ; PIC-NEXT: .LBB1_2:
; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
; PIC-NEXT: .LBB1_3: ; PIC-NEXT: .LBB1_3:
; PIC-NEXT: or %s11, 0, %s9 ; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: b.l.t (, %s10)
%2 = add i32 %0, -1 %2 = add i32 %0, -1
%3 = icmp ult i32 %2, 4 %3 = icmp ult i32 %2, 4
br i1 %3, label %4, label %8 br i1 %3, label %4, label %8
4: ; preds = %1 4: ; preds = %1
%5 = sext i32 %2 to i64 %5 = sext i32 %2 to i64
%6 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.br_jt4, i64 0, i64 %5 %6 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.br_jt4, i64 0, i64 %5
%7 = load i32, i32* %6, align 4 %7 = load i32, i32* %6, align 4
Show All 26 Lines
; CHECK-NEXT: sll %s0, %s0, 2 ; CHECK-NEXT: sll %s0, %s0, 2
; CHECK-NEXT: lea %s1, .Lswitch.table.br_jt7@lo ; CHECK-NEXT: lea %s1, .Lswitch.table.br_jt7@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .Lswitch.table.br_jt7@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, .Lswitch.table.br_jt7@hi(, %s1)
; CHECK-NEXT: ldl.sx %s0, (%s0, %s1) ; CHECK-NEXT: ldl.sx %s0, (%s0, %s1)
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; ;
; PIC-LABEL: br_jt7: ; PIC-LABEL: br_jt7:
; PIC: .LBB{{[0-9]+}}_6: ; PIC: # %bb.0:
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: and %s0, %s0, (32)0 ; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: adds.w.sx %s1, -1, %s0 ; PIC-NEXT: adds.w.sx %s1, -1, %s0
; PIC-NEXT: cmpu.w %s2, 8, %s1 ; PIC-NEXT: cmpu.w %s2, 8, %s1
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16 ; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: brgt.w 0, %s2, .LBB2_3 ; PIC-NEXT: brgt.w 0, %s2, .LBB2_3
Show All 10 Lines
; PIC-NEXT: .LBB2_2: ; PIC-NEXT: .LBB2_2:
; PIC-NEXT: adds.w.sx %s0, %s1, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s1, (0)1
; PIC-NEXT: sll %s0, %s0, 2 ; PIC-NEXT: sll %s0, %s0, 2
; PIC-NEXT: lea %s1, .Lswitch.table.br_jt7@gotoff_lo ; PIC-NEXT: lea %s1, .Lswitch.table.br_jt7@gotoff_lo
; PIC-NEXT: and %s1, %s1, (32)0 ; PIC-NEXT: and %s1, %s1, (32)0
; PIC-NEXT: lea.sl %s1, .Lswitch.table.br_jt7@gotoff_hi(%s1, %s15) ; PIC-NEXT: lea.sl %s1, .Lswitch.table.br_jt7@gotoff_hi(%s1, %s15)
; PIC-NEXT: ldl.sx %s0, (%s0, %s1) ; PIC-NEXT: ldl.sx %s0, (%s0, %s1)
; PIC-NEXT: .LBB2_4: ; PIC-NEXT: .LBB2_4:
; PIC-NEXT: or %s11, 0, %s9 ; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: b.l.t (, %s10)
%2 = add i32 %0, -1 %2 = add i32 %0, -1
%3 = icmp ult i32 %2, 9 %3 = icmp ult i32 %2, 9
br i1 %3, label %4, label %13 br i1 %3, label %4, label %13
4: ; preds = %1 4: ; preds = %1
%5 = trunc i32 %2 to i16 %5 = trunc i32 %2 to i16
%6 = lshr i16 463, %5 %6 = lshr i16 463, %5
%7 = and i16 %6, 1 %7 = and i16 %6, 1
Show All 33 Lines
; CHECK-NEXT: sll %s0, %s0, 2 ; CHECK-NEXT: sll %s0, %s0, 2
; CHECK-NEXT: lea %s1, .Lswitch.table.br_jt8@lo ; CHECK-NEXT: lea %s1, .Lswitch.table.br_jt8@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .Lswitch.table.br_jt8@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, .Lswitch.table.br_jt8@hi(, %s1)
; CHECK-NEXT: ldl.sx %s0, (%s0, %s1) ; CHECK-NEXT: ldl.sx %s0, (%s0, %s1)
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; ;
; PIC-LABEL: br_jt8: ; PIC-LABEL: br_jt8:
; PIC: .LBB{{[0-9]+}}_6: ; PIC: # %bb.0:
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: and %s0, %s0, (32)0 ; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: adds.w.sx %s1, -1, %s0 ; PIC-NEXT: adds.w.sx %s1, -1, %s0
; PIC-NEXT: cmpu.w %s2, 8, %s1 ; PIC-NEXT: cmpu.w %s2, 8, %s1
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16 ; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: brgt.w 0, %s2, .LBB3_3 ; PIC-NEXT: brgt.w 0, %s2, .LBB3_3
Show All 10 Lines
; PIC-NEXT: .LBB3_2: ; PIC-NEXT: .LBB3_2:
; PIC-NEXT: adds.w.sx %s0, %s1, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s1, (0)1
; PIC-NEXT: sll %s0, %s0, 2 ; PIC-NEXT: sll %s0, %s0, 2
; PIC-NEXT: lea %s1, .Lswitch.table.br_jt8@gotoff_lo ; PIC-NEXT: lea %s1, .Lswitch.table.br_jt8@gotoff_lo
; PIC-NEXT: and %s1, %s1, (32)0 ; PIC-NEXT: and %s1, %s1, (32)0
; PIC-NEXT: lea.sl %s1, .Lswitch.table.br_jt8@gotoff_hi(%s1, %s15) ; PIC-NEXT: lea.sl %s1, .Lswitch.table.br_jt8@gotoff_hi(%s1, %s15)
; PIC-NEXT: ldl.sx %s0, (%s0, %s1) ; PIC-NEXT: ldl.sx %s0, (%s0, %s1)
; PIC-NEXT: .LBB3_4: ; PIC-NEXT: .LBB3_4:
; PIC-NEXT: or %s11, 0, %s9 ; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: b.l.t (, %s10)
%2 = add i32 %0, -1 %2 = add i32 %0, -1
%3 = icmp ult i32 %2, 9 %3 = icmp ult i32 %2, 9
br i1 %3, label %4, label %13 br i1 %3, label %4, label %13
4: ; preds = %1 4: ; preds = %1
%5 = trunc i32 %2 to i16 %5 = trunc i32 %2 to i16
%6 = lshr i16 495, %5 %6 = lshr i16 495, %5
%7 = and i16 %6, 1 %7 = and i16 %6, 1
▲ Show 20 Lines • Show All 349 Lines • ▼ Show 20 Lines
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_7: ; CHECK-NEXT: .LBB{{[0-9]+}}_7:
; CHECK-NEXT: or %s0, 10, (0)1 ; CHECK-NEXT: or %s0, 10, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; ;
; PIC-LABEL: br_jt8_m: ; PIC-LABEL: br_jt8_m:
; PIC: .LBB{{[0-9]+}}_12: ; PIC: # %bb.0:
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: and %s2, %s0, (32)0 ; PIC-NEXT: and %s2, %s0, (32)0
; PIC-NEXT: adds.w.sx %s0, -1, %s2 ; PIC-NEXT: adds.w.sx %s0, -1, %s2
; PIC-NEXT: cmpu.w %s3, 8, %s0 ; PIC-NEXT: cmpu.w %s3, 8, %s0
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16 ; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: brgt.w 0, %s3, .LBB7_9 ; PIC-NEXT: brgt.w 0, %s3, .LBB7_9
Show All 31 Lines
; PIC-NEXT: br.l.t .LBB7_10 ; PIC-NEXT: br.l.t .LBB7_10
; PIC-NEXT: .LBB7_8: ; PIC-NEXT: .LBB7_8:
; PIC-NEXT: or %s0, 11, (0)1 ; PIC-NEXT: or %s0, 11, (0)1
; PIC-NEXT: br.l.t .LBB7_10 ; PIC-NEXT: br.l.t .LBB7_10
; PIC-NEXT: .LBB7_7: ; PIC-NEXT: .LBB7_7:
; PIC-NEXT: or %s0, 10, (0)1 ; PIC-NEXT: or %s0, 10, (0)1
; PIC-NEXT: .LBB7_10: ; PIC-NEXT: .LBB7_10:
; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
; PIC-NEXT: or %s11, 0, %s9 ; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: b.l.t (, %s10)
switch i32 %0, label %13 [ switch i32 %0, label %13 [
i32 1, label %14 i32 1, label %14
i32 2, label %3 i32 2, label %3
i32 3, label %4 i32 3, label %4
i32 4, label %5 i32 4, label %5
i32 6, label %7 i32 6, label %7
i32 7, label %9 i32 7, label %9
i32 9, label %11 i32 9, label %11
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llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll

Show All 22 Lines
; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; ;
; PIC-LABEL: func_gv: ; PIC-LABEL: func_gv:
; PIC: # %bb.0: ; PIC: # %bb.0:
; PIC-NEXT: st %s9, (, %s11)
; PIC-NEXT: st %s10, 8(, %s11)
; PIC-NEXT: st %s15, 24(, %s11) ; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11) ; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: or %s9, 0, %s11
; PIC-NEXT: lea %s11, -176(, %s11)
; PIC-NEXT: brge.l.t %s11, %s8, .LBB1_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT: ld %s61, 24(, %s14)
; PIC-NEXT: or %s62, 0, %s0
; PIC-NEXT: lea %s63, 315
; PIC-NEXT: shm.l %s63, (%s61)
; PIC-NEXT: shm.l %s8, 8(%s61)
; PIC-NEXT: shm.l %s11, 16(%s61)
; PIC-NEXT: monc
; PIC-NEXT: or %s0, 0, %s62
; PIC-NEXT: .LBB1_2:
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16 ; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: lea %s0, vi8@got_lo ; PIC-NEXT: lea %s0, vi8@got_lo
; PIC-NEXT: and %s0, %s0, (32)0 ; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: lea.sl %s0, vi8@got_hi(, %s0) ; PIC-NEXT: lea.sl %s0, vi8@got_hi(, %s0)
; PIC-NEXT: ld %s0, (%s0, %s15) ; PIC-NEXT: ld %s0, (%s0, %s15)
; PIC-NEXT: ld1b.zx %s0, (, %s0) ; PIC-NEXT: ld1b.zx %s0, (, %s0)
; PIC-NEXT: or %s11, 0, %s9
; PIC-NEXT: ld %s16, 32(, %s11) ; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11) ; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: ld %s10, 8(, %s11)
; PIC-NEXT: ld %s9, (, %s11)
; PIC-NEXT: b.l.t (, %s10) ; PIC-NEXT: b.l.t (, %s10)
%v = load i8, i8* @vi8, align 1 %v = load i8, i8* @vi8, align 1
ret i8 %v ret i8 %v
} }
define i32 @func_alloca(i32 signext %0) { define i32 @func_alloca(i32 signext %0) {
; CHECK-LABEL: func_alloca: ; CHECK-LABEL: func_alloca:
Show All 39 Lines

llvm/test/CodeGen/VE/Scalar/pic_access_data.ll

; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s
@dst = external global i32, align 4 @dst = external global i32, align 4
@ptr = external global i32*, align 8 @ptr = external global i32*, align 8
@src = external global i32, align 4 @src = external global i32, align 4
define i32 @func() { define i32 @func() {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; CHECK-NEXT: and %s15, %s15, (32)0 ; CHECK-NEXT: and %s15, %s15, (32)0
; CHECK-NEXT: sic %s16 ; CHECK-NEXT: sic %s16
; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; CHECK-NEXT: lea %s0, dst@got_lo ; CHECK-NEXT: lea %s0, dst@got_lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, dst@got_hi(, %s0) ; CHECK-NEXT: lea.sl %s0, dst@got_hi(, %s0)
; CHECK-NEXT: ld %s1, (%s0, %s15) ; CHECK-NEXT: ld %s1, (%s0, %s15)
; CHECK-NEXT: lea %s0, ptr@got_lo ; CHECK-NEXT: lea %s0, ptr@got_lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s2, src@got_lo ; CHECK-NEXT: lea %s2, src@got_lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, src@got_hi(, %s2) ; CHECK-NEXT: lea.sl %s2, src@got_hi(, %s2)
; CHECK-NEXT: ld %s2, (%s2, %s15) ; CHECK-NEXT: ld %s2, (%s2, %s15)
; CHECK-NEXT: lea.sl %s0, ptr@got_hi(, %s0) ; CHECK-NEXT: lea.sl %s0, ptr@got_hi(, %s0)
; CHECK-NEXT: ld %s0, (%s0, %s15) ; CHECK-NEXT: ld %s0, (%s0, %s15)
; CHECK-NEXT: ldl.sx %s2, (, %s2) ; CHECK-NEXT: ldl.sx %s2, (, %s2)
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: stl %s2, (, %s1) ; CHECK-NEXT: stl %s2, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: b.l.t (, %s10)
store i32* @dst, i32** @ptr, align 8 store i32* @dst, i32** @ptr, align 8
%1 = load i32, i32* @src, align 4 %1 = load i32, i32* @src, align 4
store i32 %1, i32* @dst, align 4 store i32 %1, i32* @dst, align 4
ret i32 1 ret i32 1
} }

llvm/test/CodeGen/VE/Scalar/pic_access_static_data.ll

; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s
@dst = internal unnamed_addr global i32 0, align 4 @dst = internal unnamed_addr global i32 0, align 4
@src = internal unnamed_addr global i1 false, align 4 @src = internal unnamed_addr global i1 false, align 4
@.str = private unnamed_addr constant [3 x i8] c"%d\00", align 1 @.str = private unnamed_addr constant [3 x i8] c"%d\00", align 1
define void @func() { define void @func() {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; CHECK-NEXT: and %s15, %s15, (32)0 ; CHECK-NEXT: and %s15, %s15, (32)0
; CHECK-NEXT: sic %s16 ; CHECK-NEXT: sic %s16
; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; CHECK-NEXT: lea %s0, src@gotoff_lo ; CHECK-NEXT: lea %s0, src@gotoff_lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, src@gotoff_hi(, %s0) ; CHECK-NEXT: lea.sl %s0, src@gotoff_hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (%s0, %s15) ; CHECK-NEXT: ld1b.zx %s0, (%s0, %s15)
; CHECK-NEXT: lea %s1, 100 ; CHECK-NEXT: lea %s1, 100
; CHECK-NEXT: cmov.w.eq %s1, (0)1, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (0)1, %s0
; CHECK-NEXT: lea %s0, dst@gotoff_lo ; CHECK-NEXT: lea %s0, dst@gotoff_lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, dst@gotoff_hi(, %s0) ; CHECK-NEXT: lea.sl %s0, dst@gotoff_hi(, %s0)
; CHECK-NEXT: stl %s1, (%s0, %s15) ; CHECK-NEXT: stl %s1, (%s0, %s15)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i1, i1* @src, align 4 %1 = load i1, i1* @src, align 4
%2 = select i1 %1, i32 100, i32 0 %2 = select i1 %1, i32 100, i32 0
store i32 %2, i32* @dst, align 4 store i32 %2, i32* @dst, align 4
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
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llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, data@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, data@hi(, %s1)
; CHECK-NEXT: ld1b.zx %s1, (, %s1) ; CHECK-NEXT: ld1b.zx %s1, (, %s1)
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; ;
; PIC-LABEL: test_frame0_var: ; PIC-LABEL: test_frame0_var:
; PIC: # %bb.0: ; PIC: # %bb.0:
; PIC-NEXT: st %s9, (, %s11)
; PIC-NEXT: st %s10, 8(, %s11)
; PIC-NEXT: st %s15, 24(, %s11) ; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11) ; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: or %s9, 0, %s11
; PIC-NEXT: lea %s11, -176(, %s11)
; PIC-NEXT: brge.l.t %s11, %s8, .LBB3_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT: ld %s61, 24(, %s14)
; PIC-NEXT: or %s62, 0, %s0
; PIC-NEXT: lea %s63, 315
; PIC-NEXT: shm.l %s63, (%s61)
; PIC-NEXT: shm.l %s8, 8(%s61)
; PIC-NEXT: shm.l %s11, 16(%s61)
; PIC-NEXT: monc
; PIC-NEXT: or %s0, 0, %s62
; PIC-NEXT: .LBB3_2:
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16 ; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: lea %s1, data@got_lo ; PIC-NEXT: lea %s1, data@got_lo
; PIC-NEXT: and %s1, %s1, (32)0 ; PIC-NEXT: and %s1, %s1, (32)0
; PIC-NEXT: lea.sl %s1, data@got_hi(, %s1) ; PIC-NEXT: lea.sl %s1, data@got_hi(, %s1)
; PIC-NEXT: ld %s1, (%s1, %s15) ; PIC-NEXT: ld %s1, (%s1, %s15)
; PIC-NEXT: ld1b.zx %s1, (, %s1) ; PIC-NEXT: ld1b.zx %s1, (, %s1)
; PIC-NEXT: st1b %s1, (, %s0) ; PIC-NEXT: st1b %s1, (, %s0)
; PIC-NEXT: or %s11, 0, %s9
; PIC-NEXT: ld %s16, 32(, %s11) ; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11) ; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: ld %s10, 8(, %s11)
; PIC-NEXT: ld %s9, (, %s11)
; PIC-NEXT: b.l.t (, %s10) ; PIC-NEXT: b.l.t (, %s10)
%3 = load i8, i8* @data, align 1 %3 = load i8, i8* @data, align 1
store i8 %3, i8* %0, align 1 store i8 %3, i8* %0, align 1
ret i8* %0 ret i8* %0
} }
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define nonnull i8* @test_frame32_var(i8* nocapture readnone %0) { define nonnull i8* @test_frame32_var(i8* nocapture readnone %0) {
Show All 17 Lines
; CHECK-NEXT: ld1b.zx %s1, (, %s0) ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
; CHECK-NEXT: lea %s0, (, %s11) ; CHECK-NEXT: lea %s0, (, %s11)
; CHECK-NEXT: st1b %s1, (, %s11) ; CHECK-NEXT: st1b %s1, (, %s11)
; CHECK-NEXT: adds.l %s11, 32, %s11 ; CHECK-NEXT: adds.l %s11, 32, %s11
; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: b.l.t (, %s10)
; ;
; PIC-LABEL: test_frame32_var: ; PIC-LABEL: test_frame32_var:
; PIC: # %bb.0: ; PIC: # %bb.0:
; PIC-NEXT: st %s9, (, %s11)
; PIC-NEXT: st %s10, 8(, %s11)
; PIC-NEXT: st %s15, 24(, %s11) ; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11) ; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: or %s9, 0, %s11 ; PIC-NEXT: adds.l %s11, -32, %s11
; PIC-NEXT: lea %s11, -208(, %s11)
; PIC-NEXT: brge.l.t %s11, %s8, .LBB4_2 ; PIC-NEXT: brge.l.t %s11, %s8, .LBB4_2
; PIC-NEXT: # %bb.1: ; PIC-NEXT: # %bb.1:
; PIC-NEXT: ld %s61, 24(, %s14) ; PIC-NEXT: ld %s61, 24(, %s14)
; PIC-NEXT: or %s62, 0, %s0 ; PIC-NEXT: or %s62, 0, %s0
; PIC-NEXT: lea %s63, 315 ; PIC-NEXT: lea %s63, 315
; PIC-NEXT: shm.l %s63, (%s61) ; PIC-NEXT: shm.l %s63, (%s61)
; PIC-NEXT: shm.l %s8, 8(%s61) ; PIC-NEXT: shm.l %s8, 8(%s61)
; PIC-NEXT: shm.l %s11, 16(%s61) ; PIC-NEXT: shm.l %s11, 16(%s61)
; PIC-NEXT: monc ; PIC-NEXT: monc
; PIC-NEXT: or %s0, 0, %s62 ; PIC-NEXT: or %s0, 0, %s62
; PIC-NEXT: .LBB4_2: ; PIC-NEXT: .LBB4_2:
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16 ; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: lea %s0, data@got_lo ; PIC-NEXT: lea %s0, data@got_lo
; PIC-NEXT: and %s0, %s0, (32)0 ; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: lea.sl %s0, data@got_hi(, %s0) ; PIC-NEXT: lea.sl %s0, data@got_hi(, %s0)
; PIC-NEXT: ld %s0, (%s0, %s15) ; PIC-NEXT: ld %s0, (%s0, %s15)
; PIC-NEXT: ld1b.zx %s1, (, %s0) ; PIC-NEXT: ld1b.zx %s1, (, %s0)
; PIC-NEXT: lea %s0, 176(, %s11) ; PIC-NEXT: lea %s0, (, %s11)
; PIC-NEXT: st1b %s1, 176(, %s11) ; PIC-NEXT: st1b %s1, (, %s11)
; PIC-NEXT: or %s11, 0, %s9 ; PIC-NEXT: adds.l %s11, 32, %s11
; PIC-NEXT: ld %s16, 32(, %s11) ; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11) ; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: ld %s10, 8(, %s11)
; PIC-NEXT: ld %s9, (, %s11)
; PIC-NEXT: b.l.t (, %s10) ; PIC-NEXT: b.l.t (, %s10)
%2 = alloca [32 x i8], align 1 %2 = alloca [32 x i8], align 1
%3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0 %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0
call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %3) call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %3)
%4 = load i8, i8* @data, align 1 %4 = load i8, i8* @data, align 1
store volatile i8 %4, i8* %3, align 1 store volatile i8 %4, i8* %3, align 1
call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %3) call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %3)
ret i8* %3 ret i8* %3
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