ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.

[pcc]

Summary

This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

[rengolin]

Small comment, otherwise, looks good to me.

cheers,
--renato

test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll

11

This change looks unrelated, do you know why it happens?

[pcc]

test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll

11

I am not sure exactly. It looks like in this case (and a few others elsewhere) the code is computing a frame pointer in r7 by taking the address of the spilled r7 value. (I don't entirely understand why we compute the frame pointer address this way.) If I look at the rest of the uses of r7, they seem fine, accounting for the change in offset.

[rengolin]

LGTM, Thanks!

test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll

11

Right, makes sense. Not seeing the whole assembly output made me worry. :)

lib/Target/ARM/ARMFrameLowering.cpp

if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
     // If stack and double are 8-byte aligned and we are spilling an odd number
     // of GPRs, spill one extra callee save GPR so we won't have to pad between
     // the integer and double callee save areas.
     unsigned TargetAlign = getStackAlignment();
     if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
       if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
         for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
           unsigned Reg = UnspilledCS1GPRs[i];
-          // Don't spill high register if the function is thumb1
-          if (!AFI->isThumb1OnlyFunction() ||
+          // Don't spill high register if the function is thumb
+          if (!AFI->isThumbFunction() ||
               isARMLowRegister(Reg) || Reg == ARM::LR) {
             MRI.setPhysRegUsed(Reg);
             if (!MRI.isReserved(Reg))
               ExtraCSSpill = true;
             break;
           }
         }
       } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {

test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll

define void @foo2(double %p0, ; --> D0
       double %p5, ; --> D5
       double %p6, ; --> D6
       double %p7, ; --> D7
       double %p8, ; --> Stack
       i32 %p9,    ; --> R0
                   %struct_t* byval %p10) ; --> Stack+8
 {
 entry:
-;CHECK:     push.w {r11, lr}
+;CHECK:     push {r7, lr}
 ;CHECK-NOT: stm
 ;CHECK:     add r0, sp, #16
 ;CHECK:     bl fooUseStruct
   call void @fooUseStruct(%struct_t* %p10)
 
   ret void
 }
 

test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll

define void @foo(double %vfp0,     ; --> D0,     NSAA=SP
      double %vfp7,     ; --> D7,     NSAA=SP
      double %vfp8,     ; --> SP,     NSAA=SP+8 (!)
                  i32 %p0,          ; --> R0,     NSAA=SP+8 
      %st_t* byval %p1, ; --> R1, R2, NSAA=SP+8
      i32 %p2,          ; --> R3,     NSAA=SP+8 
                  i32 %p3) #0 {     ; --> SP+4,   NSAA=SP+12
 entry:
   ;CHECK: sub sp, #12
-  ;CHECK: push.w {r11, lr}
+  ;CHECK: push {r7, lr}
   ;CHECK: sub sp, #4
   ;CHECK: add r0, sp, #12
   ;CHECK: str r2, [sp, #16]
   ;CHECK: str r1, [sp, #12]
   ;CHECK: bl  fooUseStruct
   call void @fooUseStruct(%st_t* %p1)
   ret void
 }

test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll

define void @foo(double %vfp0,     ; --> D0,              NSAA=SP
      double %vfp6,     ; --> D6,              NSAA=SP
      double %vfp7,     ; --> D7,              NSAA=SP
      double %vfp8,     ; --> SP,              NSAA=SP+8 (!)
                  i32 %p0,          ; --> R0,              NSAA=SP+8 
      %st_t* byval %p1, ; --> SP+8, 4 words    NSAA=SP+24
      i32 %p2) #0 {     ; --> SP+24,           NSAA=SP+24 
                  
 entry:
-  ;CHECK:  push.w {r11, lr}
+  ;CHECK:  push {r7, lr}
   ;CHECK:  ldr    r0, [sp, #32]
   ;CHECK:  bl     fooUseI32
   call void @fooUseI32(i32 %p2)
   ret void
 }
 
 declare void @fooUseI32(i32)
 

test/CodeGen/ARM/debug-frame.ll

 ; CHECK-THUMB-FP-ELIM:   .cfi_offset r5, -16
 ; CHECK-THUMB-FP-ELIM:   .cfi_offset r4, -20
 ; CHECK-THUMB-FP-ELIM:   sub    sp, #60
 ; CHECK-THUMB-FP-ELIM:   .cfi_def_cfa_offset 80
 ; CHECK-THUMB-FP-ELIM:   .cfi_endproc
 
 ; CHECK-THUMB-V7-FP-LABEL: _Z4testiiiiiddddd:
 ; CHECK-THUMB-V7-FP:   .cfi_startproc
-; CHECK-THUMB-V7-FP:   push.w   {r4, r7, r11, lr}
+; CHECK-THUMB-V7-FP:   push   {r4, r6, r7, lr}
 ; CHECK-THUMB-V7-FP:   .cfi_def_cfa_offset 16
 ; CHECK-THUMB-V7-FP:   .cfi_offset lr, -4
-; CHECK-THUMB-V7-FP:   .cfi_offset r11, -8
-; CHECK-THUMB-V7-FP:   .cfi_offset r7, -12
+; CHECK-THUMB-V7-FP:   .cfi_offset r7, -8
+; CHECK-THUMB-V7-FP:   .cfi_offset r6, -12
 ; CHECK-THUMB-V7-FP:   .cfi_offset r4, -16
-; CHECK-THUMB-V7-FP:   add    r7, sp, #4
-; CHECK-THUMB-V7-FP:   .cfi_def_cfa r7, 12
+; CHECK-THUMB-V7-FP:   add    r7, sp, #8
+; CHECK-THUMB-V7-FP:   .cfi_def_cfa r7, 8
 ; CHECK-THUMB-V7-FP:   vpush  {d8, d9, d10, d11, d12}
 ; CHECK-THUMB-V7-FP:   .cfi_offset d12, -24
 ; CHECK-THUMB-V7-FP:   .cfi_offset d11, -32
 ; CHECK-THUMB-V7-FP:   .cfi_offset d10, -40
 ; CHECK-THUMB-V7-FP:   .cfi_offset d9, -48
 ; CHECK-THUMB-V7-FP:   .cfi_offset d8, -56
 ; CHECK-THUMB-V7-FP:   sub    sp, #24
 ; CHECK-THUMB-V7-FP:   .cfi_endproc

 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset d9, -40
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset d8, -48
 ; CHECK-THUMB-V7-FP-ELIM:   sub    sp, #24
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_def_cfa_offset 72
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_endproc
 
 ; CHECK-THUMB-V7-FP-NOIAS-LABEL: _Z4testiiiiiddddd:
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_startproc
-; CHECK-THUMB-V7-FP-NOIAS:   push.w   {r4, r7, r11, lr}
+; CHECK-THUMB-V7-FP-NOIAS:   push   {r4, r6, r7, lr}
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_def_cfa_offset 16
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 14, -4
-; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 11, -8
-; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 7, -12
+; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 7, -8
+; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 6, -12
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 4, -16
-; CHECK-THUMB-V7-FP-NOIAS:   add    r7, sp, #4
-; CHECK-THUMB-V7-FP-NOIAS:   .cfi_def_cfa 7, 12
+; CHECK-THUMB-V7-FP-NOIAS:   add    r7, sp, #8
+; CHECK-THUMB-V7-FP-NOIAS:   .cfi_def_cfa 7, 8
 ; CHECK-THUMB-V7-FP-NOIAS:   vpush  {d8, d9, d10, d11, d12}
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 268, -24
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 267, -32
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 266, -40
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 265, -48
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_offset 264, -56
 ; CHECK-THUMB-V7-FP-NOIAS:   sub    sp, #24
 ; CHECK-THUMB-V7-FP-NOIAS:   .cfi_endproc

 ; CHECK-THUMB-V7-FP:   .cfi_offset r7, -8
 ; CHECK-THUMB-V7-FP:   mov    r7, sp
 ; CHECK-THUMB-V7-FP:   .cfi_def_cfa_register r7
 ; CHECK-THUMB-V7-FP:   pop    {r7, pc}
 ; CHECK-THUMB-V7-FP:   .cfi_endproc
 
 ; CHECK-THUMB-V7-FP-ELIM-LABEL: test2:
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_startproc
-; CHECK-THUMB-V7-FP-ELIM:   push.w  {r11, lr}
+; CHECK-THUMB-V7-FP-ELIM:   push  {r7, lr}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_def_cfa_offset 8
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset lr, -4
-; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r11, -8
-; CHECK-THUMB-V7-FP-ELIM:   pop.w   {r11, pc}
+; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r7, -8
+; CHECK-THUMB-V7-FP-ELIM:   pop   {r7, pc}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_endproc
 
 
 ;-------------------------------------------------------------------------------
 ; Test 3
 ;-------------------------------------------------------------------------------
 
 declare void @throw_exception_3(i32)

 ; CHECK-THUMB-V7-FP:   .cfi_offset r4, -16
 ; CHECK-THUMB-V7-FP:   add    r7, sp, #8
 ; CHECK-THUMB-V7-FP:   .cfi_def_cfa r7, 8
 ; CHECK-THUMB-V7-FP:   pop    {r4, r5, r7, pc}
 ; CHECK-THUMB-V7-FP:   .cfi_endproc
 
 ; CHECK-THUMB-V7-FP-ELIM-LABEL: test3:
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_startproc
-; CHECK-THUMB-V7-FP-ELIM:   push.w  {r4, r5, r11, lr}
+; CHECK-THUMB-V7-FP-ELIM:   push  {r4, r5, r7, lr}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_def_cfa_offset 16
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset lr, -4
-; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r11, -8
+; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r7, -8
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r5, -12
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_offset r4, -16
-; CHECK-THUMB-V7-FP-ELIM:   pop.w   {r4, r5, r11, pc}
+; CHECK-THUMB-V7-FP-ELIM:   pop   {r4, r5, r7, pc}
 ; CHECK-THUMB-V7-FP-ELIM:   .cfi_endproc
 
 
 ;-------------------------------------------------------------------------------
 ; Test 4
 ;-------------------------------------------------------------------------------
 
 define void @test4() nounwind {

test/CodeGen/ARM/fold-stack-adjust.ll

 ; RUN: llc -mtriple=thumbv7-apple-none-macho < %s | FileCheck %s
 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
 ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS
 ; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX
 
 
 declare void @bar(i8*)
 
 %bigVec = type [2 x double]
 
 @var = global %bigVec zeroinitializer
 
 define void @check_simple() minsize {
 ; CHECK-LABEL: check_simple:
-; CHECK: push.w {r7, r8, r9, r10, r11, lr}
+; CHECK: push {r3, r4, r5, r6, r7, lr}
 ; CHECK-NOT: sub sp, sp,
 ; ...
 ; CHECK-NOT: add sp, sp,
-; CHECK: pop.w {r0, r1, r2, r3, r11, pc}
+; CHECK: pop {r0, r1, r2, r3, r7, pc}
 
 ; CHECK-T1-LABEL: check_simple:
 ; CHECK-T1: push {r3, r4, r5, r6, r7, lr}
 ; CHECK-T1: add r7, sp, #16
 ; CHECK-T1-NOT: sub sp, sp,
 ; ...
 ; CHECK-T1-NOT: add sp, sp,
 ; CHECK-T1: pop {r0, r1, r2, r3, r7, pc}
; CHEC: pop {r3, r4, r5, r6, r7, pc}
 
   %var = alloca i8, i32 16
   call void @bar(i8* %var)
   ret void
 }
 
 define void @check_simple_too_big() minsize {
 ; CHECK-LABEL: check_simple_too_big:
-; CHECK: push.w {r11, lr}
+; CHECK: push {r7, lr}
 ; CHECK: sub sp,
 ; ...
 ; CHECK: add sp,
-; CHECK: pop.w {r11, pc}
+; CHECK: pop {r7, pc}
   %var = alloca i8, i32 64
   call void @bar(i8* %var)
   ret void
 }
 
 define void @check_vfp_fold() minsize {
 ; CHECK-LABEL: check_vfp_fold:
 ; CHECK: push {r[[GLOBREG:[0-9]+]], lr}
; CHECK-IOS: pop {r4, r7, pc}
 
   ret void
 }
 
 ; This function should use just enough space that the "add sp, sp, ..." could be
 ; folded in except that doing so would clobber the value being returned.
 define i64 @check_no_return_clobber() minsize {
 ; CHECK-LABEL: check_no_return_clobber:
-; CHECK: push.w {r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr}
 ; CHECK-NOT: sub sp,
 ; ...
 ; CHECK: add sp, #24
-; CHECK: pop.w {r11, pc}
+; CHECK: pop {r7, pc}
 
   ; Just to keep iOS FileCheck within previous function:
 ; CHECK-IOS-LABEL: check_no_return_clobber:
 
   %var = alloca i8, i32 20
   call void @bar(i8* %var)
   ret i64 0
 }

 ; ...
 ; CHECK-T1: pop {r2, r3, r7}
 ; CHECK-T1: pop {r3}
 ; CHECK-T1: add sp, #16
 ; CHECK-T1: bx  r3
 
 ; CHECK-LABEL: test_varsize:
 ; CHECK: sub  sp, #16
-; CHECK: push.w {r9, r10, r11, lr}
+; CHECK: push {r5, r6, r7, lr}
 ; ...
-; CHECK: pop.w  {r2, r3, r11, lr}
+; CHECK: pop.w  {r2, r3, r7, lr}
 ; CHECK: add  sp, #16
 ; CHECK: bx lr
 
   %var = alloca i8, i32 8
   call void @llvm.va_start(i8* %var)
   call void @bar(i8* %var)
   ret void
 }

test/CodeGen/ARM/interrupt-attr.ll

 ; CHECK-A-THUMB: sub.w r4, r7,  #20
 ; CHECK-A-THUMB: mov sp, r4
 ; CHECK-A-THUMB: pop.w {r0, r1, r2, r3, r4, r7, r12, lr}
 ; CHECK-A-THUMB: subs pc, lr, #4
 
   ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
   ; appropriate sentinel so no special return needed).
 ; CHECK-M-LABEL: irq_fn:
-; CHECK-M: push.w {r4, r10, r11, lr}
+; CHECK-M: push.w {r4, r7, r11, lr}
 ; CHECK-M: add.w r11, sp, #8
 ; CHECK-M: mov r4, sp
 ; CHECK-M: bfc r4, #0, #3
 ; CHECK-M: mov sp, r4
 ; CHECK-M: bl _bar
 ; CHECK-M: sub.w r4, r11, #8
 ; CHECK-M: mov sp, r4
-; CHECK-M: pop.w {r4, r10, r11, pc}
+; CHECK-M: pop.w {r4, r7, r11, pc}
 
   call arm_aapcscc void @bar()
   ret void
 }
 
 ; We don't push/pop r12, as it is banked for FIQ
 define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" {
 ; CHECK-A-LABEL: fiq_fn:

test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll

 ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -arm-atomic-cfg-tidy=0 | FileCheck %s
 ; PR4659
 ; PR4682
 
 define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
 entry:
 ; CHECK-LABEL: __gcov_execlp:
 ; CHECK: sub sp, #8
 ; CHECK: push
-; CHECK: add r7, sp, #4
-; CHECK: sub.w r4, r7, #4
+; CHECK: add r7, sp, #8
+; CHECK: sub.w r4, r7, #8
 ; CHECK: mov sp, r4
 ; CHECK-NOT: mov sp, r7
 ; CHECK: add sp, #8
   call void @__gcov_flush() nounwind
   call void @llvm.va_start(i8* null)
   br i1 undef, label %bb5, label %bb
 
 bb:   ; preds = %bb, %entry

test/CodeGen/Thumb2/large-stack.ll

 }
 
 define i32 @test3() {
 ; DARWIN-LABEL: test3:
 ; DARWIN: push    {r4, r7, lr}
 ; DARWIN: sub.w sp, sp, #805306368
 ; DARWIN: sub sp, #20
 ; LINUX-LABEL: test3:
-; LINUX: push.w {r4, r7, r11, lr}
+; LINUX: push {r4, r6, r7, lr}
 ; LINUX: sub.w sp, sp, #805306368
 ; LINUX: sub sp, #16
     %retval = alloca i32, align 4
     %tmp = alloca i32, align 4
     %a = alloca [805306369 x i8], align 16
     store i32 0, i32* %tmp
     %tmp1 = load i32, i32* %tmp
     ret i32 %tmp1
 }

test/CodeGen/Thumb2/tpsoft.ll

bb:                                               ; preds = %entry
   ret i32 %1
 ; ELFASM:         bl  __aeabi_read_tp
 
 
 ; ELFOBJ:      Sections [
 ; ELFOBJ:        Section {
 ; ELFOBJ:          Name: .text
 ; ELFOBJ-LE:          SectionData (
-;;;                  BL __aeabi_read_tp is ---------+
-;;;                                                 V
-; ELFOBJ-LE-NEXT:     0000: 2DE90048 0E487844 0168FFF7 FEFF4058
+;;;                  BL __aeabi_read_tp is ---+
+;;;                                           V
+; ELFOBJ-LE-NEXT:     0000: 80B50E48 78440168 FFF7FEFF 40580D28
 ; ELFOBJ-BE:          SectionData (
-;;;                  BL __aeabi_read_tp is ---------+
-;;;                                                 V
-; ELFOBJ-BE-NEXT:     0000: E92D4800 480E4478 6801F7FF FFFE5840
+;;;                  BL __aeabi_read_tp is ---+
+;;;                                           V
+; ELFOBJ-BE-NEXT:     0000: B580480E 44786801 F7FFFFFE 5840280D
 
 
 bb1:                                              ; preds = %entry
   %2 = tail call arm_aapcs_vfpcc  i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
   ret i32 %2
 
 bb2:                                              ; preds = %entry
   ret i32 -1
 }
 
 declare arm_aapcs_vfpcc i32 @foo(i8*)
 
 declare arm_aapcs_vfpcc i32 @bar(i32*)

test/MC/ARM/elf-thumbfunc-reloc.ll

entry:
   call void @foo()
   ret void
 }
 
 
 ; make sure that bl 0 <foo> (fff7feff) is correctly encoded
 ; CHECK: Sections [
 ; CHECK:   SectionData (
-; CHECK:     0000: 704700BF 2DE90048 FFF7FEFF BDE80088
+; CHECK:     0000: 704700BF 80B5FFF7 FEFF80BD
 ; CHECK:   )
 ; CHECK: ]
 
 ; CHECK:      Relocations [
 ; CHECK-NEXT:   Section (2) .rel.text {
-; CHECK-NEXT:     0x8 R_ARM_THM_CALL foo 0x0
+; CHECK-NEXT:     0x6 R_ARM_THM_CALL foo 0x0
 ; CHECK-NEXT:   }
 ; CHECK-NEXT:   Section (7) .rel.ARM.exidx {
 ; CHECK-NEXT:     0x0 R_ARM_PREL31 .text 0x0
 ; CHECK-NEXT:     0x8 R_ARM_PREL31 .text 0x0
 ; CHECK-NEXT:   }
 ; CHECK-NEXT: ]
 
 ; make sure foo is thumb function: bit 0 = 1
 ; CHECK:      Symbols [
 ; CHECK:        Symbol {
 ; CHECK:          Name: foo
 ; CHECK-NEXT:     Value: 0x1