[AMDGPU][MC] Corrected error position for some operands and modifiers

[dp]

Summary

Partially fixes bug 47518

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

private:
   bool validateHwreg(const OperandInfoTy &HwReg,
                      const OperandInfoTy &Offset,
                      const OperandInfoTy &Width);
 
   OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
   SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
   SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;
 
+  SMLoc getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test,
+                      const OperandVector &Operands) const;
+  SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
+  SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
+
   bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
   bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSOPLiteral(const MCInst &Inst) const;
   bool validateConstantBusLimitations(const MCInst &Inst);
   bool validateEarlyClobberLimitations(const MCInst &Inst);
   bool validateIntClampSupported(const MCInst &Inst);
   bool validateMIMGAtomicDMask(const MCInst &Inst);
bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {
   // TODO: Check that src0 = src1 or src2.
 
   for (auto Name : {AMDGPU::OpName::src0_modifiers,
                     AMDGPU::OpName::src2_modifiers,
                     AMDGPU::OpName::src2_modifiers}) {
     if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name))
             .getImm() &
         SISrcMods::ABS) {
-      Error(getLoc(), "ABS not allowed in VOP3B instructions");
       return false;
     }
   }
 
   return true;
 }
 
 bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
if (!isUIntN(OffsetSize - 1, Op.getImm())) {
       return false;
     }
   }
 
   return true;
 }
 
 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {
-  for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
+  // Start with second operand because SMEM Offset cannot be dst or src0.
+  for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
     if (Op.isSMEMOffset())
       return Op.getStartLoc();
   }
   return getLoc();
 }
 
 bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,
bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
 
   return true;
 }
 
 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
                                           const SMLoc &IDLoc,
                                           const OperandVector &Operands) {
   if (!validateLdsDirect(Inst)) {
-    Error(IDLoc,
+    Error(getRegLoc(AMDGPU::LDS_DIRECT, Operands),
       "invalid use of lds_direct");
     return false;
   }
   if (!validateSOPLiteral(Inst)) {
     Error(IDLoc,
       "only one literal operand is allowed");
     return false;
   }
   if (!validateVOP3Literal(Inst)) {
     Error(IDLoc,
       "invalid literal operand");
     return false;
   }
   if (!validateConstantBusLimitations(Inst)) {
     Error(IDLoc,
       "invalid operand (violates constant bus restrictions)");
     return false;
   }
   if (!validateEarlyClobberLimitations(Inst)) {
     Error(IDLoc,
       "destination must be different than all sources");
     return false;
   }
   if (!validateIntClampSupported(Inst)) {
-    Error(IDLoc,
+    Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),
       "integer clamping is not supported on this GPU");
     return false;
   }
   if (!validateOpSel(Inst)) {
-    Error(IDLoc,
+    Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),
       "invalid op_sel operand");
     return false;
   }
   // For MUBUF/MTBUF d16 is a part of opcode, so there is nothing to validate.
   if (!validateMIMGD16(Inst)) {
-    Error(IDLoc,
+    Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),
       "d16 modifier is not supported on this GPU");
     return false;
   }
   if (!validateMIMGDim(Inst)) {
     Error(IDLoc, "dim modifier is required on this GPU");
     return false;
   }
   if (!validateMIMGDataSize(Inst)) {
     Error(IDLoc,
       "image data size does not match dmask and tfe");
     return false;
   }
   if (!validateMIMGAddrSize(Inst)) {
     Error(IDLoc,
       "image address size does not match dim and a16");
     return false;
   }
   if (!validateMIMGAtomicDMask(Inst)) {
-    Error(IDLoc,
+    Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
       "invalid atomic image dmask");
     return false;
   }
   if (!validateMIMGGatherDMask(Inst)) {
-    Error(IDLoc,
+    Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
       "invalid image_gather dmask: only one bit must be set");
     return false;
   }
   if (!validateMovrels(Inst)) {
     Error(IDLoc, "source operand must be a VGPR");
     return false;
   }
   if (!validateFlatOffset(Inst, Operands)) {
     return false;
   }
   if (!validateSMEMOffset(Inst, Operands)) {
     return false;
   }
   if (!validateMAIAccWrite(Inst)) {
     return false;
   }
   if (!validateDivScale(Inst)) {
+    Error(IDLoc, "ABS not allowed in VOP3B instructions");
     return false;
   }
   if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
     return false;
   }
 
   return true;
 }
AMDGPUAsmParser::getTokenStr() const {
   return getToken().getString();
 }
 
 void
 AMDGPUAsmParser::lex() {
   Parser.Lex();
 }
 
+SMLoc
+AMDGPUAsmParser::getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test,
+                               const OperandVector &Operands) const {
+  for (unsigned i = Operands.size() - 1; i > 0; --i) {
+    AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
+    if (Test(Op))
+      return Op.getStartLoc();
+  }
+  return ((AMDGPUOperand &)*Operands[0]).getStartLoc();
+}
+
+SMLoc
+AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,
+                           const OperandVector &Operands) const {
+  auto Test = [=](const AMDGPUOperand& Op) { return Op.isImmTy(Type); };
+  return getOperandLoc(Test, Operands);
+}
+
+SMLoc
+AMDGPUAsmParser::getRegLoc(unsigned Reg,
+                           const OperandVector &Operands) const {
+  auto Test = [=](const AMDGPUOperand& Op) {
+    return Op.isRegKind() && Op.getReg() == Reg;
+  };
+  return getOperandLoc(Test, Operands);
+}
+
 //===----------------------------------------------------------------------===//
 // swizzle
 //===----------------------------------------------------------------------===//
 
 LLVM_READNONE
 static unsigned
 encodeBitmaskPerm(const unsigned AndMask,
                   const unsigned OrMask,

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 // CHECK-NEXT:{{^}}                                                ^
 
 //==============================================================================
 // expected a 20-bit unsigned offset
 
 s_atc_probe_buffer 0x1, s[8:11], -1
 // CHECK: error: expected a 20-bit unsigned offset
 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], -1
-// CHECK-NEXT:{{^}}                   ^
+// CHECK-NEXT:{{^}}                                 ^
 
 s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
 // CHECK: error: expected a 20-bit unsigned offset
 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
-// CHECK-NEXT:{{^}}                   ^
+// CHECK-NEXT:{{^}}                                 ^
 
 s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
 // CHECK: error: expected a 20-bit unsigned offset
 // CHECK-NEXT:{{^}}s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
 // CHECK-NEXT:{{^}}                                 ^
 
 //==============================================================================
 // expected a 21-bit signed offset
 
 s_atc_probe 0x7, s[4:5], 0x1FFFFF
 // CHECK: error: expected a 21-bit signed offset
 // CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], 0x1FFFFF
-// CHECK-NEXT:{{^}}            ^
+// CHECK-NEXT:{{^}}                         ^
 
 s_atomic_swap s5, s[2:3], 0x1FFFFF
 // CHECK: error: expected a 21-bit signed offset
 // CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF
 // CHECK-NEXT:{{^}}                          ^
 
 //==============================================================================
 // expected a 5-character mask

 // CHECK-NEXT:{{^}}                         ^
 
 //==============================================================================
 // invalid op_sel operand
 
 v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 // CHECK: error: invalid op_sel operand
 // CHECK-NEXT:{{^}}v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                                ^
 
 //==============================================================================
 // invalid op_sel value.
 
 v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 // CHECK: error: invalid op_sel value.
 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 // CHECK-NEXT:{{^}}                                ^

 // CHECK-NEXT:{{^}}               ^
 
 //==============================================================================
 // invalid use of lds_direct
 
 v_ashrrev_i16 v0, lds_direct, v0
 // CHECK: error: invalid use of lds_direct
 // CHECK-NEXT:{{^}}v_ashrrev_i16 v0, lds_direct, v0
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                  ^
 
 //==============================================================================
 // lane id must be in the interval [0,group size - 1]
 
 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 // CHECK: error: lane id must be in the interval [0,group size - 1]
 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 // CHECK-NEXT:{{^}}                                                 ^

llvm/test/MC/AMDGPU/gfx7_err_pos.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
 
 //==============================================================================
 // d16 modifier is not supported on this GPU
 
 image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
 // CHECK: error: d16 modifier is not supported on this GPU
 // CHECK-NEXT:{{^}}image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                                                      ^
 
 //==============================================================================
 // integer clamping is not supported on this GPU
 
 v_add_co_u32 v84, s[4:5], v13, v31 clamp
 // CHECK: error: integer clamping is not supported on this GPU
 // CHECK-NEXT:{{^}}v_add_co_u32 v84, s[4:5], v13, v31 clamp
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                                   ^
 
 //==============================================================================
 // invalid literal operand
 
 v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
 // CHECK: error: invalid literal operand
 // CHECK-NEXT:{{^}}v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
 // CHECK-NEXT:{{^}}^

llvm/test/MC/AMDGPU/gfx8_err_pos.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
 
 //==============================================================================
 // a16 modifier is not supported on this GPU
 
 image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 a16
 // CHECK: error: a16 modifier is not supported on this GPU
 // CHECK-NEXT:{{^}}image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 a16
 // CHECK-NEXT:{{^}}                                                      ^
 
 //==============================================================================
 // expected a 20-bit unsigned offset
 
 s_atc_probe 0x7, s[4:5], -1
 // CHECK: error: expected a 20-bit unsigned offset
 // CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], -1
-// CHECK-NEXT:{{^}}            ^
+// CHECK-NEXT:{{^}}                         ^
 
 s_store_dword s1, s[2:3], 0xFFFFFFFFFFF00000
 // CHECK: error: expected a 20-bit unsigned offset
 // CHECK-NEXT:{{^}}s_store_dword s1, s[2:3], 0xFFFFFFFFFFF00000
 // CHECK-NEXT:{{^}}                          ^
 
 //==============================================================================
 // flat offset modifier is not supported on this GPU

llvm/test/MC/AMDGPU/gfx9_err_pos.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
 
 //==============================================================================
 // 'null' operand is not supported on this GPU
 
 s_add_u32 null, null, null
 // CHECK: error: 'null' operand is not supported on this GPU
 // CHECK-NEXT:{{^}}s_add_u32 null, null, null
 // CHECK-NEXT:{{^}}          ^
 
 //==============================================================================
+// ABS not allowed in VOP3B instructions
+
+v_div_scale_f64  v[24:25], vcc, -|v[22:23]|, v[22:23], v[20:21]
+// CHECK: error: ABS not allowed in VOP3B instructions
+// CHECK-NEXT:{{^}}v_div_scale_f64  v[24:25], vcc, -|v[22:23]|, v[22:23], v[20:21]
+// CHECK-NEXT:{{^}}^
+
+//==============================================================================
 // duplicate VGPR index mode
 
 s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST)
 // CHECK: error: duplicate VGPR index mode
 // CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST)
 // CHECK-NEXT:{{^}}                                           ^
 
 //==============================================================================

 image_atomic_add v252, v2, s[8:15]
 // CHECK: error: invalid atomic image dmask
 // CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]
 // CHECK-NEXT:{{^}}^
 
 image_atomic_cmpswap v[4:7], v[192:195], s[28:35] dmask:0xe tfe
 // CHECK: error: invalid atomic image dmask
 // CHECK-NEXT:{{^}}image_atomic_cmpswap v[4:7], v[192:195], s[28:35] dmask:0xe tfe
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                                                  ^
 
 //==============================================================================
 // invalid image_gather dmask: only one bit must be set
 
 image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3
 // CHECK: error: invalid image_gather dmask: only one bit must be set
 // CHECK-NEXT:{{^}}image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                                                   ^
 
 //==============================================================================
 // invalid immediate: only 4-bit values are legal
 
 s_set_gpr_idx_on s0, 16
 // CHECK: error: invalid immediate: only 4-bit values are legal
 // CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, 16
 // CHECK-NEXT:{{^}}                     ^