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Differential D91301

[VE] Change the default type of v64 register class
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Authored by kaz7 on Nov 11 2020, 2:41 PM.

Details

Reviewers
simoll
k-ishizaka
Commits
rGa72d3842495d: [VE] Change the default type of v64 register class
Summary

Change the default type of v64 register class from v512i32 to v256f64.
Add a regression test also.

Diff Detail

Event Timeline

kaz7 created this revision.Nov 11 2020, 2:41 PM
Herald added subscribers: llvm-commits, hiraditya. · View Herald TranscriptNov 11 2020, 2:41 PM
kaz7 requested review of this revision.Nov 11 2020, 2:41 PM
Harbormaster completed remote builds in B78528: Diff 304659.Nov 11 2020, 3:23 PM
simoll accepted this revision.Nov 11 2020, 11:50 PM
This revision is now accepted and ready to land.Nov 11 2020, 11:50 PM
This revision was landed with ongoing or failed builds.Nov 12 2020, 2:07 AM
Closed by commit rGa72d3842495d: [VE] Change the default type of v64 register class (authored by kaz7). · Explain Why
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rGa72d3842495d: [VE] Change the default type of v64 register class.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
5 lines
test/
CodeGen/
VE/
Scalar/
18 lines

Diff 304756

llvm/lib/Target/VE/VERegisterInfo.td

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Linesdef F32 : RegisterClass<"VE", [f32], 32,
(sequence "SF%u", 34, 63), (sequence "SF%u", 34, 63),
(sequence "SF%u", 8, 33))>; (sequence "SF%u", 8, 33))>;
def F128 : RegisterClass<"VE", [f128], 128, def F128 : RegisterClass<"VE", [f128], 128,
(add (sequence "Q%u", 0, 3), (add (sequence "Q%u", 0, 3),
(sequence "Q%u", 17, 31), (sequence "Q%u", 17, 31),
(sequence "Q%u", 4, 16))>; (sequence "Q%u", 4, 16))>;
def V64 : RegisterClass<"VE", def V64 : RegisterClass<"VE",
[v512i32, v512f32, [v256f64, // default type for vector registers
v256i64, v256i32, v256f32, v256f64, v512i32, v512f32,
v256i64, v256i32, v256f32, /* v256f64, */
v128i64, v128i32, v128f32, v128f64, v128i64, v128i32, v128f32, v128f64,
v64i64, v64i32, v64f32, v64f64, v64i64, v64i32, v64f32, v64f64,
v32i64, v32i32, v32f32, v32f64, v32i64, v32i32, v32f32, v32f64,
v16i64, v16i32, v16f32, v16f64, v16i64, v16i32, v16f32, v16f64,
v8i64, v8i32, v8f32, v8f64, v8i64, v8i32, v8f32, v8f64,
v4i64, v4i32, v4f32, v4f64, v4i64, v4i32, v4f32, v4f64,
v2i64, v2i32, v2f32, v2f64], 64, v2i64, v2i32, v2f32, v2f64], 64,
(add (sequence "V%u", 0, 63), (add (sequence "V%u", 0, 63),
VIX)>; VIX)>;
// vm0 is reserved for always true // vm0 is reserved for always true
def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>; def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>;
def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>; def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>;

llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst-reg.ll

  • This file was added.
; REQUIRES: asserts
; RUN: llc < %s -mtriple=ve -mattr=+vpu -o /dev/null -debug-only=selectiondag 2>&1 | FileCheck %s
;; Check that a vector register is not bitcasted or assigned to v512* type
;; like below. Because, inline asm assigns registers by not a type but
;; register class.
;;
;; t26: ch,glue = inlineasm t25, TargetExternalSymbol:i64'vld $0, $2, $1', MDNode:ch<null>, TargetConstant:i64<1>, TargetConstant:i32<589834>, Register:v512i32 %4, TargetConstant:i32<262153>, Register:i64 %5, TargetConstant:i32<262153>, Register:i64 %6, t25:1
;; t28: v512i32 = bitcast t27
define void @vldvst(i8* %p, i64 %i) nounwind {
; CHECK-NOT: v512
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
%1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind
ret void
}