[VE] Implement FoldImmediate

[kaz7]

Summary

Implement FoldImmediate for only integer aritihmetic operations.
Add regression tests also.

[kaz7]

Update codes following clang-tidy

llvm/lib/Target/VE/VE.h

inline static bool isMImm32Val(uint32_t Val) {
   if (isMask_32(Val)) {
     // (m)0 patterns
     return true;
   }
   // (m)1 patterns
   return (Val & (1 << 31)) && isShiftedMask_32(Val);
 }
 
+/// val2MImm - Convert an integer immediate value to target MImm immediate.
+inline static uint64_t val2MImm(uint64_t Val) {
+  if (Val == 0)
+    return 0; // (0)1
+  if (Val & (1UL << 63))
+    return countLeadingOnes(Val);       // (m)1
+  return countLeadingZeros(Val) | 0x40; // (m)0
+}
+
+/// mimm2Val - Convert a target MImm immediate to an integer immediate value.
+inline static uint64_t mimm2Val(uint64_t Val) {
+  if (Val == 0)
+    return 0; // (0)1
+  if ((Val & 0x40) == 0)
+    return (uint64_t)((1L << 63) >> (Val & 0x3f)); // (m)1
+  return ((uint64_t)(-1L) >> (Val & 0x3f));        // (m)0
+}
+
 inline unsigned M0(unsigned Val) { return Val + 64; }
 inline unsigned M1(unsigned Val) { return Val; }
 
 } // namespace llvm
 #endif

llvm/lib/Target/VE/VEISelDAGToDAG.cpp

inline static uint64_t getFpImmVal(const ConstantFPSDNode *N) {
   uint64_t Val = Imm.getZExtValue();
   if (Imm.getBitWidth() == 32) {
     // Immediate value of float place places at higher bits on VE.
     Val <<= 32;
   }
   return Val;
 }
 
-/// convMImmVal - Convert a mimm integer immediate value to target immediate.
-inline static uint64_t convMImmVal(uint64_t Val) {
-  if (Val == 0)
-    return 0; // (0)1
-  if (Val & (1UL << 63))
-    return countLeadingOnes(Val);       // (m)1
-  return countLeadingZeros(Val) | 0x40; // (m)0
-}
-
 //===--------------------------------------------------------------------===//
 /// VEDAGToDAGISel - VE specific code to select VE machine
 /// instructions for SelectionDAG operations.
 ///
 namespace {
 class VEDAGToDAGISel : public SelectionDAGISel {
   /// Subtarget - Keep a pointer to the VE Subtarget around so that we can
   /// make the right decision when generating code for different targets.

llvm/lib/Target/VE/VEInstrInfo.h

void storeRegToStackSlot(MachineBasicBlock &MBB,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI, Register DestReg,
                             int FrameIndex, const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI) const override;
   /// } Stack Spill & Reload
 
+  /// Optimization {
+
+  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
+                     MachineRegisterInfo *MRI) const override;
+
+  /// } Optimization
+
   Register getGlobalBaseReg(MachineFunction *MF) const;
 
   // Lower pseudo instructions after register allocation.
   bool expandPostRAPseudo(MachineInstr &MI) const override;
 
   bool expandExtendStackPseudo(MachineInstr &MI) const;
   bool expandGetStackTopPseudo(MachineInstr &MI) const;
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/VE/VEInstrInfo.cpp

BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg)
         .addFrameIndex(FI)
         .addImm(0)
         .addImm(0)
         .addMemOperand(MMO);
   } else
     report_fatal_error("Can't load this register from stack slot");
 }
 
+bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+                                Register Reg, MachineRegisterInfo *MRI) const {
+  LLVM_DEBUG(dbgs() << "FoldImmediate\n");
+
+  LLVM_DEBUG(dbgs() << "checking DefMI\n");
+  int64_t ImmVal;
+  switch (DefMI.getOpcode()) {
+  default:
+    return false;
+  case VE::ORim:
+    // General move small immediate instruction on VE.
+    LLVM_DEBUG(dbgs() << "checking ORim\n");
+    LLVM_DEBUG(DefMI.dump());
+    // FIXME: We may need to support FPImm too.
+    assert(DefMI.getOperand(1).isImm());
+    assert(DefMI.getOperand(2).isImm());
+    ImmVal =
+        DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm());
+    LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");
+    break;
+  case VE::LEAzii:
+    // General move immediate instruction on VE.
+    LLVM_DEBUG(dbgs() << "checking LEAzii\n");
+    LLVM_DEBUG(DefMI.dump());
+    // FIXME: We may need to support FPImm too.
+    assert(DefMI.getOperand(2).isImm());
+    if (!DefMI.getOperand(3).isImm())
+      // LEAzii may refer label
+      return false;
+    ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm();
+    LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");
+    break;
+  }
+
+  // Try to fold like below:
+  //   %1:i64 = ORim 0, 0(1)
+  //   %2:i64 = CMPSLrr %0, %1
+  // To
+  //   %2:i64 = CMPSLrm %0, 0(1)
+  //
+  // Another example:
+  //   %1:i64 = ORim 6, 0(1)
+  //   %2:i64 = CMPSLrr %1, %0
+  // To
+  //   %2:i64 = CMPSLir 6, %0
+  //
+  // Support commutable instructions like below:
+  //   %1:i64 = ORim 6, 0(1)
+  //   %2:i64 = ADDSLrr %1, %0
+  // To
+  //   %2:i64 = ADDSLri %0, 6
+  //
+  // FIXME: Need to support i32.  Current implementtation requires
+  //        EXTRACT_SUBREG, so input has following COPY and it avoids folding:
+  //   %1:i64 = ORim 6, 0(1)
+  //   %2:i32 = COPY %1.sub_i32
+  //   %3:i32 = ADDSWSXrr %0, %2
+  // FIXME: Need to support shift, cmov, and more instructions.
+  // FIXME: Need to support lvl too, but LVLGen runs after peephole-opt.
+
+  LLVM_DEBUG(dbgs() << "checking UseMI\n");
+  LLVM_DEBUG(UseMI.dump());
+  unsigned NewUseOpcSImm7;
+  unsigned NewUseOpcMImm;
+  enum InstType {
+    rr2ri_rm, // rr -> ri or rm, commutable
+    rr2ir_rm, // rr -> ir or rm
+  } InstType;
+
+  using namespace llvm::VE;
+#define INSTRKIND(NAME)                                                        \
+  case NAME##rr:                                                               \
+    NewUseOpcSImm7 = NAME##ri;                                                 \
+    NewUseOpcMImm = NAME##rm;                                                  \
+    InstType = rr2ri_rm;                                                       \
+    break
+#define NCINSTRKIND(NAME)                                                      \
+  case NAME##rr:                                                               \
+    NewUseOpcSImm7 = NAME##ir;                                                 \
+    NewUseOpcMImm = NAME##rm;                                                  \
+    InstType = rr2ir_rm;                                                       \
+    break
+
+  switch (UseMI.getOpcode()) {
+  default:
+    return false;
+
+    INSTRKIND(ADDUL);
+    INSTRKIND(ADDSWSX);
+    INSTRKIND(ADDSWZX);
+    INSTRKIND(ADDSL);
+    NCINSTRKIND(SUBUL);
+    NCINSTRKIND(SUBSWSX);
+    NCINSTRKIND(SUBSWZX);
+    NCINSTRKIND(SUBSL);
+    INSTRKIND(MULUL);
+    INSTRKIND(MULSWSX);
+    INSTRKIND(MULSWZX);
+    INSTRKIND(MULSL);
+    NCINSTRKIND(DIVUL);
+    NCINSTRKIND(DIVSWSX);
+    NCINSTRKIND(DIVSWZX);
+    NCINSTRKIND(DIVSL);
+    NCINSTRKIND(CMPUL);
+    NCINSTRKIND(CMPSWSX);
+    NCINSTRKIND(CMPSWZX);
+    NCINSTRKIND(CMPSL);
+    INSTRKIND(MAXSWSX);
+    INSTRKIND(MAXSWZX);
+    INSTRKIND(MAXSL);
+    INSTRKIND(MINSWSX);
+    INSTRKIND(MINSWZX);
+    INSTRKIND(MINSL);
+    INSTRKIND(AND);
+    INSTRKIND(OR);
+    INSTRKIND(XOR);
+    INSTRKIND(EQV);
+    NCINSTRKIND(NND);
+    NCINSTRKIND(MRG);
+  }
+
+#undef INSTRKIND
+
+  unsigned NewUseOpc;
+  unsigned UseIdx;
+  bool Commute = false;
+  LLVM_DEBUG(dbgs() << "checking UseMI operands\n");
+  switch (InstType) {
+  case rr2ri_rm:
+    UseIdx = 2;
+    if (UseMI.getOperand(1).getReg() == Reg) {
+      Commute = true;
+    } else {
+      assert(UseMI.getOperand(2).getReg() == Reg);
+    }
+    if (isInt<7>(ImmVal)) {
+      // This ImmVal matches to SImm7 slot, so change UseOpc to an instruction
+      // holds a simm7 slot.
+      NewUseOpc = NewUseOpcSImm7;
+    } else if (isMImmVal(ImmVal)) {
+      // Similarly, change UseOpc to an instruction holds a mimm slot.
+      NewUseOpc = NewUseOpcMImm;
+      ImmVal = val2MImm(ImmVal);
+    } else
+      return false;
+    break;
+  case rr2ir_rm:
+    if (UseMI.getOperand(1).getReg() == Reg) {
+      // Check immediate value whether it matchs to the UseMI instruction.
+      if (!isInt<7>(ImmVal))
+        return false;
+      NewUseOpc = NewUseOpcSImm7;
+      UseIdx = 1;
+    } else {
+      assert(UseMI.getOperand(2).getReg() == Reg);
+      // Check immediate value whether it matchs to the UseMI instruction.
+      if (!isMImmVal(ImmVal))
+        return false;
+      NewUseOpc = NewUseOpcMImm;
+      ImmVal = val2MImm(ImmVal);
+      UseIdx = 2;
+    }
+    break;
+  }
+
+  LLVM_DEBUG(dbgs() << "modifying UseMI\n");
+  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
+  UseMI.setDesc(get(NewUseOpc));
+  if (Commute) {
+    UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg());
+  }
+  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
+  if (DeleteDef)
+    DefMI.eraseFromParent();
+
+  return true;
+}
+
 Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
   VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>();
   Register GlobalBaseReg = VEFI->getGlobalBaseReg();
   if (GlobalBaseReg != 0)
     return GlobalBaseReg;
 
   // We use %s15 (%got) as a global base register
   GlobalBaseReg = VE::SX15;

llvm/lib/Target/VE/VEInstrInfo.td

def ULO7 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getZExtValue() & 0x7f,
                                    SDLoc(N), MVT::i32);
 }]>;
 def LO7 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
                                    SDLoc(N), MVT::i32);
 }]>;
 def MIMM : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(convMImmVal(getImmVal(N)),
+  return CurDAG->getTargetConstant(val2MImm(getImmVal(N)),
                                    SDLoc(N), MVT::i32);
 }]>;
 def LO32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(Lo_32(N->getZExtValue()),
                                    SDLoc(N), MVT::i32);
 }]>;
 def HI32 : SDNodeXForm<imm, [{
   // Transformation function: shift the immediate value down into the low bits.
   return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),
                                    SDLoc(N), MVT::i32);
 }]>;
 
 def LO7FP : SDNodeXForm<fpimm, [{
   uint64_t Val = getFpImmVal(N);
   return CurDAG->getTargetConstant(SignExtend32(Val, 7), SDLoc(N), MVT::i32);
 }]>;
 def MIMMFP : SDNodeXForm<fpimm, [{
-  return CurDAG->getTargetConstant(convMImmVal(getFpImmVal(N)),
+  return CurDAG->getTargetConstant(val2MImm(getFpImmVal(N)),
                                    SDLoc(N), MVT::i32);
 }]>;
 def LOFP32 : SDNodeXForm<fpimm, [{
   return CurDAG->getTargetConstant(Lo_32(getFpImmVal(N) & 0xffffffff),
                                    SDLoc(N), MVT::i32);
 }]>;
 def HIFP32 : SDNodeXForm<fpimm, [{
   return CurDAG->getTargetConstant(Hi_32(getFpImmVal(N)), SDLoc(N), MVT::i32);

 //===----------------------------------------------------------------------===//
 
 // Multiclass for generic RR type instructions
 let hasSideEffects = 0 in
 multiclass RRbm<string opcStr, bits<8>opc,
                 RegisterClass RCo, ValueType Tyo,
                 RegisterClass RCi, ValueType Tyi,
                 SDPatternOperator OpNode = null_frag,
-                Operand immOp = simm7, Operand mOp = mimm> {
+                Operand immOp = simm7, Operand mOp = mimm,
+                bit MoveImm = 0> {
   def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
               !strconcat(opcStr, " $sx, $sy, $sz"),
               [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;
   // VE calculates (OpNode $sy, $sz), but llvm requires to have immediate
   // in RHS, so we use following definition.
   let cy = 0 in
   def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy),
               !strconcat(opcStr, " $sx, $sy, $sz"),
               [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi immOp:$sy)))]>;
   let cz = 0 in
   def rm : RR<opc, (outs RCo:$sx), (ins RCi:$sy, mOp:$sz),
               !strconcat(opcStr, " $sx, $sy, $sz"),
               [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;
   let cy = 0, cz = 0 in
   def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz),
               !strconcat(opcStr, " $sx, $sy, $sz"),
-              [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]>;
+              [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]> {
+    // VE uses ORim as a move immediate instruction, so declare it here.
+    // An instruction declared as MoveImm will be optimized in FoldImmediate
+    // later.
+    let isMoveImm = MoveImm;
+  }
 }
 
 // Multiclass for non-commutative RR type instructions
 let hasSideEffects = 0 in
 multiclass RRNCbm<string opcStr, bits<8>opc,
                 RegisterClass RCo, ValueType Tyo,
                 RegisterClass RCi, ValueType Tyi,
                 SDPatternOperator OpNode = null_frag,
def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz),
               [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]>;
 }
 
 // Generic RR multiclass with 2 arguments.
 //   e.g. ADDUL, ADDSWSX, ADDSWZX, and etc.
 multiclass RRm<string opcStr, bits<8>opc,
                RegisterClass RC, ValueType Ty,
                SDPatternOperator OpNode = null_frag,
-               Operand immOp = simm7, Operand mOp = mimm> :
-  RRbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp>;
+               Operand immOp = simm7, Operand mOp = mimm, bit MoveImm = 0> :
+  RRbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp, MoveImm>;
 
 // Generic RR multiclass for non-commutative instructions with 2 arguments.
 //   e.g. SUBUL, SUBUW, SUBSWSX, and etc.
 multiclass RRNCm<string opcStr, bits<8>opc,
                  RegisterClass RC, ValueType Ty,
                  SDPatternOperator OpNode = null_frag,
                  Operand immOp = simm7, Operand mOp = mimm> :
   RRNCbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp>;

 // Assembly Language Reference Manual.
 //===----------------------------------------------------------------------===//
 
 //-----------------------------------------------------------------------------
 // Section 8.2 - Load/Store instructions
 //-----------------------------------------------------------------------------
 
 // Multiclass for generic RM instructions
-multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC> {
+multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC, bit MoveImm = 0> {
   def rri : RM<opc, (outs RC:$dest), (ins MEMrri:$addr),
                !strconcat(opcStr, " $dest, $addr"), []>;
   let cy = 0 in
   def rii : RM<opc, (outs RC:$dest), (ins MEMrii:$addr),
                !strconcat(opcStr, " $dest, $addr"), []>;
   let cz = 0 in
   def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr),
                !strconcat(opcStr, " $dest, $addr"), []>;
   let cy = 0, cz = 0 in
   def zii : RM<opc, (outs RC:$dest), (ins MEMzii:$addr),
-               !strconcat(opcStr, " $dest, $addr"), []>;
+               !strconcat(opcStr, " $dest, $addr"), []> {
+    // VE uses LEAzii and LEASLzii as a move immediate instruction, so declare
+    // it here.  An instruction declared as MoveImm will be optimized in
+    // FoldImmediate later.
+    let isMoveImm = MoveImm;
+  }
 }
 
 // Section 8.2.1 - LEA
 let isReMaterializable = 1, isAsCheapAsAMove = 1,
     DecoderMethod = "DecodeLoadI64" in {
-  let cx = 0 in defm LEA : RMm<"lea", 0x06, I64>;
-  let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64>;
+  let cx = 0 in defm LEA : RMm<"lea", 0x06, I64, /* MoveImm */ 1>;
+  let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64, /* MoveImm */ 1>;
 }
 
 // LEA basic patterns.
 //   Need to be defined here to prioritize LEA over ADX.
 def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;
 def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
 def : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>;
 def : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>;

 //-----------------------------------------------------------------------------
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 
 // Section 8.5.1 - AND (AND)
 defm AND : RRm<"and", 0x44, I64, i64, and>;
 
 // Section 8.5.2 - OR (OR)
-defm OR : RRm<"or", 0x45, I64, i64, or>;
+defm OR : RRm<"or", 0x45, I64, i64, or, simm7, mimm, /* MoveImm */ 1>;
 
 // Section 8.5.3 - XOR (Exclusive OR)
 defm XOR : RRm<"xor", 0x46, I64, i64, xor>;
 
 // Section 8.5.4 - EQV (Equivalence)
 defm EQV : RRm<"eqv", 0x47, I64, i64>;
 
 } // isReMaterializable, isAsCheapAsAMove

llvm/test/CodeGen/VE/Scalar/atomic_load.ll

 ; Function Attrs: nounwind
 define i128 @_Z24atomic_load_relaxed_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) {
 ; CHECK-LABEL: _Z24atomic_load_relaxed_i128RNSt3__16atomicInEE:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    lea %s0, __atomic_load@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_load@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld %s1, -8(, %s9)
 ; CHECK-NEXT:    ld %s0, -16(, %s9)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = alloca i128, align 16
   %3 = bitcast i128* %2 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
   %4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
   call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 0)
   %5 = load i128, i128* %2, align 16, !tbaa !2
   call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
   ret i128 %5
 }
 
 ; Function Attrs: nounwind
 define i128 @_Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) {
 ; CHECK-LABEL: _Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    lea %s0, __atomic_load@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_load@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld %s1, -8(, %s9)
 ; CHECK-NEXT:    ld %s0, -16(, %s9)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = alloca i128, align 16
   %3 = bitcast i128* %2 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)

 ; Function Attrs: nounwind
 define i128 @_Z24atomic_load_acquire_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) {
 ; CHECK-LABEL: _Z24atomic_load_acquire_i128RNSt3__16atomicInEE:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    lea %s0, __atomic_load@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_load@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld %s1, -8(, %s9)
 ; CHECK-NEXT:    ld %s0, -16(, %s9)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = alloca i128, align 16
   %3 = bitcast i128* %2 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
   %4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
   call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 2)
   %5 = load i128, i128* %2, align 16, !tbaa !2
   call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
   ret i128 %5
 }
 
 ; Function Attrs: nounwind
 define i128 @_Z24atomic_load_acquire_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) {
 ; CHECK-LABEL: _Z24atomic_load_acquire_u128RNSt3__16atomicIoEE:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    lea %s0, __atomic_load@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_load@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld %s1, -8(, %s9)
 ; CHECK-NEXT:    ld %s0, -16(, %s9)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = alloca i128, align 16
   %3 = bitcast i128* %2 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)

 ; Function Attrs: nounwind
 define i128 @_Z24atomic_load_seq_cst_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) {
 ; CHECK-LABEL: _Z24atomic_load_seq_cst_i128RNSt3__16atomicInEE:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    lea %s0, __atomic_load@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_load@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 5, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld %s1, -8(, %s9)
 ; CHECK-NEXT:    ld %s0, -16(, %s9)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = alloca i128, align 16
   %3 = bitcast i128* %2 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
   %4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
   call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 5)
   %5 = load i128, i128* %2, align 16, !tbaa !2
   call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
   ret i128 %5
 }
 
 ; Function Attrs: nounwind
 define i128 @_Z24atomic_load_seq_cst_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) {
 ; CHECK-LABEL: _Z24atomic_load_seq_cst_u128RNSt3__16atomicIoEE:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    lea %s0, __atomic_load@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_load@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 5, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld %s1, -8(, %s9)
 ; CHECK-NEXT:    ld %s0, -16(, %s9)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = alloca i128, align 16
   %3 = bitcast i128* %2 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)

llvm/test/CodeGen/VE/Scalar/atomic_store.ll

 ; CHECK-LABEL: _Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s4, 0, %s0
 ; CHECK-NEXT:    st %s2, -8(, %s9)
 ; CHECK-NEXT:    st %s1, -16(, %s9)
 ; CHECK-NEXT:    lea %s0, __atomic_store@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_store@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    or %s1, 0, %s4
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = alloca i128, align 16
   %4 = bitcast i128* %3 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
   store i128 %1, i128* %3, align 16, !tbaa !2
   %5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
   call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 0)
   call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @_Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
 ; CHECK-LABEL: _Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s4, 0, %s0
 ; CHECK-NEXT:    st %s2, -8(, %s9)
 ; CHECK-NEXT:    st %s1, -16(, %s9)
 ; CHECK-NEXT:    lea %s0, __atomic_store@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_store@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    or %s1, 0, %s4
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = alloca i128, align 16
   %4 = bitcast i128* %3 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
   store i128 %1, i128* %3, align 16, !tbaa !2

 ; CHECK-LABEL: _Z25atomic_store_release_i128RNSt3__16atomicInEEn:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s4, 0, %s0
 ; CHECK-NEXT:    st %s2, -8(, %s9)
 ; CHECK-NEXT:    st %s1, -16(, %s9)
 ; CHECK-NEXT:    lea %s0, __atomic_store@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_store@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 3, (0)1
 ; CHECK-NEXT:    or %s1, 0, %s4
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = alloca i128, align 16
   %4 = bitcast i128* %3 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
   store i128 %1, i128* %3, align 16, !tbaa !2
   %5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
   call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 3)
   call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @_Z25atomic_store_release_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
 ; CHECK-LABEL: _Z25atomic_store_release_u128RNSt3__16atomicIoEEo:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s4, 0, %s0
 ; CHECK-NEXT:    st %s2, -8(, %s9)
 ; CHECK-NEXT:    st %s1, -16(, %s9)
 ; CHECK-NEXT:    lea %s0, __atomic_store@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_store@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 3, (0)1
 ; CHECK-NEXT:    or %s1, 0, %s4
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = alloca i128, align 16
   %4 = bitcast i128* %3 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
   store i128 %1, i128* %3, align 16, !tbaa !2

 ; CHECK-LABEL: _Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s4, 0, %s0
 ; CHECK-NEXT:    st %s2, -8(, %s9)
 ; CHECK-NEXT:    st %s1, -16(, %s9)
 ; CHECK-NEXT:    lea %s0, __atomic_store@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_store@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 5, (0)1
 ; CHECK-NEXT:    or %s1, 0, %s4
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = alloca i128, align 16
   %4 = bitcast i128* %3 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
   store i128 %1, i128* %3, align 16, !tbaa !2
   %5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
   call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 5)
   call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @_Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
 ; CHECK-LABEL: _Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s4, 0, %s0
 ; CHECK-NEXT:    st %s2, -8(, %s9)
 ; CHECK-NEXT:    st %s1, -16(, %s9)
 ; CHECK-NEXT:    lea %s0, __atomic_store@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __atomic_store@hi(, %s0)
-; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    lea %s2, -16(, %s9)
+; CHECK-NEXT:    or %s0, 16, (0)1
 ; CHECK-NEXT:    or %s3, 5, (0)1
 ; CHECK-NEXT:    or %s1, 0, %s4
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = alloca i128, align 16
   %4 = bitcast i128* %3 to i8*
   call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
   store i128 %1, i128* %3, align 16, !tbaa !2

llvm/test/CodeGen/VE/Scalar/br_cc.ll

4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_i128_imm(i128 %0) {
 ; CHECK-LABEL: br_cc_i128_imm:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s1, %s1, %s2
+; CHECK-NEXT:    cmps.l %s1, %s1, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
-; CHECK-NEXT:    or %s4, 63, (0)1
-; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
+; CHECK-NEXT:    cmpu.l %s0, %s0, (58)0
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
 ; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
 ; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_u128_imm(i128 %0) {
 ; CHECK-LABEL: br_cc_u128_imm:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s1, %s1, %s2
+; CHECK-NEXT:    cmps.l %s1, %s1, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
-; CHECK-NEXT:    or %s4, 63, (0)1
-; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
+; CHECK-NEXT:    cmpu.l %s0, %s0, (58)0
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
 ; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
 ; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:

 4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_imm_i128(i128 %0) {
 ; CHECK-LABEL: br_cc_imm_i128:
 ; CHECK:       .LBB{{[0-9]+}}_4:
-; CHECK-NEXT:    or %s2, -1, (0)1
-; CHECK-NEXT:    cmps.l %s1, %s1, %s2
+; CHECK-NEXT:    cmps.l %s1, %s1, (0)0
 ; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s1
-; CHECK-NEXT:    or %s4, -64, (0)1
-; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
+; CHECK-NEXT:    cmpu.l %s0, %s0, (58)1
 ; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
 ; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
 ; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = icmp sgt i128 %0, -65
   br i1 %2, label %3, label %4
 
 3:                                                ; preds = %1
   tail call void asm sideeffect "nop", ""()
   br label %4
 
 4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_imm_u128(i128 %0) {
 ; CHECK-LABEL: br_cc_imm_u128:
 ; CHECK:       .LBB{{[0-9]+}}_4:
-; CHECK-NEXT:    or %s2, -1, (0)1
-; CHECK-NEXT:    cmps.l %s1, %s1, %s2
+; CHECK-NEXT:    cmps.l %s1, %s1, (0)0
 ; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
-; CHECK-NEXT:    or %s4, -64, (0)1
-; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
+; CHECK-NEXT:    cmpu.l %s0, %s0, (58)1
 ; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
 ; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
 ; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:

llvm/test/CodeGen/VE/Scalar/cast.ll

 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s11, 0, %s9
   ret i64 %0
 }
 
 define float @ull2f(i64 %x) {
 ; CHECK-LABEL: ull2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s2, %s0, %s1
+; CHECK-NEXT:    cmps.l %s2, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.l %s1, %s0
 ; CHECK-NEXT:    cvt.s.d %s1, %s1
 ; CHECK-NEXT:    srl %s3, %s0, 1
 ; CHECK-NEXT:    and %s0, 1, %s0
 ; CHECK-NEXT:    or %s0, %s0, %s3
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    cvt.s.d %s0, %s0
 ; CHECK-NEXT:    fadd.s %s0, %s0, %s0

llvm/test/CodeGen/VE/Scalar/ctlz.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 declare i128 @llvm.ctlz.i128(i128, i1)
 declare i64 @llvm.ctlz.i64(i64, i1)
 declare i32 @llvm.ctlz.i32(i32, i1)
 declare i16 @llvm.ctlz.i16(i16, i1)
 declare i8 @llvm.ctlz.i8(i8, i1)
 
 define i128 @func128(i128 %p){
 ; CHECK-LABEL: func128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s2, %s1, %s2
+; CHECK-NEXT:    cmps.l %s2, %s1, (0)1
 ; CHECK-NEXT:    ldz %s1, %s1
 ; CHECK-NEXT:    ldz %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
 ; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s2
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true)
   ret i128 %r

 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true)
   ret i8 %r
 }
 
 define i128 @func128x(i128 %p){
 ; CHECK-LABEL: func128x:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s2, %s1, %s2
+; CHECK-NEXT:    cmps.l %s2, %s1, (0)1
 ; CHECK-NEXT:    ldz %s1, %s1
 ; CHECK-NEXT:    ldz %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
 ; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s2
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false)
   ret i128 %r

llvm/test/CodeGen/VE/Scalar/cttz.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 declare i128 @llvm.cttz.i128(i128, i1)
 declare i64 @llvm.cttz.i64(i64, i1)
 declare i32 @llvm.cttz.i32(i32, i1)
 declare i16 @llvm.cttz.i16(i16, i1)
 declare i8 @llvm.cttz.i8(i8, i1)
 
 define i128 @func128(i128 %p) {
 ; CHECK-LABEL: func128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s2, %s0, %s2
+; CHECK-NEXT:    cmps.l %s2, %s0, (0)1
 ; CHECK-NEXT:    lea %s3, -1(, %s0)
 ; CHECK-NEXT:    nnd %s0, %s0, %s3
 ; CHECK-NEXT:    pcnt %s3, %s0
 ; CHECK-NEXT:    lea %s0, -1(, %s1)
 ; CHECK-NEXT:    nnd %s0, %s1, %s0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
 ; CHECK-NEXT:    cmov.l.ne %s0, %s3, %s2

llvm/test/CodeGen/VE/Scalar/fold-imm-addsl.mir

+# RUN: llc -mtriple=ve -verify-machineinstrs -run-pass peephole-opt -o - %s | FileCheck %s
+
+---
+## Ensure fold immediate as simm7 at rhs
+#CHECK-LABEL: name: addsl_ri
+#CHECK: %2:i64 = nsw ADDSLri %0, 5
+name:            addsl_ri
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: i64, preferred-register: '' }
+  - { id: 1, class: i64, preferred-register: '' }
+liveins:
+  - { reg: '$sx0', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $sx0
+
+    %0:i64 = COPY $sx0
+    %1:i64 = ORim 5, 0
+    %2:i64 = nsw ADDSLrr %0, %1
+    $sx0 = COPY %2
+    RET implicit $sx10, implicit $sx0
+
+...
+
+---
+## Ensure fold immediate as mimm at rhs
+#CHECK-LABEL: name: addsl_rm
+#CHECK: %2:i64 = nsw ADDSLrm %0, 120
+name:            addsl_rm
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: i64, preferred-register: '' }
+  - { id: 1, class: i64, preferred-register: '' }
+liveins:
+  - { reg: '$sx0', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $sx0
+
+    %0:i64 = COPY $sx0
+    %1:i64 = ORim 0, 120
+    %2:i64 = nsw ADDSLrr %0, %1
+    $sx0 = COPY %2
+    RET implicit $sx10, implicit $sx0
+
+...
+
+---
+## Ensure fold immediate as simm7 at lhs
+#CHECK-LABEL: name: addsl_ri_com
+#CHECK: %2:i64 = nsw ADDSLri %0, 5
+name:            addsl_ri_com
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: i64, preferred-register: '' }
+  - { id: 1, class: i64, preferred-register: '' }
+liveins:
+  - { reg: '$sx0', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $sx0
+
+    %0:i64 = COPY $sx0
+    %1:i64 = ORim 5, 0
+    %2:i64 = nsw ADDSLrr %1, %0
+    $sx0 = COPY %2
+    RET implicit $sx10, implicit $sx0
+
+...
+
+---
+## Ensure fold immediate as mimm at rhs
+#CHECK-LABEL: name: addsl_rm_com
+#CHECK: %2:i64 = nsw ADDSLrm %0, 120
+name:            addsl_rm_com
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: i64, preferred-register: '' }
+  - { id: 1, class: i64, preferred-register: '' }
+liveins:
+  - { reg: '$sx0', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $sx0
+
+    %0:i64 = COPY $sx0
+    %1:i64 = ORim 0, 120
+    %2:i64 = nsw ADDSLrr %1, %0
+    $sx0 = COPY %2
+    RET implicit $sx10, implicit $sx0
+
+...

llvm/test/CodeGen/VE/Scalar/fold-imm-cmpsl.mir

+# RUN: llc -mtriple=ve -verify-machineinstrs -run-pass peephole-opt -o - %s | FileCheck %s
+
+---
+## Ensure fold immediate as simm7 at rhs
+#CHECK-LABEL: name: cmpsl_ir
+#CHECK: %2:i64 = nsw CMPSLir 5, %0
+name:            cmpsl_ir
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: i64, preferred-register: '' }
+  - { id: 1, class: i64, preferred-register: '' }
+liveins:
+  - { reg: '$sx0', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $sx0
+
+    %0:i64 = COPY $sx0
+    %1:i64 = ORim 5, 0
+    %2:i64 = nsw CMPSLrr %1, %0
+    $sx0 = COPY %2
+    RET implicit $sx10, implicit $sx0
+
+...
+
+---
+## Ensure fold immediate as mimm at rhs
+#CHECK-LABEL: name: cmpsl_rm
+#CHECK: %2:i64 = nsw CMPSLrm %0, 120
+name:            cmpsl_rm
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: i64, preferred-register: '' }
+  - { id: 1, class: i64, preferred-register: '' }
+liveins:
+  - { reg: '$sx0', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $sx0
+
+    %0:i64 = COPY $sx0
+    %1:i64 = ORim 0, 120
+    %2:i64 = nsw CMPSLrr %0, %1
+    $sx0 = COPY %2
+    RET implicit $sx10, implicit $sx0
+
+...

llvm/test/CodeGen/VE/Scalar/int_to_fp.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 ; Function Attrs: norecurse nounwind readnone
 define float @c2f(i8 signext %a) {
 ; CHECK-LABEL: c2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i8 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @s2f(i16 signext %a) {
 ; CHECK-LABEL: s2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i16 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @i2f(i32 %a) {
 ; CHECK-LABEL: i2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i32 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @l2f(i64 %a) {
 ; CHECK-LABEL: l2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    cvt.s.d %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i64 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @uc2f(i8 zeroext %a) {
 ; CHECK-LABEL: uc2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i8 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @us2f(i16 zeroext %a) {
 ; CHECK-LABEL: us2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i16 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @ui2f(i32 %a) {
 ; CHECK-LABEL: ui2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    cvt.s.d %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i32 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @ul2f(i64 %a) {
 ; CHECK-LABEL: ul2f:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s2, %s0, %s1
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
+; CHECK-NEXT:    cmps.l %s2, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.l %s1, %s0
 ; CHECK-NEXT:    cvt.s.d %s1, %s1
 ; CHECK-NEXT:    srl %s3, %s0, 1
 ; CHECK-NEXT:    and %s0, 1, %s0
 ; CHECK-NEXT:    or %s0, %s0, %s3
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    cvt.s.d %s0, %s0
 ; CHECK-NEXT:    fadd.s %s0, %s0, %s0
 ; CHECK-NEXT:    cmov.l.lt %s1, %s0, %s2
 ; CHECK-NEXT:    or %s0, 0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i64 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @c2d(i8 signext %a) {
 ; CHECK-LABEL: c2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i8 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @s2d(i16 signext %a) {
 ; CHECK-LABEL: s2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i16 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @i2d(i32 %a) {
 ; CHECK-LABEL: i2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i32 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @l2d(i64 %a) {
 ; CHECK-LABEL: l2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i64 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @uc2d(i8 zeroext %a) {
 ; CHECK-LABEL: uc2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i8 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @us2d(i16 zeroext %a) {
 ; CHECK-LABEL: us2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i16 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @ui2d(i32 %a) {
 ; CHECK-LABEL: ui2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i32 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @ul2d(i64 %a) {
 ; CHECK-LABEL: ul2d:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       .LBB{{[0-9]+}}_2: # %entry
 ; CHECK-NEXT:    srl %s1, %s0, 32
 ; CHECK-NEXT:    lea.sl %s2, 1160773632
 ; CHECK-NEXT:    or %s1, %s1, %s2
 ; CHECK-NEXT:    lea %s2, 1048576
 ; CHECK-NEXT:    lea.sl %s2, -986710016(, %s2)
 ; CHECK-NEXT:    fadd.d %s1, %s1, %s2
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s2, 1127219200
 ; CHECK-NEXT:    or %s0, %s0, %s2
 ; CHECK-NEXT:    fadd.d %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i64 %a to double
   ret double %conv
 }

llvm/test/CodeGen/VE/Scalar/select_cc.ll

 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i1 @select_cc_i128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) {
 ; CHECK-LABEL: select_cc_i128_i1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i1 %2, i1 %3
   ret i1 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i1 @select_cc_u128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) {
 ; CHECK-LABEL: select_cc_u128_i1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i1 %2, i1 %3
   ret i1 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @select_cc_i128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) {
 ; CHECK-LABEL: select_cc_i128_i8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.sx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i8 %2, i8 %3
   ret i8 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @select_cc_u128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) {
 ; CHECK-LABEL: select_cc_u128_i8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.sx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i8 %2, i8 %3
   ret i8 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @select_cc_i128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) {
 ; CHECK-LABEL: select_cc_i128_u8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i8 %2, i8 %3
   ret i8 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @select_cc_u128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) {
 ; CHECK-LABEL: select_cc_u128_u8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i8 %2, i8 %3
   ret i8 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @select_cc_i128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) {
 ; CHECK-LABEL: select_cc_i128_i16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.sx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i16 %2, i16 %3
   ret i16 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @select_cc_u128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) {
 ; CHECK-LABEL: select_cc_u128_i16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.sx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i16 %2, i16 %3
   ret i16 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @select_cc_i128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) {
 ; CHECK-LABEL: select_cc_i128_u16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i16 %2, i16 %3
   ret i16 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @select_cc_u128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) {
 ; CHECK-LABEL: select_cc_u128_u16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i16 %2, i16 %3
   ret i16 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @select_cc_i128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) {
 ; CHECK-LABEL: select_cc_i128_i32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.sx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @select_cc_u128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) {
 ; CHECK-LABEL: select_cc_u128_i32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.sx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @select_cc_i128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) {
 ; CHECK-LABEL: select_cc_i128_u32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @select_cc_u128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) {
 ; CHECK-LABEL: select_cc_u128_u32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s5, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @select_cc_i128_i64(i128 %0, i128 %1, i64 %2, i64 %3) {
 ; CHECK-LABEL: select_cc_i128_i64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @select_cc_u128_i64(i128 %0, i128 %1, i64 %2, i64 %3) {
 ; CHECK-LABEL: select_cc_u128_i64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @select_cc_i128_u64(i128 %0, i128 %1, i64 %2, i64 %3) {
 ; CHECK-LABEL: select_cc_i128_u64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @select_cc_u128_u64(i128 %0, i128 %1, i64 %2, i64 %3) {
 ; CHECK-LABEL: select_cc_u128_u64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define i128 @select_cc_i128_i128(i128 %0, i128 %1, i128 %2, i128 %3) {
 ; CHECK-LABEL: select_cc_i128_i128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s6, %s4, %s0
 ; CHECK-NEXT:    cmov.l.eq %s7, %s5, %s0
 ; CHECK-NEXT:    or %s0, 0, %s6
 ; CHECK-NEXT:    or %s1, 0, %s7
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i128 %2, i128 %3
   ret i128 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i128 @select_cc_u128_i128(i128 %0, i128 %1, i128 %2, i128 %3) {
 ; CHECK-LABEL: select_cc_u128_i128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s6, %s4, %s0
 ; CHECK-NEXT:    cmov.l.eq %s7, %s5, %s0
 ; CHECK-NEXT:    or %s0, 0, %s6
 ; CHECK-NEXT:    or %s1, 0, %s7
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i128 %2, i128 %3
   ret i128 %6

 
 ; Function Attrs: norecurse nounwind readnone
 define i128 @select_cc_i128_u128(i128 %0, i128 %1, i128 %2, i128 %3) {
 ; CHECK-LABEL: select_cc_i128_u128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s6, %s4, %s0
 ; CHECK-NEXT:    cmov.l.eq %s7, %s5, %s0
 ; CHECK-NEXT:    or %s0, 0, %s6
 ; CHECK-NEXT:    or %s1, 0, %s7
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i128 %2, i128 %3
   ret i128 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i128 @select_cc_u128_u128(i128 %0, i128 %1, i128 %2, i128 %3) {
 ; CHECK-LABEL: select_cc_u128_u128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s6, %s4, %s0
 ; CHECK-NEXT:    cmov.l.eq %s7, %s5, %s0
 ; CHECK-NEXT:    or %s0, 0, %s6
 ; CHECK-NEXT:    or %s1, 0, %s7
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select i1 %5, i128 %2, i128 %3
   ret i128 %6

 
 ; Function Attrs: norecurse nounwind readnone
 define float @select_cc_i128_float(i128 %0, i128 %1, float %2, float %3) {
 ; CHECK-LABEL: select_cc_i128_float:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select fast i1 %5, float %2, float %3
   ret float %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @select_cc_u128_float(i128 %0, i128 %1, float %2, float %3) {
 ; CHECK-LABEL: select_cc_u128_float:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select fast i1 %5, float %2, float %3
   ret float %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define double @select_cc_i128_double(i128 %0, i128 %1, double %2, double %3) {
 ; CHECK-LABEL: select_cc_i128_double:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select fast i1 %5, double %2, double %3
   ret double %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @select_cc_u128_double(i128 %0, i128 %1, double %2, double %3) {
 ; CHECK-LABEL: select_cc_u128_double:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select fast i1 %5, double %2, double %3
   ret double %6
 }
 

 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @select_cc_i128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) {
 ; CHECK-LABEL: select_cc_i128_quad:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s6, %s4, %s0
 ; CHECK-NEXT:    cmov.l.eq %s7, %s5, %s0
 ; CHECK-NEXT:    or %s0, 0, %s6
 ; CHECK-NEXT:    or %s1, 0, %s7
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select fast i1 %5, fp128 %2, fp128 %3
   ret fp128 %6
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @select_cc_u128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) {
 ; CHECK-LABEL: select_cc_u128_quad:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s6, %s4, %s0
 ; CHECK-NEXT:    cmov.l.eq %s7, %s5, %s0
 ; CHECK-NEXT:    or %s0, 0, %s6
 ; CHECK-NEXT:    or %s1, 0, %s7
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i128 %0, %1
   %6 = select fast i1 %5, fp128 %2, fp128 %3
   ret fp128 %6

llvm/test/CodeGen/VE/Scalar/setcc.ll

 ; Function Attrs: norecurse nounwind readnone
 define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
 ; CHECK-LABEL: setcc_i128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp eq i128 %0, %1
   ret i1 %3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
 ; CHECK-LABEL: setcc_u128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    xor %s1, %s1, %s3
 ; CHECK-NEXT:    xor %s0, %s0, %s2
 ; CHECK-NEXT:    or %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
-; CHECK-NEXT:    cmps.l %s0, %s0, %s1
+; CHECK-NEXT:    cmps.l %s0, %s0, (0)1
 ; CHECK-NEXT:    cmov.l.eq %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp eq i128 %0, %1
   ret i1 %3
 }
 
 ; Function Attrs: norecurse nounwind readnone