[LLDB] Fix SVE reginfo for sequential offset in g packet

[omjavaid]

Summary

This moves in the direction of our effort to synchronize register descriptions between LLDB and GDB xml description. We want to able to send registers in a way that their offset fields can be re-constructed based on register sizes in the increasing order of register number.

In context to Arm64 SVE, FPCR and FPSR are same registers in FPU regset and SVE regset. Previously FPSR/FPCR offset was set at the end of SVE data because Linux ptrace data placed FPCR and FPSR at the end of SVE register set.

Now we have two options

1. to include 2 additional primary FPCR/FPSR at the end of SVE regset and make existing FPCR/FPSR in FPU regset as their value regs.
2. use the same register for both SVE and FPU register set.

I have taken the second choice and considering interoperability with other stubs like QEMU and that g packets should generate register data in increasing order of register numbers. We have to move FPCR/FPSR offset up to its original location according to register numbering scheme of ARM64 registers with SVE registers included.

[labath]

The fact that the byte_offset field doubles as a g offset and a ptrace offset is makes things pretty convoluted. Maybe (just maybe) one day we wouldn't even need to materialize the g offset anywhere -- it could just be computed on-the-fly when iterating through the g and qRegisterInfo packets.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

uint32_t NativeRegisterContextLinux_arm64::CalculateSVEOffset(
     const RegisterInfo *reg_info) const {
   // Start of Z0 data is after GPRs plus 8 bytes of vg register
   uint32_t sve_reg_offset = LLDB_INVALID_INDEX32;
   if (m_sve_state == SVEState::FPSIMD) {
     const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
     sve_reg_offset =
         SVE_PT_FPSIMD_OFFSET + (reg - GetRegisterInfo().GetRegNumSVEZ0()) * 16;
   } else if (m_sve_state == SVEState::Full) {
-    uint32_t sve_z0_offset = GetGPRSize() + 8;
+    uint32_t sve_z0_offset = GetGPRSize() + 16;
     sve_reg_offset =
         SVE_SIG_REGS_OFFSET + reg_info->byte_offset - sve_z0_offset;
   }
   return sve_reg_offset;
 }
 
 void *NativeRegisterContextLinux_arm64::GetSVEBuffer() {
   if (m_sve_state == SVEState::FPSIMD)
     return m_sve_ptrace_payload.data() + SVE_PT_FPSIMD_OFFSET;
 
   return m_sve_ptrace_payload.data();
 }
 
 #endif // defined (__arm64__) || defined (__aarch64__)

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

std::vector<lldb_private::RegisterInfo> &reg_info_ref =
       m_per_vq_reg_infos[sve_vq];
 
   if (reg_info_ref.empty()) {
     reg_info_ref = llvm::makeArrayRef(g_register_infos_arm64_sve_le,
                                       m_register_info_count);
 
     uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX;
 
-    reg_info_ref[sve_vg].byte_offset = offset;
-    offset += reg_info_ref[sve_vg].byte_size;
+    reg_info_ref[fpu_fpsr].byte_offset = offset;
+    reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
+    reg_info_ref[sve_vg].byte_offset = offset + 8;
+    offset += 16;
 
     // Update Z registers size and offset
     uint32_t s_reg_base = fpu_s0;
     uint32_t d_reg_base = fpu_d0;
     uint32_t v_reg_base = fpu_v0;
     uint32_t z_reg_base = sve_z0;
 
     for (uint32_t index = 0; index < 32; index++) {
       reg_info_ref[s_reg_base + index].byte_offset = offset;
       reg_info_ref[d_reg_base + index].byte_offset = offset;
       reg_info_ref[v_reg_base + index].byte_offset = offset;
       reg_info_ref[z_reg_base + index].byte_offset = offset;
 
       reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
       offset += reg_info_ref[z_reg_base + index].byte_size;
     }
 
     // Update P registers and FFR size and offset
     for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
       reg_info_ref[it].byte_offset = offset;
       reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
       offset += reg_info_ref[it].byte_size;
     }
 
-    reg_info_ref[fpu_fpsr].byte_offset = offset;
-    reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
+    m_per_vq_reg_infos[sve_vq] = reg_info_ref;
   }
 
   m_register_info_p = reg_info_ref.data();
   return m_vector_reg_vq;
 }
 
 bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
   return (sve_z0 <= reg && reg <= sve_z31);

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

 uint32_t RegisterContextCorePOSIX_arm64::CalculateSVEOffset(
     const RegisterInfo *reg_info) {
   // Start of Z0 data is after GPRs plus 8 bytes of vg register
   uint32_t sve_reg_offset = LLDB_INVALID_INDEX32;
   if (m_sve_state == SVEState::FPSIMD) {
     const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
     sve_reg_offset = sve::ptrace_fpsimd_offset + (reg - GetRegNumSVEZ0()) * 16;
   } else if (m_sve_state == SVEState::Full) {
-    uint32_t sve_z0_offset = GetGPRSize() + 8;
+    uint32_t sve_z0_offset = GetGPRSize() + 16;
     sve_reg_offset =
         sve::SigRegsOffset() + reg_info->byte_offset - sve_z0_offset;
   }
 
   return sve_reg_offset;
 }
 
 bool RegisterContextCorePOSIX_arm64::ReadRegister(const RegisterInfo *reg_info,