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Differential D90152

Fix issue in cortex-a57 sched model
ClosedPublic

Authored by evgeny777 on Oct 26 2020, 5:24 AM.

Details

Reviewers
dmgreen
andreadb
Commits
rGa877bda397bb: Fix issue in cortex-a57 sched model
Summary

This fixes issue with A57Write_4cyc_1M found in D89777

Diff Detail

Event Timeline

evgeny777 created this revision.Oct 26 2020, 5:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 26 2020, 5:24 AM
Herald added subscribers: gbedwell, hiraditya. · View Herald Transcript
evgeny777 requested review of this revision.Oct 26 2020, 5:24 AM
dmgreen accepted this revision.Oct 26 2020, 8:12 AM

LGTM. Thanks for fixing this.

This revision is now accepted and ready to land.Oct 26 2020, 8:12 AM
Closed by commit rGa877bda397bb: Fix issue in cortex-a57 sched model (authored by evgeny777). · Explain WhyOct 26 2020, 10:17 AM
This revision was automatically updated to reflect the committed changes.
evgeny777 added a commit: rGa877bda397bb: Fix issue in cortex-a57 sched model.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
2 lines
test/
tools/
llvm-mca/
ARM/
38 lines

Diff 300714

llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td

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// A57Write_4cyc_1S - A57Write_16cyc_1S // A57Write_4cyc_1S - A57Write_16cyc_1S
foreach Lat = 4-16 in { foreach Lat = 4-16 in {
def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> { def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
let Latency = Lat; let Latency = Lat;
} }
} }
def A57Write_4cyc_1M : SchedWriteRes<[A57UnitL]> { let Latency = 4; } def A57Write_4cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 4; }
def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; } def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
def A57Write_4cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 4; } def A57Write_4cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 4; }
def A57Write_5cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 5; } def A57Write_5cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 5; }
def A57Write_6cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 6; } def A57Write_6cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 6; }
def A57Write_6cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 6; } def A57Write_6cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 6; }
def A57Write_8cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 8; } def A57Write_8cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 8; }
def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; } def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; } def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
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llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

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# CHECK-NEXT: [2] - A57UnitL # CHECK-NEXT: [2] - A57UnitL
# CHECK-NEXT: [3] - A57UnitM # CHECK-NEXT: [3] - A57UnitM
# CHECK-NEXT: [4] - A57UnitS # CHECK-NEXT: [4] - A57UnitS
# CHECK-NEXT: [5] - A57UnitW # CHECK-NEXT: [5] - A57UnitW
# CHECK-NEXT: [6] - A57UnitX # CHECK-NEXT: [6] - A57UnitX
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
# CHECK-NEXT: 8.00 133.00 133.00 79.00 496.00 12.00 - - # CHECK-NEXT: 8.00 133.00 133.00 53.00 522.00 12.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #15 # CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #15
# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #240 # CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #240
# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #3840 # CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #3840
# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #61440 # CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #61440
# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #983040 # CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #983040
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# CHECK-NEXT: - - - - 2.00 - - - smlalbt r5, r6, r4, r1 # CHECK-NEXT: - - - - 2.00 - - - smlalbt r5, r6, r4, r1
# CHECK-NEXT: - - - - 2.00 - - - smlaltb r4, r2, r3, r2 # CHECK-NEXT: - - - - 2.00 - - - smlaltb r4, r2, r3, r2
# CHECK-NEXT: - - - - 2.00 - - - smlaltt r8, r3, r8, r4 # CHECK-NEXT: - - - - 2.00 - - - smlaltt r8, r3, r8, r4
# CHECK-NEXT: - - - - 2.00 - - - smlalbbge r3, r1, r9, r0 # CHECK-NEXT: - - - - 2.00 - - - smlalbbge r3, r1, r9, r0
# CHECK-NEXT: - - - - 2.00 - - - smlalbtle r5, r6, r4, r1 # CHECK-NEXT: - - - - 2.00 - - - smlalbtle r5, r6, r4, r1
# CHECK-NEXT: - - - - 2.00 - - - smlaltbne r4, r2, r3, r2 # CHECK-NEXT: - - - - 2.00 - - - smlaltbne r4, r2, r3, r2
# CHECK-NEXT: - - - - 2.00 - - - smlaltteq r8, r3, r8, r4 # CHECK-NEXT: - - - - 2.00 - - - smlaltteq r8, r3, r8, r4
# CHECK-NEXT: - - - - 2.00 - - - smlald r2, r3, r5, r8 # CHECK-NEXT: - - - - 2.00 - - - smlald r2, r3, r5, r8
# CHECK-NEXT: - - - 2.00 - - - - smlaldx r2, r3, r5, r8 # CHECK-NEXT: - - - - 2.00 - - - smlaldx r2, r3, r5, r8
# CHECK-NEXT: - - - - 2.00 - - - smlaldeq r2, r3, r5, r8 # CHECK-NEXT: - - - - 2.00 - - - smlaldeq r2, r3, r5, r8
# CHECK-NEXT: - - - 2.00 - - - - smlaldxhi r2, r3, r5, r8 # CHECK-NEXT: - - - - 2.00 - - - smlaldxhi r2, r3, r5, r8
# CHECK-NEXT: - - - - 1.00 - - - smlawb r2, r3, r10, r8 # CHECK-NEXT: - - - - 1.00 - - - smlawb r2, r3, r10, r8
# CHECK-NEXT: - - - - 1.00 - - - smlawt r8, r3, r5, r9 # CHECK-NEXT: - - - - 1.00 - - - smlawt r8, r3, r5, r9
# CHECK-NEXT: - - - - 1.00 - - - smlawbeq r2, r7, r5, r8 # CHECK-NEXT: - - - - 1.00 - - - smlawbeq r2, r7, r5, r8
# CHECK-NEXT: - - - - 1.00 - - - smlawthi r1, r3, r0, r8 # CHECK-NEXT: - - - - 1.00 - - - smlawthi r1, r3, r0, r8
# CHECK-NEXT: - - - - 1.00 - - - smlsd r2, r3, r5, r8 # CHECK-NEXT: - - - - 1.00 - - - smlsd r2, r3, r5, r8
# CHECK-NEXT: - - - - 1.00 - - - smlsdx r2, r3, r5, r8 # CHECK-NEXT: - - - - 1.00 - - - smlsdx r2, r3, r5, r8
# CHECK-NEXT: - - - - 1.00 - - - smlsdeq r2, r3, r5, r8 # CHECK-NEXT: - - - - 1.00 - - - smlsdeq r2, r3, r5, r8
# CHECK-NEXT: - - - - 1.00 - - - smlsdxhi r2, r3, r5, r8 # CHECK-NEXT: - - - - 1.00 - - - smlsdxhi r2, r3, r5, r8
# CHECK-NEXT: - - - - 2.00 - - - smlsld r2, r9, r5, r1 # CHECK-NEXT: - - - - 2.00 - - - smlsld r2, r9, r5, r1
# CHECK-NEXT: - - - 2.00 - - - - smlsldx r4, r11, r2, r8 # CHECK-NEXT: - - - - 2.00 - - - smlsldx r4, r11, r2, r8
# CHECK-NEXT: - - - - 2.00 - - - smlsldeq r8, r2, r5, r6 # CHECK-NEXT: - - - - 2.00 - - - smlsldeq r8, r2, r5, r6
# CHECK-NEXT: - - - 2.00 - - - - smlsldxhi r1, r0, r3, r8 # CHECK-NEXT: - - - - 2.00 - - - smlsldxhi r1, r0, r3, r8
# CHECK-NEXT: - - - - 1.00 - - - smmla r1, r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smmla r1, r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smmlar r4, r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smmlar r4, r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smmlalo r1, r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smmlalo r1, r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smmlarhs r4, r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smmlarhs r4, r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smmls r1, r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smmls r1, r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smmlsr r4, r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smmlsr r4, r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smmlslo r1, r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smmlslo r1, r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smmlsrhs r4, r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smmlsrhs r4, r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smmul r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smmul r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smmulr r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smmulr r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smmullo r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smmullo r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smmulrhs r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smmulrhs r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smuad r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smuad r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smuadx r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smuadx r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smuadlt r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smuadlt r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smuadxge r3, r2, r1 # CHECK-NEXT: - - - - 1.00 - - - smuadxge r3, r2, r1
# CHECK-NEXT: - - - - 1.00 - - - smulbb r3, r9, r0 # CHECK-NEXT: - - - - 1.00 - - - smulbb r3, r9, r0
# CHECK-NEXT: - - - - 1.00 - - - smulbt r5, r4, r1 # CHECK-NEXT: - - - - 1.00 - - - smulbt r5, r4, r1
# CHECK-NEXT: - - - - 1.00 - - - smultb r4, r2, r2 # CHECK-NEXT: - - - - 1.00 - - - smultb r4, r2, r2
# CHECK-NEXT: - - - - 1.00 - - - smultt r8, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smultt r8, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - smulbbge r1, r9, r0 # CHECK-NEXT: - - - - 1.00 - - - smulbbge r1, r9, r0
# CHECK-NEXT: - - - - 1.00 - - - smulbtle r5, r6, r4 # CHECK-NEXT: - - - - 1.00 - - - smulbtle r5, r6, r4
# CHECK-NEXT: - - - - 1.00 - - - smultbne r2, r3, r2 # CHECK-NEXT: - - - - 1.00 - - - smultbne r2, r3, r2
# CHECK-NEXT: - - - - 1.00 - - - smultteq r8, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - smultteq r8, r3, r4
# CHECK-NEXT: - - - 2.00 - - - - smull r3, r9, r0, r1 # CHECK-NEXT: - - - - 2.00 - - - smull r3, r9, r0, r1
# CHECK-NEXT: - - - 2.00 - - - - smulls r3, r9, r0, r2 # CHECK-NEXT: - - - - 2.00 - - - smulls r3, r9, r0, r2
# CHECK-NEXT: - - - 2.00 - - - - smulleq r8, r3, r4, r5 # CHECK-NEXT: - - - - 2.00 - - - smulleq r8, r3, r4, r5
# CHECK-NEXT: - - - 2.00 - - - - smullseq r8, r3, r4, r3 # CHECK-NEXT: - - - - 2.00 - - - smullseq r8, r3, r4, r3
# CHECK-NEXT: - - - - 1.00 - - - smulwb r3, r9, r0 # CHECK-NEXT: - - - - 1.00 - - - smulwb r3, r9, r0
# CHECK-NEXT: - - - - 1.00 - - - smulwt r3, r9, r2 # CHECK-NEXT: - - - - 1.00 - - - smulwt r3, r9, r2
# CHECK-NEXT: - - - - 1.00 - - - smusd r3, r0, r1 # CHECK-NEXT: - - - - 1.00 - - - smusd r3, r0, r1
# CHECK-NEXT: - - - - 1.00 - - - smusdx r3, r9, r2 # CHECK-NEXT: - - - - 1.00 - - - smusdx r3, r9, r2
# CHECK-NEXT: - - - - 1.00 - - - smusdeq r8, r3, r2 # CHECK-NEXT: - - - - 1.00 - - - smusdeq r8, r3, r2
# CHECK-NEXT: - - - - 1.00 - - - smusdxne r7, r4, r3 # CHECK-NEXT: - - - - 1.00 - - - smusdxne r7, r4, r3
# CHECK-NEXT: - - - - - - - - srsda sp, #5 # CHECK-NEXT: - - - - - - - - srsda sp, #5
# CHECK-NEXT: - - - - - - - - srsdb sp, #1 # CHECK-NEXT: - - - - - - - - srsdb sp, #1
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# CHECK-NEXT: - - - - - - - - svc #16 # CHECK-NEXT: - - - - - - - - svc #16
# CHECK-NEXT: - - - - - - - - svc #0 # CHECK-NEXT: - - - - - - - - svc #0
# CHECK-NEXT: - - - - - - - - svc #16777215 # CHECK-NEXT: - - - - - - - - svc #16777215
# CHECK-NEXT: - - - - 1.00 - - - sxtab r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - sxtab r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - sxtab r4, r5, r6 # CHECK-NEXT: - - - - 1.00 - - - sxtab r4, r5, r6
# CHECK-NEXT: - - - - 1.00 - - - sxtablt r6, r2, r9, ror #8 # CHECK-NEXT: - - - - 1.00 - - - sxtablt r6, r2, r9, ror #8
# CHECK-NEXT: - - - - 1.00 - - - sxtab r5, r1, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - sxtab r5, r1, r4, ror #16
# CHECK-NEXT: - - - - 1.00 - - - sxtab r7, r8, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - sxtab r7, r8, r3, ror #24
# CHECK-NEXT: - - - 1.00 - - - - sxtab16ge r0, r1, r4 # CHECK-NEXT: - - - - 1.00 - - - sxtab16ge r0, r1, r4
# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r6, r2, r7 # CHECK-NEXT: - - - - 1.00 - - - sxtab16 r6, r2, r7
# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r3, r5, r8, ror #8 # CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r5, r8, ror #8
# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r3, r2, r1, ror #16 # CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r2, r1, ror #16
# CHECK-NEXT: - - - 1.00 - - - - sxtab16eq r1, r2, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - sxtab16eq r1, r2, r3, ror #24
# CHECK-NEXT: - - - - 1.00 - - - sxtah r1, r3, r9 # CHECK-NEXT: - - - - 1.00 - - - sxtah r1, r3, r9
# CHECK-NEXT: - - - - 1.00 - - - sxtahhi r6, r1, r6 # CHECK-NEXT: - - - - 1.00 - - - sxtahhi r6, r1, r6
# CHECK-NEXT: - - - - 1.00 - - - sxtah r3, r8, r3, ror #8 # CHECK-NEXT: - - - - 1.00 - - - sxtah r3, r8, r3, ror #8
# CHECK-NEXT: - - - - 1.00 - - - sxtahlo r2, r2, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - sxtahlo r2, r2, r4, ror #16
# CHECK-NEXT: - - - - 1.00 - - - sxtah r9, r3, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - sxtah r9, r3, r3, ror #24
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtbge r2, r4 # CHECK-NEXT: - 0.50 0.50 - - - - - sxtbge r2, r4
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r5, r6 # CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r5, r6
# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r6, r9, ror #8 # CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r6, r9, ror #8
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# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub16hi r1, r1, r3 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub16hi r1, r1, r3
# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub8 r1, r8, r5 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub8 r1, r8, r5
# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub8le r9, r2, r3 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub8le r9, r2, r3
# CHECK-NEXT: - - - - 1.00 - - - uxtab r2, r3, r4 # CHECK-NEXT: - - - - 1.00 - - - uxtab r2, r3, r4
# CHECK-NEXT: - - - - 1.00 - - - uxtab r4, r5, r6 # CHECK-NEXT: - - - - 1.00 - - - uxtab r4, r5, r6
# CHECK-NEXT: - - - - 1.00 - - - uxtablt r6, r2, r9, ror #8 # CHECK-NEXT: - - - - 1.00 - - - uxtablt r6, r2, r9, ror #8
# CHECK-NEXT: - - - - 1.00 - - - uxtab r5, r1, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - uxtab r5, r1, r4, ror #16
# CHECK-NEXT: - - - - 1.00 - - - uxtab r7, r8, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - uxtab r7, r8, r3, ror #24
# CHECK-NEXT: - - - 1.00 - - - - uxtab16ge r0, r1, r4 # CHECK-NEXT: - - - - 1.00 - - - uxtab16ge r0, r1, r4
# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r6, r2, r7 # CHECK-NEXT: - - - - 1.00 - - - uxtab16 r6, r2, r7
# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r3, r5, r8, ror #8 # CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r5, r8, ror #8
# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r3, r2, r1, ror #16 # CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r2, r1, ror #16
# CHECK-NEXT: - - - 1.00 - - - - uxtab16eq r1, r2, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - uxtab16eq r1, r2, r3, ror #24
# CHECK-NEXT: - - - - 1.00 - - - uxtah r1, r3, r9 # CHECK-NEXT: - - - - 1.00 - - - uxtah r1, r3, r9
# CHECK-NEXT: - - - - 1.00 - - - uxtahhi r6, r1, r6 # CHECK-NEXT: - - - - 1.00 - - - uxtahhi r6, r1, r6
# CHECK-NEXT: - - - - 1.00 - - - uxtah r3, r8, r3, ror #8 # CHECK-NEXT: - - - - 1.00 - - - uxtah r3, r8, r3, ror #8
# CHECK-NEXT: - - - - 1.00 - - - uxtahlo r2, r2, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - uxtahlo r2, r2, r4, ror #16
# CHECK-NEXT: - - - - 1.00 - - - uxtah r9, r3, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - uxtah r9, r3, r3, ror #24
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtbge r2, r4 # CHECK-NEXT: - 0.50 0.50 - - - - - uxtbge r2, r4
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r5, r6 # CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r5, r6
# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r6, r9, ror #8 # CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r6, r9, ror #8
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