[TargetLowering] Add i1 condition for bit comparison fold

[ErikHogeman]

Summary

For i1 types, boolean false is represented identically regardless of the boolean content, so we can allow optimizations that otherwise would not be correct for booleans with false represented as a negative one.

[ErikHogeman]

This is the follow-up from https://reviews.llvm.org/D89390, as discussed in that review.

[spatel]

LGTM

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
 
   // Back to non-vector simplifications.
   // TODO: Can we do these for vector splats?
   if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
     const APInt &C1 = N1C->getAPIntValue();
     EVT ShValTy = N0.getValueType();
 
-    // Fold bit comparisons when we can.
-    if (getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent &&
+    // Fold bit comparisons when we can. This will result in an
+    // incorrect value when boolean false is negative one, unless
+    // the bitsize is 1 in which case the false value is the same
+    // in practice regardless of the representation.
+    if ((VT.getSizeInBits() == 1 ||
+         getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) &&
         (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
         (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) &&
         N0.getOpcode() == ISD::AND) {
       if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
         EVT ShiftTy =
             getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
         if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
           // Perform the xform if the AND RHS is a single bit.

llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll

 ; RUN: llc -march=nvptx -verify-machineinstrs < %s | FileCheck %s
 
 ; Tests the following pattern:
 ; (X & 8) != 0 --> (X & 8) >> 3
 
-; This produces incorrect code when boolean false is represented
-; as a negative one, and this test checks that the transform is
-; not triggered.
+; This produces incorrect code in general when boolean false is
+; represented as a negative one. There is however a special
+; case when the type has a bitsize of 1, for which the false
+; value will be identical regardless of the boolean representation.
+; Check that the optimization triggers in this case.
 
 ; CHECK-LABEL: @pow2_mask_cmp
-; CHECK: and.b32 [[AND:%r[0-9]+]], %r{{[0-9]+}}, 8
-; CHECK: setp.ne.s32 [[SETP:%p[0-9+]]], [[AND]], 0
-; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, [[SETP]]
+; CHECK: bfe.u32 {{%r[0-9]+}}, {{%r[0-9]+}}, 3, 1
 define i32 @pow2_mask_cmp(i32 %x) {
   %a = and i32 %x, 8
   %cmp = icmp ne i32 %a, 0
   %r = zext i1 %cmp to i32
   ret i32 %r
 }