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Differential D89683

[VE] Add setcc for fp128
ClosedPublic

Authored by kaz7 on Oct 19 2020, 3:24 AM.

Details

Reviewers
simoll
k-ishizaka
Commits
rG6bb60d3e2680: [VE] Add setcc for fp128
Summary

Add setcc for fp128 and clean existing ISel patterns. Also add
a regression test.

Diff Detail

Event Timeline

kaz7 created this revision.Oct 19 2020, 3:24 AM
Herald added subscribers: llvm-commits, hiraditya. · View Herald TranscriptOct 19 2020, 3:24 AM
kaz7 requested review of this revision.Oct 19 2020, 3:24 AM
Harbormaster completed remote builds in B75508: Diff 298985.Oct 19 2020, 4:13 AM
simoll accepted this revision.Oct 19 2020, 5:06 AM
This revision is now accepted and ready to land.Oct 19 2020, 5:06 AM
Closed by commit rG6bb60d3e2680: [VE] Add setcc for fp128 (authored by kaz7). · Explain WhyOct 19 2020, 5:37 AM
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rG6bb60d3e2680: [VE] Add setcc for fp128.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
62 lines
test/
CodeGen/
VE/
193 lines

Diff 299020

llvm/lib/Target/VE/VEInstrInfo.td

Show First 20 Lines • Show All 1,782 Lines • ▼ Show 20 Linesdef GETSTACKTOP : Pseudo<(outs I64:$dst), (ins),
[(set iPTR:$dst, (GetStackTop))]>; [(set iPTR:$dst, (GetStackTop))]>;
// SETCC pattern matches // SETCC pattern matches
// //
// CMP %tmp, lhs, rhs ; compare lhs and rhs // CMP %tmp, lhs, rhs ; compare lhs and rhs
// or %res, 0, (0)1 ; initialize by 0 // or %res, 0, (0)1 ; initialize by 0
// CMOV %res, (63)0, %tmp ; set 1 if %tmp is true // CMOV %res, (63)0, %tmp ; set 1 if %tmp is true
def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCSIOp:$cond)), class setccrr<Instruction INSN> :
OutPatFrag<(ops node:$cond, node:$comp),
(EXTRACT_SUBREG (EXTRACT_SUBREG
(CMOVLrm (icond2cc $cond), (INSN $cond, $comp,
(CMPSLrr i64:$LHS, i64:$RHS), !add(63, 64), // means (63)0 == 1
!add(63, 64),
(ORim 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCUIOp:$cond)),
(EXTRACT_SUBREG
(CMOVLrm (icond2cc $cond),
(CMPULrr i64:$LHS, i64:$RHS),
!add(63, 64),
(ORim 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCSIOp:$cond)),
(EXTRACT_SUBREG
(CMOVWrm (icond2cc $cond),
(CMPSWSXrr i32:$LHS, i32:$RHS),
!add(63, 64),
(ORim 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCUIOp:$cond)),
(EXTRACT_SUBREG
(CMOVWrm (icond2cc $cond),
(CMPUWrr i32:$LHS, i32:$RHS),
!add(63, 64),
(ORim 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc f64:$LHS, f64:$RHS, cond:$cond)),
(EXTRACT_SUBREG
(CMOVDrm (fcond2cc $cond),
(FCMPDrr f64:$LHS, f64:$RHS),
!add(63, 64),
(ORim 0, 0)), sub_i32)>; (ORim 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc f32:$LHS, f32:$RHS, cond:$cond)), def : Pat<(i32 (setcc i32:$l, i32:$r, CCSIOp:$cond)),
(EXTRACT_SUBREG (setccrr<CMOVWrm> (icond2cc $cond), (CMPSWSXrr $l, $r))>;
(CMOVSrm (fcond2cc $cond), def : Pat<(i32 (setcc i32:$l, i32:$r, CCUIOp:$cond)),
(FCMPSrr f32:$LHS, f32:$RHS), (setccrr<CMOVWrm> (icond2cc $cond), (CMPUWrr $l, $r))>;
!add(63, 64), def : Pat<(i32 (setcc i64:$l, i64:$r, CCSIOp:$cond)),
(ORim 0, 0)), sub_i32)>; (setccrr<CMOVLrm> (icond2cc $cond), (CMPSLrr $l, $r))>;
def : Pat<(i32 (setcc i64:$l, i64:$r, CCUIOp:$cond)),
(setccrr<CMOVLrm> (icond2cc $cond), (CMPULrr $l, $r))>;
def : Pat<(i32 (setcc f32:$l, f32:$r, cond:$cond)),
(setccrr<CMOVSrm> (fcond2cc $cond), (FCMPSrr $l, $r))>;
def : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)),
(setccrr<CMOVDrm> (fcond2cc $cond), (FCMPDrr $l, $r))>;
def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)),
(setccrr<CMOVDrm> (fcond2cc $cond), (FCMPQrr $l, $r))>;
// Special SELECTCC pattern matches // Special SELECTCC pattern matches
// Use min/max for better performance. // Use min/max for better performance.
// //
// MAX/MIN %res, %lhs, %rhs // MAX/MIN %res, %lhs, %rhs
def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGT)), def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGT)),
(FMAXDrr $LHS, $RHS)>; (FMAXDrr $LHS, $RHS)>;
▲ Show 20 Lines • Show All 229 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/setcc.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve | FileCheck %s
;;; Test all combination of input type and output type among following types.
;;;
;;; Types:
;;; i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: setcc_i1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: xor %s0, 1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = xor i1 %0, %1
%4 = xor i1 %3, true
ret i1 %4
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: setcc_i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i8 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: setcc_u8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i8 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: setcc_i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i16 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: setcc_u16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i16 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: setcc_i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i32 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: setcc_u32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i32 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i64(i64 %0, i64 %1) {
; CHECK-LABEL: setcc_i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i64 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u64(i64 %0, i64 %1) {
; CHECK-LABEL: setcc_u64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i64 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
; CHECK-LABEL: setcc_i128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i128 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
; CHECK-LABEL: setcc_u128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i128 %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_float(float %0, float %1) {
; CHECK-LABEL: setcc_float:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp fast oeq float %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_double(double %0, double %1) {
; CHECK-LABEL: setcc_double:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp fast oeq double %0, %1
ret i1 %3
}
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_quad(fp128 %0, fp128 %1) {
; CHECK-LABEL: setcc_quad:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp fast oeq fp128 %0, %1
ret i1 %3
}