AMDGPU: Implement getNoPreservedMask

[arsenm]

Summary

We don't support funclets for exception handling and I hit this when
manually reducing MIR.

[arsenm]

d3bcfe2a3602e14606417d8bb9d6bbaf636d9a02

llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td

 def CSR_AMDGPU_AllAllocatableSRegs : CalleeSavedRegs<
   (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
 >;
 
 def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
   (add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs_32_105)
 >;
 
+def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
+
 // Calling convention for leaf functions
 def CC_AMDGPU_Func : CallingConv<[
   CCIfByVal<CCPassByVal<4, 4>>,
   CCIfType<[i1], CCPromoteToType<i32>>,
   CCIfType<[i1, i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
   CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
     VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
     VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

public:
   MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
+  const uint32_t *getNoPreservedMask() const override;
 
   // Stack access is very expensive. CSRs are also the high registers, and we
   // want to minimize the number of used registers.
   unsigned getCSRFirstUseCost() const override {
     return 100;
   }
 
   Register getFrameRegister(const MachineFunction &MF) const override;

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
   case CallingConv::Fast:
   case CallingConv::Cold:
     return CSR_AMDGPU_HighRegs_RegMask;
   default:
     return nullptr;
   }
 }
 
+const uint32_t *SIRegisterInfo::getNoPreservedMask() const {
+  return CSR_AMDGPU_NoRegs_RegMask;
+}
+
 Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const SIFrameLowering *TFI =
       MF.getSubtarget<GCNSubtarget>().getFrameLowering();
   const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
   // During ISel lowering we always reserve the stack pointer in entry
   // functions, but never actually want to reference it when accessing our own
   // frame. If we need a frame pointer we use it, but otherwise we can just use
   // an immediate "0" which we represent by returning NoRegister.

llvm/test/CodeGen/AMDGPU/return-with-successors.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=liveintervals -o - %s | FileCheck %s
+# Test that getNoPreservedMask is implemented, which is called when
+# return blocks have successors.
+
+---
+name: endpgm_with_successors
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: endpgm_with_successors
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   S_ENDPGM 0
+  ; CHECK: bb.1:
+  ; CHECK:   S_NOP 0
+  bb.0:
+    successors: %bb.1
+    S_ENDPGM 0
+
+  bb.1:
+    S_NOP 0
+
+...
+
+---
+name: setpc_with_successors
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: setpc_with_successors
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $sgpr30_sgpr31
+  ; CHECK:   S_SETPC_B64 $sgpr30_sgpr31
+  ; CHECK: bb.1:
+  ; CHECK:   S_NOP 0
+  bb.0:
+    liveins: $sgpr30_sgpr31
+    successors: %bb.1
+    S_SETPC_B64 $sgpr30_sgpr31
+
+  bb.1:
+    S_NOP 0
+
+...