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Differential D8764

[mips][microMIPSr6] Implement SUB and SUBU instructions
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Authored by zoran.jovanovic on Apr 1 2015, 3:35 AM.

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Reviewers
dsanders
jkolek
Commits
rL236118: [mips][microMIPSr6] Implement SUB and SUBU instructions

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Event Timeline

zoran.jovanovic updated this revision to Diff 23035.Apr 1 2015, 3:35 AM
zoran.jovanovic retitled this revision from to [mips][microMIPSr6] Implement SUB and SUBU instructions.
zoran.jovanovic updated this object.
zoran.jovanovic edited the test plan for this revision. (Show Details)
zoran.jovanovic added reviewers: dsanders, jkolek.
zoran.jovanovic added parent revisions: D8386: [mips][microMIPSr6] Implement initial subtarget support, D8387: [mips][microMIPSr6] Implement initial mapping support, D8388: [mips][microMIPSr6] Implement BALC and BC instructions, D8490: [mips][microMIPSr6] Implement disassembler support, D8661: [mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping support , D8704: [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions.
zoran.jovanovic added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Apr 10 2015, 9:04 AM
dsanders edited edge metadata.

LGTM with a formatting nit

test/MC/Disassembler/Mips/micromips32r6.txt
18–22

Nit: As per D8704, could you use one-per-line formatting?

This revision is now accepted and ready to land.Apr 10 2015, 9:04 AM
Closed by commit rL236118: [mips][microMIPSr6] Implement SUB and SUBU instructions (authored by zjovanovic). · Explain WhyApr 29 2015, 9:26 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
6 lines
test/
MC/
Disassembler/
Mips/
6 lines
Mips/
micromips32r6/
2 lines

Diff 23035

lib/Target/Mips/MicroMips32r6InstrInfo.td

Show All 15 Lines
// Instruction Encodings // Instruction Encodings
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>; class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>; class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>; class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Descriptions // Instruction Descriptions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>; class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>; class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>; class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd> class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
: BRANCH_DESC_BASE, MMR6Arch<instr_asm> { : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
dag InOperandList = (ins opnd:$offset); dag InOperandList = (ins opnd:$offset);
dag OutOperandList = (outs); dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$offset"); string AsmString = !strconcat(instr_asm, "\t$offset");
bit isBarrier = 1; bit isBarrier = 1;
} }
class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> { class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
bit isCall = 1; bit isCall = 1;
list<Register> Defs = [RA]; list<Register> Defs = [RA];
} }
class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>; class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DecoderNamespace = "MicroMips32r6" in { let DecoderNamespace = "MicroMips32r6" in {
def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6; def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6; def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6; def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6; def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
} }

test/MC/Disassembler/Mips/micromips32r6.txt

# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips32r6 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips32r6 | FileCheck %s
# CHECK: add $3, $4, $5 # CHECK: add $3, $4, $5
0x00 0xa4 0x19 0x10 0x00 0xa4 0x19 0x10
# CHECK: addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234
0x30 0x64 0x04 0xd2 0x30 0x64 0x04 0xd2
# CHECK: addu $3, $4, $5 # CHECK: addu $3, $4, $5
0x00 0xa4 0x19 0x50 0x00 0xa4 0x19 0x50
# CHECK: balc 14572256 # CHECK: balc 14572256
0xb4 0x37 0x96 0xb8 0xb4 0x37 0x96 0xb8
# CHECK: bc 14572256 # CHECK: bc 14572256
0x94 0x37 0x96 0xb8 0x94 0x37 0x96 0xb8
# CHECK: sub $3, $4, $5
0x00 0xa4 0x19 0x90
# CHECK: subu $3, $4, $5
0x00 0xa4 0x19 0xd0
dsandersUnsubmitted
Not Done
ReplyInline Actions

Nit: As per D8704, could you use one-per-line formatting?

dsanders: Nit: As per D8704, could you use one-per-line formatting?

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips32r6 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips32r6 | FileCheck %s
.set noat .set noat
add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10] add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10]
addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2] addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2]
addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50] addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50]
balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8]
bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8]
sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90]
subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]