[DAGTypeLegalizer] Handle ZERO_EXTEND of promoted integer in WidenVecRes_Convert.

[jonpa]

Summary

On SystemZ, a ZERO_EXTEND of an i1 vector handled by WidenVecRes_Convert() always ended up being scalarized, because the type action of the input is promotion which was previously an unhandled case in this method.

This fixes https://bugs.llvm.org/show_bug.cgi?id=47132.

Patch by Eli Friedman.

[jonpa]

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

3331

Does this assume that the final (unroll) part of the method will always be reached? In that case, should that be made explicit with an extra "else" wrapping the cases for Widening/Legal, and alsomaybe an assert that the promoted InVT does then not need Widening or is legal?

[jonpa]

ping!

[uweigand]

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

3331

The result of ZExtPromotedInteger is guaranteed to always have legal type, so afterwards getTypeAction(InVT) will always be TypeWidenLegal.

However, I'm no longer sure all cases are covered here. The situation is that we have a vector zero-extend operation from a type vNiA to another type vNiB (same number of elements, B > A). We know vNiB is not legal, and the preferred legal type is vMiB (with some M > N). If we enter the if, we also know that vNiA is not legal, and the preferred legal type is vNiC (with some C > A).

Therefore, we want to transform the initial operation vNiA -> vNiB into an operation vNiC -> vMiB.

But we do not know anything about the relationship between C and B necessarily. If C is still smaller than B, the operation remains an extension. If C is now larger than B, the operation becomes a truncation. Both these cases are handled. But C could now also be equal to B on some platforms (this cannot happen on Z since all legal vector types have the same total size, but in theory it could happen on a platform that supports multiple legal vector widths). In this case the operation should be neither an extension nor a truncation, just a vector widening. I don't see this handled.

[jonpa]

But we do not know anything about the relationship between C and B necessarily.

Added a check for this.

[uweigand]

This LGTM now. Thanks!

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

SDValue OtherVal = DAG.getNode(
         ISD::EXTRACT_SUBVECTOR, DL, OtherVT, SDValue(WideNode, OtherNo), Zero);
     ReplaceValueWith(SDValue(N, OtherNo), OtherVal);
   }
 
   return SDValue(WideNode, ResNo);
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
+  LLVMContext &Ctx = *DAG.getContext();
   SDValue InOp = N->getOperand(0);
   SDLoc DL(N);
 
-  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  EVT WidenVT = TLI.getTypeToTransformTo(Ctx, N->getValueType(0));
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
 
   EVT InVT = InOp.getValueType();
-  EVT InEltVT = InVT.getVectorElementType();
-  EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
 
   unsigned Opcode = N->getOpcode();
-  unsigned InVTNumElts = InVT.getVectorNumElements();
   const SDNodeFlags Flags = N->getFlags();
+
+  // Handle the case of ZERO_EXTEND where the promoted InVT element size does
+  // not equal that of WidenVT.
+  if (N->getOpcode() == ISD::ZERO_EXTEND &&
+      getTypeAction(InVT) == TargetLowering::TypePromoteInteger &&
+      TLI.getTypeToTransformTo(Ctx, InVT).getScalarSizeInBits() !=
+      WidenVT.getScalarSizeInBits()) {
+    InOp = ZExtPromotedInteger(InOp);
+    InVT = InOp.getValueType();
+    if (WidenVT.getScalarSizeInBits() < InVT.getScalarSizeInBits())
+      Opcode = ISD::TRUNCATE;
+  }
+
+  EVT InEltVT = InVT.getVectorElementType();
+  EVT InWidenVT = EVT::getVectorVT(Ctx, InEltVT, WidenNumElts);
+  unsigned InVTNumElts = InVT.getVectorNumElements();
+
   if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
     InOp = GetWidenedVector(N->getOperand(0));
     InVT = InOp.getValueType();
     InVTNumElts = InVT.getVectorNumElements();
     if (InVTNumElts == WidenNumElts) {
       if (N->getNumOperands() == 1)
         return DAG.getNode(Opcode, DL, WidenVT, InOp);
       return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);

llvm/test/CodeGen/SystemZ/vec-zext.ll

 define <8 x i16> @fun10(<8 x i8> %val1) {
 ; CHECK-LABEL: fun10:
 ; CHECK:        vuplhb  %v24, %v24
 ; CHECK-NEXT:   br  %r14
   %z = zext <8 x i8> %val1 to <8 x i16>
   ret <8 x i16> %z
 }
 
+define <2 x i32> @fun11(<2 x i64> %Arg1, <2 x i64> %Arg2) {
+; CHECK-LABEL: fun11:
+; CHECK:      vgbm    %v0, 0
+; CHECK-NEXT: vceqg   %v1, %v24, %v0
+; CHECK-NEXT: vceqg   %v0, %v26, %v0
+; CHECK-NEXT: vo      %v0, %v1, %v0
+; CHECK-NEXT: vrepig  %v1, 1
+; CHECK-NEXT: vn      %v0, %v0, %v1
+; CHECK-NEXT: vpkg    %v24, %v0, %v0
+; CHECK-NEXT: br      %r14
+  %i3 = icmp eq <2 x i64> %Arg1, zeroinitializer
+  %i5 = icmp eq <2 x i64> %Arg2, zeroinitializer
+  %i6 = or <2 x i1> %i3, %i5
+  %i7 = zext <2 x i1> %i6 to <2 x i32>
+  ret <2 x i32> %i7
+}