[VE] Change to promote i32 AND/OR/XOR operations

[kaz7]

Summary

VE has only 64 bits AND/OR/XOR instructions. We pretended that VE has 32 bits
instructions also, but doing it increase the number of generated instructions.
Therefore, we decide to promote 32 bits operations and use only 64 bits
instructions in back end. We also avoid pretending that VE has 32 bits LEA
instruction. Update regression tests also.

[simoll]

llvm/test/CodeGen/VE/xor.ll

115–118

Are you planning to address this regression? (non-blocker given the significant improvements everywhere else)

[kaz7]

Thank you for reviewing.

llvm/test/CodeGen/VE/xor.ll

115–118

No since I think these additional instructions are required to handle 32 bits correctly. VE instructions sign-extend all immediate values in instructions. So, (33)1 is 0xFFFFFFFF80000000. However, llvm expects 0x0000000080000000 here, I think.

llvm/lib/Target/VE/VEISelLowering.cpp

for (MVT IntVT : {MVT::i32, MVT::i64}) {
 
     // VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
     // operations.  Use isel patterns for i64, promote for i32.
     LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal;
     setOperationAction(ISD::BITREVERSE, IntVT, Act);
     setOperationAction(ISD::CTLZ, IntVT, Act);
     setOperationAction(ISD::CTLZ_ZERO_UNDEF, IntVT, Act);
     setOperationAction(ISD::CTPOP, IntVT, Act);
+
+    // VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
+    // Use isel patterns for i64, promote for i32.
+    setOperationAction(ISD::AND, IntVT, Act);
+    setOperationAction(ISD::OR, IntVT, Act);
+    setOperationAction(ISD::XOR, IntVT, Act);
   }
   /// } Int Ops
 
   /// Conversion {
   // VE doesn't have instructions for fp<->uint, so expand them by llvm
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); // use i64
   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64
   setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);

llvm/lib/Target/VE/VEInstrInfo.td

def zii : RM<opc, (outs RC:$dest), (ins MEMzii:$addr),
                !strconcat(opcStr, " $dest, $addr"), []>;
 }
 
 // Section 8.2.1 - LEA
 let cx = 0, DecoderMethod = "DecodeLoadI64" in
 defm LEA : RMm<"lea", 0x06, I64>;
 let cx = 1, DecoderMethod = "DecodeLoadI64" in
 defm LEASL : RMm<"lea.sl", 0x06, I64>;
-let cx = 0, DecoderMethod = "DecodeLoadI32", isCodeGenOnly = 1 in
-defm LEA32 : RMm<"lea", 0x06, I32>;
 
 def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;
 def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
 def : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>;
 def : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>;
-def : Pat<(add I32:$base, simm32:$disp),
-          (LEA32rii (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $base, sub_i32), 0,
-                    (LO32 $disp))>;
 
 def lea_add : PatFrags<(ops node:$base, node:$idx, node:$disp),
                        [(add (add node:$base, node:$idx), node:$disp),
                         (add (add node:$base, node:$disp), node:$idx)]>;
 def : Pat<(lea_add I64:$base, simm7:$idx, simm32:$disp),
           (LEArii $base, (LO7 $idx), (LO32 $disp))>;
 def : Pat<(lea_add I64:$base, I64:$idx, simm32:$disp),
           (LEArri $base, $idx, (LO32 $disp))>;

 let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>;
 
 //-----------------------------------------------------------------------------
 // Section 8.5 - Logical Operation Instructions
 //-----------------------------------------------------------------------------
 
 // Section 8.5.1 - AND (AND)
 defm AND : RRm<"and", 0x44, I64, i64, and>;
-let isCodeGenOnly = 1 in defm AND32 : RRm<"and", 0x44, I32, i32, and>;
 
 // Section 8.5.2 - OR (OR)
 defm OR : RRm<"or", 0x45, I64, i64, or>;
-let isCodeGenOnly = 1 in defm OR32 : RRm<"or", 0x45, I32, i32, or>;
 
 // Section 8.5.3 - XOR (Exclusive OR)
 defm XOR : RRm<"xor", 0x46, I64, i64, xor>;
-let isCodeGenOnly = 1 in defm XOR32 : RRm<"xor", 0x46, I32, i32, xor>;
 
 // Section 8.5.4 - EQV (Equivalence)
 defm EQV : RRm<"eqv", 0x47, I64, i64>;
 
 // Section 8.5.5 - NND (Negate AND)
 def and_not : PatFrags<(ops node:$x, node:$y),
                        [(and (not node:$x), node:$y)]>;
 defm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>;

 // Instructions for CodeGenOnly
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Pattern Matchings
 //===----------------------------------------------------------------------===//
 
 // Small immediates.
-def : Pat<(i32 simm7:$val), (OR32im (LO7 $val), 0)>;
+def : Pat<(i32 simm7:$val), (EXTRACT_SUBREG (ORim (LO7 $val), 0), sub_i32)>;
 def : Pat<(i64 simm7:$val), (ORim (LO7 $val), 0)>;
 // Medium immediates.
-def : Pat<(i32 simm32:$val), (LEA32zii 0, 0, (LO32 $val))>;
+def : Pat<(i32 simm32:$val),
+          (EXTRACT_SUBREG (LEAzii 0, 0, (LO32 $val)), sub_i32)>;
 def : Pat<(i64 simm32:$val), (LEAzii 0, 0, (LO32 $val))>;
 def : Pat<(i64 uimm32:$val), (ANDrm (LEAzii 0, 0, (LO32 $val)), !add(32, 64))>;
 // Arbitrary immediates.
 def : Pat<(i64 lozero:$val),
           (LEASLzii 0, 0, (HI32 imm:$val))>;
 def : Pat<(i64 lomsbzero:$val),
           (LEASLrii (LEAzii 0, 0, (LO32 imm:$val)), 0, (HI32 imm:$val))>;
 def : Pat<(i64 imm:$val),

 
 // Cast to i8
 def : Pat<(sext_inreg I32:$src, i8),
           (SRAWSXri (SLAWSXri $src, 24), 24)>;
 def : Pat<(sext_inreg I64:$src, i8),
           (SRALri (SLLri $src, 56), 56)>;
 def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8),
           (EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>;
-def : Pat<(and (trunc i64:$src), 0xff),
-          (AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(56, 64))>;
+def : Pat<(i32 (and (trunc i64:$src), 0xff)),
+          (EXTRACT_SUBREG (ANDrm $src, !add(56, 64)), sub_i32)>;
 
 // Cast to i16
 def : Pat<(sext_inreg I32:$src, i16),
           (SRAWSXri (SLAWSXri $src, 16), 16)>;
 def : Pat<(sext_inreg I64:$src, i16),
           (SRALri (SLLri $src, 48), 48)>;
 def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16),
           (EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>;
-def : Pat<(and (trunc i64:$src), 0xffff),
-          (AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(48, 64))>;
+def : Pat<(i32 (and (trunc i64:$src), 0xffff)),
+          (EXTRACT_SUBREG (ANDrm $src, !add(48, 64)), sub_i32)>;
 
 // Cast to i32
 def : Pat<(i32 (trunc i64:$src)),
           (ADDSWSXrm (EXTRACT_SUBREG $src, sub_i32), 0)>;
 def : Pat<(i32 (fp_to_sint I64:$reg)), (CVTWDSXr RD_RZ, $reg)>;
 def : Pat<(i32 (fp_to_sint F32:$reg)), (CVTWSSXr RD_RZ, $reg)>;
 
 // Cast to i64

 
 def : Pat<(i32 (bitconvert f32:$op)),
           (EXTRACT_SUBREG (SRALri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
             $op, sub_f32), 32), sub_i32)>;
 def : Pat<(f32 (bitconvert i32:$op)),
           (EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
             $op, sub_i32), 32), sub_f32)>;
 
-// Several special pattern matches to optimize code
-
-def : Pat<(i32 (and i32:$lhs, 0xff)),
-          (AND32rm $lhs, !add(56, 64))>;
-def : Pat<(i32 (and i32:$lhs, 0xffff)),
-          (AND32rm $lhs, !add(48, 64))>;
-def : Pat<(i32 (and i32:$lhs, 0xffffffff)),
-          (AND32rm $lhs, !add(32, 64))>;
+// Optimize code A generated by `(unsigned char)c << 5` to B.
+// A) sla.w.sx %s0, %s0, 5
+//    lea %s1, 224           ; 0xE0
+//    and %s0, %s0, %s1
+// B) sla.w.sx %s0, %s0, 5
+//    and %s0, %s0, (56)0
+
+def : Pat<(i32 (and i32:$val, 0xff)),
+          (EXTRACT_SUBREG
+              (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32),
+                     !add(56, 64)), sub_i32)>;
+def : Pat<(i32 (and i32:$val, 0xffff)),
+          (EXTRACT_SUBREG
+              (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32),
+                     !add(48, 64)), sub_i32)>;
+def : Pat<(i64 (and i64:$val, 0xffffffff)),
+          (ANDrm $val, !add(32, 64))>;

llvm/test/CodeGen/VE/cttz.ll

 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i64 @llvm.cttz.i64(i64 %p, i1 true)
   ret i64 %r
 }
 
 define signext i32 @func32s(i32 signext %p) {
 ; CHECK-LABEL: func32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
+; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
   ret i32 %r
 }
 
 define zeroext i32 @func32z(i32 zeroext %p) {
 ; CHECK-LABEL: func32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
+; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
   ret i32 %r
 }
 
 define signext i16 @func16s(i16 signext %p) {
 ; CHECK-LABEL: func16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
+; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
   ret i16 %r
 }
 
 define zeroext i16 @func16z(i16 zeroext %p) {
 ; CHECK-LABEL: func16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
+; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
   ret i16 %r
 }
 
 define signext i8 @func8s(i8 signext %p) {
 ; CHECK-LABEL: func8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
+; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
   ret i8 %r
 }
 
 define zeroext i8 @func8z(i8 zeroext %p) {
 ; CHECK-LABEL: func8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
+; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
   ret i8 %r
 }
 
 define i128 @func128i() {
 ; CHECK-LABEL: func128i:

llvm/test/CodeGen/VE/nnd.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func8s(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: func8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i8 %a, -1
   %res = and i8 %not, %b
   ret i8 %res
 }
 
 define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: func8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s1, %s0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i8 %a, -1
   %res = and i8 %b, %not
   ret i8 %res
 }
 
 define signext i8 @funci8s(i8 signext %a) {
 ; CHECK-LABEL: funci8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, 5, %s0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    or %s1, 5, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i8 %a, -1
   %res = and i8 %not, 5
   ret i8 %res
 }
 
 define zeroext i8 @funci8z(i8 zeroext %a) {
 ; CHECK-LABEL: funci8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
 ; CHECK-NEXT:    lea %s1, 251
-; CHECK-NEXT:    and %s0, %s0, %s1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i8 %a, -1
   %res = and i8 -5, %not
   ret i8 %res
 }
 
 define signext i16 @func16s(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: func16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i16 %a, -1
   %res = and i16 %not, %b
   ret i16 %res
 }
 
 define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: func16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s1, %s0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i16 %a, -1
   %res = and i16 %b, %not
   ret i16 %res
 }
 
 define signext i16 @funci16s(i16 signext %a) {
 ; CHECK-LABEL: funci16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i16 %a, -1
   %res = and i16 %not, 65535
   ret i16 %res
 }
 
 define zeroext i16 @funci16z(i16 zeroext %a) {
 ; CHECK-LABEL: funci16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, (52)0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, (52)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i16 %a, -1
   %res = and i16 4095, %not
   ret i16 %res
 }
 
 define signext i32 @func32s(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: func32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i32 %a, -1
   %res = and i32 %not, %b
   ret i32 %res
 }
 
 define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: func32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i32 %a, -1
   %res = and i32 %not, %b
   ret i32 %res
 }
 
 define signext i32 @funci32s(i32 signext %a) {
 ; CHECK-LABEL: funci32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, (36)0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, (36)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i32 %a, -1
   %res = and i32 %not, 268435455
   ret i32 %res
 }
 
 define zeroext i32 @funci32z(i32 zeroext %a) {
 ; CHECK-LABEL: funci32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    and %s0, %s0, (36)0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT:    nnd %s0, %s0, (36)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %not = xor i32 %a, -1
   %res = and i32 %not, 268435455
   ret i32 %res
 }
 
 define i64 @func64(i64 %a, i64 %b) {
 ; CHECK-LABEL: func64:

llvm/test/CodeGen/VE/or.ll

 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i8 %b, %a
   ret i8 %res
 }
 
 define signext i8 @funci8s(i8 signext %a) {
 ; CHECK-LABEL: funci8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s0, 5, %s0
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i8 %a, 5
   ret i8 %res
 }
 
 define zeroext i8 @funci8z(i8 zeroext %a) {
 ; CHECK-LABEL: funci8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    lea %s1, 251
 ; CHECK-NEXT:    or %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i8 -5, %a
   ret i8 %res
 }
 
 define signext i16 @func16s(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: func16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i16 %a, 65535
   ret i16 %res
 }
 
 define zeroext i16 @funci16z(i16 zeroext %a) {
 ; CHECK-LABEL: funci16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s0, %s0, (52)0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i16 4095, %a
   ret i16 %res
 }
 
 define signext i32 @func32s(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: func32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i32 %a, %b
   ret i32 %res
 }
 
 define signext i32 @funci32s(i32 signext %a) {
 ; CHECK-LABEL: funci32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s0, %s0, (36)0
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i32 %a, 268435455
   ret i32 %res
 }
 
 define zeroext i32 @funci32z(i32 zeroext %a) {
 ; CHECK-LABEL: funci32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s0, %s0, (36)0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = or i32 %a, 268435455
   ret i32 %res
 }
 
 define i64 @func64(i64 %a, i64 %b) {
 ; CHECK-LABEL: func64:
 ; CHECK:       .LBB{{[0-9]+}}_2:

llvm/test/CodeGen/VE/selectccf32c.ll

 define float @selectccsgti128(i128, i128, float, float) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
 ; CHECK-NEXT:    or %s3, 0, %s6
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT:    or %s0, 0, (0)1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, float %2, float %3
   ret float %6
 }
 

llvm/test/CodeGen/VE/selectccf64c.ll

 define double @selectccsgti128(i128, i128, double, double) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
 ; CHECK-NEXT:    or %s3, 0, %s6
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT:    or %s0, 0, (0)1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, double %2, double %3
   ret double %6
 }
 

llvm/test/CodeGen/VE/selectcci32c.ll

 define i32 @selectccsgti128(i128, i128, i32, i32) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
 ; CHECK-NEXT:    or %s3, 0, %s6
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT:    or %s0, 0, (0)1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 

llvm/test/CodeGen/VE/selectcci64c.ll

 define i64 @selectccsgti128(i128, i128, i64, i64) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
 ; CHECK-NEXT:    or %s3, 0, %s6
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT:    or %s0, 0, (0)1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 

llvm/test/CodeGen/VE/xor.ll

 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i8 %b, %a
   ret i8 %res
 }
 
 define signext i8 @funci8s(i8 signext %a) {
 ; CHECK-LABEL: funci8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    xor %s0, 5, %s0
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i8 %a, 5
   ret i8 %res
 }
 
 define zeroext i8 @funci8z(i8 zeroext %a) {
 ; CHECK-LABEL: funci8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    lea %s1, 251
 ; CHECK-NEXT:    xor %s0, %s0, %s1
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i8 -5, %a
   ret i8 %res
 }
 
 define signext i16 @func16s(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: func16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i16 %b, %a
   ret i16 %res
 }
 
 define signext i16 @funci16s(i16 signext %a) {
 ; CHECK-LABEL: funci16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    xor %s0, -1, %s0
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i16 %a, 65535
   ret i16 %res
 }
 
 define zeroext i16 @funci16z(i16 zeroext %a) {
 ; CHECK-LABEL: funci16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    xor %s0, %s0, (52)0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i16 4095, %a
   ret i16 %res
 }
 
 define signext i32 @func32s(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: func32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i32 %a, %b
   ret i32 %res
 }
 
 define signext i32 @funci32s(i32 signext %a) {
 ; CHECK-LABEL: funci32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    xor %s0, %s0, (36)0
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i32 %a, 268435455
   ret i32 %res
 }
 
 define zeroext i32 @funci32z(i32 zeroext %a) {
 ; CHECK-LABEL: funci32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    xor %s0, %s0, (36)0
-; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %res = xor i32 %a, 268435455
   ret i32 %res
 }
 
 define i32 @funci32_another(i32 %0) {
 ; CHECK-LABEL: funci32_another:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    xor %s0, %s0, (33)1
+; CHECK-NEXT:    lea %s1, -2147483648
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    xor %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = xor i32 %0, -2147483648
   ret i32 %2
 }
 
 
 define i64 @func64(i64 %a, i64 %b) {
 ; CHECK-LABEL: func64:
 ; CHECK:       .LBB{{[0-9]+}}_2: