[mips][microMIPSr6] Implement CLO and CLZ instructions

[jkolek]

Summary

This patch implements CLO and CLZ instructions using mapping.

[zoran.jovanovic]

LGTM with a nit.

test/MC/Disassembler/Mips/micromips32r6.txt

18

Nit: Please use the single-line style.

lib/Target/Mips/MicroMipsR6InstrFormats.td

class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
   bits<32> Inst;
 
   let Inst{31-26} = 0b011110;
   let Inst{25-21} = rt;
   let Inst{20-16} = funct;
   let Inst{15-0}  = imm;
 }
 
+class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
+  bits<5> rs;
+  bits<5> rt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-6}  = funct;
+  let Inst{5-0}   = 0b111100;
+}
+
+class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
+  bits<5> rs;
+  bits<5> rt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rs;
+  let Inst{20-16} = 0b00000;
+  let Inst{15-11} = rt;
+  let Inst{10-6}  = 0b00001;
+  let Inst{5-0}   = funct;
+}
+
 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
   bits<5> rd;
   bits<5> rs;
   bits<5> rt;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b000000;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-11} = rd;
   let Inst{10}    = 0;
   let Inst{9-0}   = funct;
 }

lib/Target/Mips/MicroMipsR6InstrInfo.td

 //
 //===----------------------------------------------------------------------===//
 
 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
+class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
+class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101001>;
 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
 
 //===----------------------------------------------------------------------===//
 //

 }
 
 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
   bit isCall = 1;
   list<Register> Defs = [RA];
 }
 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 
+class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+    : MMR6Arch<instr_asm> {
+  dag OutOperandList = (outs GPROpnd:$rt);
+  dag InOperandList = (ins GPROpnd:$rs);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
+}
+
+class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
+class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
+
 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
                                      RegisterOperand GPROpnd>
     : MMR6Arch<opstr> {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   string AsmString = !strconcat(opstr, "\t$rt, $offset");
   list<dag> Pattern = [];
   bit isTerminator = 1;
   bit hasDelaySlot = 0;

 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMips32r6" in {
 def ALUIPC_MMR6 : MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC, ISA_MICROMIPSR6;
 def AUIPC_MMR6 : MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPSR6;
 def ADDIUPC_MMR6 : MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC, ISA_MICROMIPSR6;
 def BALC_MMR6 : MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPSR6;
 def BC_MMR6 : MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPSR6;
+def CLO_MMR6 : MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPSR6;
+def CLZ_MMR6 : MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPSR6;
 def JIALC_MMR6 : MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPSR6;
 def JIC_MMR6 : MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPSR6;
 def LWPC_MMR6 : MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPSR6;
 def SELEQZ_MMR6 : MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC, ISA_MICROMIPSR6;
 def SELNEZ_MMR6 : MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC, ISA_MICROMIPSR6;
 }

lib/Target/Mips/Mips32r6InstrInfo.td

class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   bit mayStore = 1;
   string Constraints = "$rt = $dst";
 }
 
 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
 
-class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+    : Mips32r6Arch<instr_asm> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 }
 
 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
     CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
   list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];

 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
 def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
-def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
-def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
+def CLO_R6 : MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
+def CLZ_R6 : MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
 def JIALC : MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
 def JIC : MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;

test/MC/Disassembler/Mips/micromips32r6.txt

 0x78 0x80 0x00 0x19
 
 # CHECK: balc 14572256
 0xb4 0x37 0x96 0xb8
 
 # CHECK: bc 14572256
 0x94 0x37 0x96 0xb8
 
+# CHECK: clo $11, $5
+0x01 0x65 0x4b 0x3c
+
+# CHECK: clz $sp, $gp
+0x03 0x80 0xe8 0x50
+
 # CHECK: jialc $5, 256
 0xa4 0x05 0x01 0x00
 
 # CHECK: jic $5, 256
 0xa0 0x05 0x01 0x00
 
 # CHECK: lwpc $2, 268
 0x78 0x48 0x00 0x43
 
 # CHECK: seleqz $2, $3, $4
 0x00 0x83 0x11 0x40
 
 # CHECK: selnez $2, $3, $4
 0x00 0x83 0x11 0x80

test/MC/Mips/micromipsr6/valid.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromipsr6 | FileCheck %s
 
   .set noat
   aluipc $3, 56            # CHECK: aluipc $3, 56       # encoding: [0x78,0x7f,0x00,0x38]
   auipc $3, -1             # CHECK: auipc $3, -1        # encoding: [0x78,0x7e,0xff,0xff]
   addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0x78,0x80,0x00,0x19]
   balc 14572256            # CHECK: balc 14572256       # encoding: [0xb4,0x37,0x96,0xb8]
   bc 14572256              # CHECK: bc 14572256         # encoding: [0x94,0x37,0x96,0xb8]
+  clo $11, $a1             # CHECK: clo $11, $5         # encoding: [0x01,0x65,0x4b,0x3c]
+  clz $sp, $gp             # CHECK: clz $sp, $gp        # encoding: [0x03,0x80,0xe8,0x50]
   jialc $5, 256            # CHECK: jialc $5, 256       # encoding: [0xa4,0x05,0x01,0x00]
   jic   $5, 256            # CHECK: jic $5, 256         # encoding: [0xa0,0x05,0x01,0x00]
   lwpc    $2,268           # CHECK: lwpc $2, 268        # encoding: [0x78,0x48,0x00,0x43]
   seleqz  $2,$3,$4         # CHECK: seleqz $2, $3, $4   # encoding: [0x00,0x83,0x11,0x40]
   selnez  $2,$3,$4         # CHECK: selnez $2, $3, $4   # encoding: [0x00,0x83,0x11,0x80]