Skip to content

Commit 6fec325

Browse files
author
Jozef Kolek
committedMay 13, 2015
[mips][microMIPSr6] Implement CLO and CLZ instructions
This patch implements CLO and CLZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8553 llvm-svn: 237257
1 parent 780a3b3 commit 6fec325

File tree

5 files changed

+51
-3
lines changed

5 files changed

+51
-3
lines changed
 

‎llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td

+27
Original file line numberDiff line numberDiff line change
@@ -109,3 +109,30 @@ class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
109109
let Inst{10} = 0;
110110
let Inst{9-0} = funct;
111111
}
112+
113+
class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
114+
bits<5> rs;
115+
bits<5> rt;
116+
117+
bits<32> Inst;
118+
119+
let Inst{31-26} = 0b000000;
120+
let Inst{25-21} = rt;
121+
let Inst{20-16} = rs;
122+
let Inst{15-6} = funct;
123+
let Inst{5-0} = 0b111100;
124+
}
125+
126+
class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
127+
bits<5> rs;
128+
bits<5> rt;
129+
130+
bits<32> Inst;
131+
132+
let Inst{31-26} = 0b000000;
133+
let Inst{25-21} = rs;
134+
let Inst{20-16} = 0b00000;
135+
let Inst{15-11} = rt;
136+
let Inst{10-6} = 0b00001;
137+
let Inst{5-0} = funct;
138+
}

‎llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

+14
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,8 @@ class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
2626
class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
2727
class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
2828
class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
29+
class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
30+
class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
2931
class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
3032
class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
3133
class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
@@ -91,6 +93,16 @@ class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
9193
class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
9294
class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
9395

96+
class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
97+
: MMR6Arch<instr_asm> {
98+
dag OutOperandList = (outs GPROpnd:$rt);
99+
dag InOperandList = (ins GPROpnd:$rs);
100+
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
101+
}
102+
103+
class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
104+
class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
105+
94106
class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
95107
RegisterOperand GPROpnd>
96108
: MMR6Arch<opstr> {
@@ -166,6 +178,8 @@ def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
166178
def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
167179
ISA_MICROMIPS32R6;
168180
def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
181+
def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
182+
def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
169183
def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
170184
def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
171185
def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;

‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td

+4-3
Original file line numberDiff line numberDiff line change
@@ -615,7 +615,8 @@ class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
615615

616616
class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
617617

618-
class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
618+
class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
619+
: MipsR6Arch<instr_asm> {
619620
dag OutOperandList = (outs GPROpnd:$rd);
620621
dag InOperandList = (ins GPROpnd:$rs);
621622
string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
@@ -683,8 +684,8 @@ def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
683684
def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
684685
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
685686
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
686-
def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
687-
def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
687+
def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
688+
def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
688689
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
689690
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
690691
def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;

‎llvm/test/MC/Disassembler/Mips/micromips32r6.txt

+4
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,10 @@
2424
# CHECK: cache 1, 8($5)
2525
0x20 0x25 0x60 0x08
2626

27+
0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
28+
29+
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
30+
2731
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
2832

2933
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256

‎llvm/test/MC/Mips/micromips32r6/valid.s

+2
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111
bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8]
1212
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]
1313
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
14+
clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c]
15+
clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
1416
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
1517
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
1618
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]

0 commit comments

Comments
 (0)
Please sign in to comment.