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Differential D85490

[VE] Change to expand multiply related instructions
ClosedPublic

Authored by kaz7 on Aug 6 2020, 5:42 PM.

Details

Reviewers
simoll
k-ishizaka
Commits
rG63bc5d786329: [VE] Change to expand multiply related instructions
Summary

Change to expand MULHU/MULHS/UMUL_LOHI/SMUL_LOHI for i32 and i64 since
those instructions are not available on Aurora SX VE. Some of them
are used in expansion of i128 multiply, so need to modify them to
support i128. Then, update basic arithmetic regression tests of
i128 and signed/unsigned i32 typed integer values.

Diff Detail

Event Timeline

kaz7 created this revision.Aug 6 2020, 5:42 PM
Herald added subscribers: llvm-commits, hiraditya. · View Herald TranscriptAug 6 2020, 5:42 PM
kaz7 requested review of this revision.Aug 6 2020, 5:42 PM
Harbormaster completed remote builds in B67399: Diff 283778.Aug 6 2020, 5:53 PM
simoll accepted this revision.Aug 7 2020, 1:20 AM
This revision is now accepted and ready to land.Aug 7 2020, 1:20 AM
This revision was landed with ongoing or failed builds.Aug 7 2020, 2:22 AM
Closed by commit rG63bc5d786329: [VE] Change to expand multiply related instructions (authored by kaz7). · Explain Why
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rG63bc5d786329: [VE] Change to expand multiply related instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
8 lines
test/
CodeGen/
VE/
148 lines
108 lines
153 lines
112 lines
182 lines

Diff 283850

llvm/lib/Target/VE/VEISelLowering.cpp

Show First 20 Lines • Show All 666 Lines • ▼ Show 20 LinesVETargetLowering::VETargetLowering(const TargetMachine &TM,
/// Int Ops { /// Int Ops {
for (MVT IntVT : {MVT::i32, MVT::i64}) { for (MVT IntVT : {MVT::i32, MVT::i64}) {
// VE has no REM or DIVREM operations. // VE has no REM or DIVREM operations.
setOperationAction(ISD::UREM, IntVT, Expand); setOperationAction(ISD::UREM, IntVT, Expand);
setOperationAction(ISD::SREM, IntVT, Expand); setOperationAction(ISD::SREM, IntVT, Expand);
setOperationAction(ISD::SDIVREM, IntVT, Expand); setOperationAction(ISD::SDIVREM, IntVT, Expand);
setOperationAction(ISD::UDIVREM, IntVT, Expand); setOperationAction(ISD::UDIVREM, IntVT, Expand);
// VE has no MULHU/S or U/SMUL_LOHI operations.
// TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
setOperationAction(ISD::MULHU, IntVT, Expand);
setOperationAction(ISD::MULHS, IntVT, Expand);
setOperationAction(ISD::UMUL_LOHI, IntVT, Expand);
setOperationAction(ISD::SMUL_LOHI, IntVT, Expand);
// VE has no CTTZ, ROTL, ROTR operations.
setOperationAction(ISD::CTTZ, IntVT, Expand); setOperationAction(ISD::CTTZ, IntVT, Expand);
setOperationAction(ISD::ROTL, IntVT, Expand); setOperationAction(ISD::ROTL, IntVT, Expand);
setOperationAction(ISD::ROTR, IntVT, Expand); setOperationAction(ISD::ROTR, IntVT, Expand);
// Use isel patterns for i32 and i64 // Use isel patterns for i32 and i64
setOperationAction(ISD::BSWAP, IntVT, Legal); setOperationAction(ISD::BSWAP, IntVT, Legal);
setOperationAction(ISD::CTLZ, IntVT, Legal); setOperationAction(ISD::CTLZ, IntVT, Legal);
setOperationAction(ISD::CTPOP, IntVT, Legal); setOperationAction(ISD::CTPOP, IntVT, Legal);
▲ Show 20 Lines • Show All 476 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/addition.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func1(i8 signext %0, i8 signext %1) { define signext i8 @func8s(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i8 %1, %0 %3 = add i8 %1, %0
ret i8 %3 ret i8 %3
} }
define signext i16 @func2(i16 signext %0, i16 signext %1) { define signext i16 @func16s(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i16 %1, %0 %3 = add i16 %1, %0
ret i16 %3 ret i16 %3
} }
define i32 @func3(i32 %0, i32 %1) { define signext i32 @func32s(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i32 %1, %0 %3 = add nsw i32 %1, %0
ret i32 %3 ret i32 %3
} }
define i64 @func4(i64 %0, i64 %1) { define i64 @func64s(i64 %0, i64 %1) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.l %s0, %s1, %s0 ; CHECK-NEXT: adds.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i64 %1, %0 %3 = add nsw i64 %1, %0
ret i64 %3 ret i64 %3
} }
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) { define i128 @func128s(i128 %0, i128 %1) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.l %s1, %s3, %s1
; CHECK-NEXT: adds.l %s0, %s2, %s0
; CHECK-NEXT: cmpu.l %s2, %s0, %s2
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2
; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s2
; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i128 %1, %0
ret i128 %3
}
define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i8 %1, %0 %3 = add i8 %1, %0
ret i8 %3 ret i8 %3
} }
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i16 %1, %0 %3 = add i16 %1, %0
ret i16 %3 ret i16 %3
} }
define i32 @func8(i32 %0, i32 %1) { define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i32 %1, %0 %3 = add i32 %1, %0
ret i32 %3 ret i32 %3
} }
define i64 @func9(i64 %0, i64 %1) { define i64 @func64z(i64 %0, i64 %1) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.l %s0, %s1, %s0 ; CHECK-NEXT: adds.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i64 %1, %0 %3 = add i64 %1, %0
ret i64 %3 ret i64 %3
} }
define signext i8 @func13(i8 signext %0) { define i128 @func128z(i128 %0, i128 %1) {
; CHECK-LABEL: func13: ; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.l %s1, %s3, %s1
; CHECK-NEXT: adds.l %s0, %s2, %s0
; CHECK-NEXT: cmpu.l %s2, %s0, %s2
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2
; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s2
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i128 %1, %0
ret i128 %3
}
define signext i8 @funci8s(i8 signext %0) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add i8 %0, 5 %2 = add i8 %0, 5
ret i8 %2 ret i8 %2
} }
define signext i16 @func14(i16 signext %0) { define signext i16 @funci16s(i16 signext %0) {
; CHECK-LABEL: func14: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add i16 %0, 5 %2 = add i16 %0, 5
ret i16 %2 ret i16 %2
} }
define i32 @func15(i32 %0) { define signext i32 @funci32s(i32 signext %0) {
; CHECK-LABEL: func15: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i32 %0, 5 %2 = add nsw i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @func16(i64 %0) { define i64 @funci64s(i64 %0) {
; CHECK-LABEL: func16: ; CHECK-LABEL: funci64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, 5(, %s0) ; CHECK-NEXT: lea %s0, 5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i64 %0, 5 %2 = add nsw i64 %0, 5
ret i64 %2 ret i64 %2
} }
define zeroext i8 @func18(i8 zeroext %0) { define i128 @funci128s(i128 %0) {
; CHECK-LABEL: func18: ; CHECK-LABEL: funci128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, 5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i128 %0, 5
ret i128 %2
}
define zeroext i8 @funci8z(i8 zeroext %0) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add i8 %0, 5 %2 = add i8 %0, 5
ret i8 %2 ret i8 %2
} }
define zeroext i16 @func19(i16 zeroext %0) { define zeroext i16 @funci16z(i16 zeroext %0) {
; CHECK-LABEL: func19: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add i16 %0, 5 %2 = add i16 %0, 5
ret i16 %2 ret i16 %2
} }
define i32 @func20(i32 %0) { define zeroext i32 @funci32z(i32 zeroext %0) {
; CHECK-LABEL: func20: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add i32 %0, 5 %2 = add i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @func21(i64 %0) { define i64 @funci64z(i64 %0) {
; CHECK-LABEL: func21: ; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, 5(, %s0) ; CHECK-NEXT: lea %s0, 5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add i64 %0, 5 %2 = add i64 %0, 5
ret i64 %2 ret i64 %2
} }
define i64 @func26(i64 %0) { define i128 @funci128z(i128 %0) {
; CHECK-LABEL: func26: ; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, 5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%2 = add i128 %0, 5
ret i128 %2
}
define i64 @funci64_2(i64 %0) {
; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: adds.l %s0, %s0, %s1 ; CHECK-NEXT: adds.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i64 %0, 2147483648 %2 = add nsw i64 %0, 2147483648
ret i64 %2 ret i64 %2
} }
define i128 @funci128_2(i128 %0) {
; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, -2147483648
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: adds.l %s2, %s0, %s2
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i128 %0, 2147483648
ret i128 %2
}

llvm/test/CodeGen/VE/div.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divi128(i128, i128) {
; CHECK-LABEL: divi128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s4, __divti3@lo
; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%3 = sdiv i128 %0, %1
ret i128 %3
}
; Function Attrs: norecurse nounwind readnone
define i64 @divi64(i64 %a, i64 %b) { define i64 @divi64(i64 %a, i64 %b) {
; CHECK-LABEL: divi64: ; CHECK-LABEL: divi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.l %s0, %s0, %s1 ; CHECK-NEXT: divs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i64 %a, %b %r = sdiv i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @divi32(i32 %a, i32 %b) { define signext i32 @divi32(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32: ; CHECK-LABEL: divi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 %a, %b %r = sdiv i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divu128(i128, i128) {
; CHECK-LABEL: divu128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s4, __udivti3@lo
; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%3 = udiv i128 %0, %1
ret i128 %3
}
; Function Attrs: norecurse nounwind readnone
define i64 @divu64(i64 %a, i64 %b) { define i64 @divu64(i64 %a, i64 %b) {
; CHECK-LABEL: divu64: ; CHECK-LABEL: divu64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.l %s0, %s0, %s1 ; CHECK-NEXT: divu.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i64 %a, %b %r = udiv i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @divu32(i32 %a, i32 %b) { define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32: ; CHECK-LABEL: divu32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 %a, %b %r = udiv i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @divi16(i16 signext %a, i16 signext %b) { define signext i16 @divi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: divi16: ; CHECK-LABEL: divi16:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i8 %a, %b %r = udiv i8 %a, %b
ret i8 %r ret i8 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divi128ri(i128) {
; CHECK-LABEL: divi128ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __divti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%2 = sdiv i128 %0, 3
ret i128 %2
}
; Function Attrs: norecurse nounwind readnone
define i64 @divi64ri(i64 %a, i64 %b) { define i64 @divi64ri(i64 %a, i64 %b) {
; CHECK-LABEL: divi64ri: ; CHECK-LABEL: divi64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.l %s0, %s0, (62)0 ; CHECK-NEXT: divs.l %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i64 %a, 3 %r = sdiv i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @divi32ri(i32 %a, i32 %b) { define signext i32 @divi32ri(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32ri: ; CHECK-LABEL: divi32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0 ; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 %a, 3 %r = sdiv i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divu128ri(i128) {
; CHECK-LABEL: divu128ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __udivti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%2 = udiv i128 %0, 3
ret i128 %2
}
; Function Attrs: norecurse nounwind readnone
define i64 @divu64ri(i64 %a, i64 %b) { define i64 @divu64ri(i64 %a, i64 %b) {
; CHECK-LABEL: divu64ri: ; CHECK-LABEL: divu64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.l %s0, %s0, (62)0 ; CHECK-NEXT: divu.l %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i64 %a, 3 %r = udiv i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @divu32ri(i32 %a, i32 %b) { define zeroext i32 @divu32ri(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32ri: ; CHECK-LABEL: divu32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.w %s0, %s0, (62)0 ; CHECK-NEXT: divu.w %s0, %s0, (62)0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 %a, 3 %r = udiv i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divi128li(i128) {
; CHECK-LABEL: divi128li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __divti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%2 = sdiv i128 3, %0
ret i128 %2
}
; Function Attrs: norecurse nounwind readnone
define i64 @divi64li(i64 %a, i64 %b) { define i64 @divi64li(i64 %a, i64 %b) {
; CHECK-LABEL: divi64li: ; CHECK-LABEL: divi64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.l %s0, 3, %s1 ; CHECK-NEXT: divs.l %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i64 3, %b %r = sdiv i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @divi32li(i32 %a, i32 %b) { define signext i32 @divi32li(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32li: ; CHECK-LABEL: divi32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.w.sx %s0, 3, %s1 ; CHECK-NEXT: divs.w.sx %s0, 3, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 3, %b %r = sdiv i32 3, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divu128li(i128) {
; CHECK-LABEL: divu128li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __udivti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%2 = udiv i128 3, %0
ret i128 %2
}
; Function Attrs: norecurse nounwind readnone
define i64 @divu64li(i64 %a, i64 %b) { define i64 @divu64li(i64 %a, i64 %b) {
; CHECK-LABEL: divu64li: ; CHECK-LABEL: divu64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.l %s0, 3, %s1 ; CHECK-NEXT: divu.l %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i64 3, %b %r = udiv i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @divu32li(i32 %a, i32 %b) { define zeroext i32 @divu32li(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32li: ; CHECK-LABEL: divu32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.w %s0, 3, %s1 ; CHECK-NEXT: divu.w %s0, 3, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 3, %b %r = udiv i32 3, %b
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/VE/multiply.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func1(i8 signext %a, i8 signext %b) { define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i8 %b, %a %r = mul i8 %b, %a
ret i8 %r ret i8 %r
} }
define signext i16 @func2(i16 signext %a, i16 signext %b) { define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i16 %b, %a %r = mul i16 %b, %a
ret i16 %r ret i16 %r
} }
define i32 @func3(i32 %a, i32 %b) { define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i32 %b, %a %r = mul nsw i32 %b, %a
ret i32 %r ret i32 %r
} }
define i64 @func4(i64 %a, i64 %b) { define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.l %s0, %s1, %s0 ; CHECK-NEXT: muls.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i64 %b, %a %r = mul nsw i64 %b, %a
ret i64 %r ret i64 %r
} }
define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) { define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func5: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s1
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: lea %s0, __multi3@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s2, 0, %s5
; CHECK-NEXT: or %s3, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i128 %b, %a
ret i128 %r
}
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i8 %b, %a %r = mul i8 %b, %a
ret i8 %r ret i8 %r
} }
define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i16 %b, %a %r = mul i16 %b, %a
ret i16 %r ret i16 %r
} }
define i32 @func7(i32 %a, i32 %b) { define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i32 %b, %a %r = mul i32 %b, %a
ret i32 %r ret i32 %r
} }
define i64 @func8(i64 %a, i64 %b) { define i64 @func64z(i64 %a, i64 %b) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.l %s0, %s1, %s0 ; CHECK-NEXT: muls.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i64 %b, %a %r = mul i64 %b, %a
ret i64 %r ret i64 %r
} }
define signext i8 @func9(i8 signext %a) { define i128 @func128z(i128 %a, i128 %b) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s1
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: lea %s0, __multi3@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s2, 0, %s5
; CHECK-NEXT: or %s3, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i128 %b, %a
ret i128 %r
}
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i8 %a, 5 %r = mul i8 %a, 5
ret i8 %r ret i8 %r
} }
define signext i16 @func10(i16 signext %a) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: func10: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i16 %a, 5 %r = mul i16 %a, 5
ret i16 %r ret i16 %r
} }
define i32 @func11(i32 %a) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: func11: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i32 %a, 5 %r = mul nsw i32 %a, 5
ret i32 %r ret i32 %r
} }
define i64 @func12(i64 %a) { define i64 @funci64(i64 %a) {
; CHECK-LABEL: func12: ; CHECK-LABEL: funci64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.l %s0, 5, %s0 ; CHECK-NEXT: muls.l %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i64 %a, 5 %r = mul nsw i64 %a, 5
ret i64 %r ret i64 %r
} }
define zeroext i8 @func13(i8 zeroext %a) { define i128 @funci128(i128 %a) {
; CHECK-LABEL: func13: ; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __multi3@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s2)
; CHECK-NEXT: or %s2, 5, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i128 %a, 5
ret i128 %r
}
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i8 %a, 5 %r = mul i8 %a, 5
ret i8 %r ret i8 %r
} }
define zeroext i16 @func14(i16 zeroext %a) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: func14: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i16 %a, 5 %r = mul i16 %a, 5
ret i16 %r ret i16 %r
} }
define i32 @func15(i32 %a) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: func15: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i32 %a, 5 %r = mul i32 %a, 5
ret i32 %r ret i32 %r
} }
define i64 @func16(i64 %a) { define i64 @funci64z(i64 %a) {
; CHECK-LABEL: func16: ; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: muls.l %s0, 5, %s0 ; CHECK-NEXT: muls.l %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i64 %a, 5 %r = mul i64 %a, 5
ret i64 %r ret i64 %r
} }
define i32 @func17(i32 %a) { define i128 @funci128z(i128 %a) {
; CHECK-LABEL: func17: ; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __multi3@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s2)
; CHECK-NEXT: or %s2, 5, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i128 %a, 5
ret i128 %r
}
define zeroext i32 @funci32z_2(i32 zeroext %a) {
; CHECK-LABEL: funci32z_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sla.w.sx %s0, %s0, 31 ; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = shl i32 %a, 31 %r = shl i32 %a, 31
ret i32 %r ret i32 %r
} }
define i64 @func18(i64 %a) { define i64 @funci64_2(i64 %a) {
; CHECK-LABEL: func18: ; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 31 ; CHECK-NEXT: sll %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = shl nsw i64 %a, 31 %r = shl nsw i64 %a, 31
ret i64 %r ret i64 %r
} }
define i128 @funci128_2(i128 %a) {
; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: srl %s2, %s0, 33
; CHECK-NEXT: sll %s1, %s1, 31
; CHECK-NEXT: or %s1, %s1, %s2
; CHECK-NEXT: sll %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
%r = shl nsw i128 %a, 31
ret i128 %r
}

llvm/test/CodeGen/VE/rem.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remi128(i128 %a, i128 %b) {
; CHECK-LABEL: remi128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s4, __modti3@lo
; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = srem i128 %a, %b
ret i128 %r
}
; Function Attrs: norecurse nounwind readnone
define i64 @remi64(i64 %a, i64 %b) { define i64 @remi64(i64 %a, i64 %b) {
; CHECK-LABEL: remi64: ; CHECK-LABEL: remi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.l %s2, %s0, %s1 ; CHECK-NEXT: divs.l %s2, %s0, %s1
; CHECK-NEXT: muls.l %s1, %s2, %s1 ; CHECK-NEXT: muls.l %s1, %s2, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i64 %a, %b %r = srem i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @remi32(i32 %a, i32 %b) { define signext i32 @remi32(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: remi32: ; CHECK-LABEL: remi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i32 %a, %b %r = srem i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remu128(i128 %a, i128 %b) {
; CHECK-LABEL: remu128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s4, __umodti3@lo
; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = urem i128 %a, %b
ret i128 %r
}
; Function Attrs: norecurse nounwind readnone
define i64 @remu64(i64 %a, i64 %b) { define i64 @remu64(i64 %a, i64 %b) {
; CHECK-LABEL: remu64: ; CHECK-LABEL: remu64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.l %s2, %s0, %s1 ; CHECK-NEXT: divu.l %s2, %s0, %s1
; CHECK-NEXT: muls.l %s1, %s2, %s1 ; CHECK-NEXT: muls.l %s1, %s2, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i64 %a, %b %r = urem i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @remu32(i32 %a, i32 %b) { define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: remu32: ; CHECK-LABEL: remu32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.w %s2, %s0, %s1 ; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i32 %a, %b %r = urem i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @remi16(i16 signext %a, i16 signext %b) { define signext i16 @remi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: remi16: ; CHECK-LABEL: remi16:
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i8 %a, %b %r = urem i8 %a, %b
ret i8 %r ret i8 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remi64ri(i64 %a, i64 %b) { define i128 @remi128ri(i128 %a) {
; CHECK-LABEL: remi128ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __modti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = srem i128 %a, 3
ret i128 %r
}
; Function Attrs: norecurse nounwind readnone
define i64 @remi64ri(i64 %a) {
; CHECK-LABEL: remi64ri: ; CHECK-LABEL: remi64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.l %s1, %s0, (62)0 ; CHECK-NEXT: divs.l %s1, %s0, (62)0
; CHECK-NEXT: muls.l %s1, 3, %s1 ; CHECK-NEXT: muls.l %s1, 3, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i64 %a, 3 %r = srem i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @remi32ri(i32 %a, i32 %b) { define signext i32 @remi32ri(i32 signext %a) {
; CHECK-LABEL: remi32ri: ; CHECK-LABEL: remi32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0 ; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i32 %a, 3 %r = srem i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remu64ri(i64 %a, i64 %b) { define i128 @remu128ri(i128 %a) {
; CHECK-LABEL: remu128ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __umodti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = urem i128 %a, 3
ret i128 %r
}
; Function Attrs: norecurse nounwind readnone
define i64 @remu64ri(i64 %a) {
; CHECK-LABEL: remu64ri: ; CHECK-LABEL: remu64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.l %s1, %s0, (62)0 ; CHECK-NEXT: divu.l %s1, %s0, (62)0
; CHECK-NEXT: muls.l %s1, 3, %s1 ; CHECK-NEXT: muls.l %s1, 3, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i64 %a, 3 %r = urem i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @remu32ri(i32 %a, i32 %b) { define zeroext i32 @remu32ri(i32 zeroext %a) {
; CHECK-LABEL: remu32ri: ; CHECK-LABEL: remu32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.w %s1, %s0, (62)0 ; CHECK-NEXT: divu.w %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i32 %a, 3 %r = urem i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remi128li(i128 %a) {
; CHECK-LABEL: remi128li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __modti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = srem i128 3, %a
ret i128 %r
}
; Function Attrs: norecurse nounwind readnone
define i64 @remi64li(i64 %a, i64 %b) { define i64 @remi64li(i64 %a, i64 %b) {
; CHECK-LABEL: remi64li: ; CHECK-LABEL: remi64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.l %s0, 3, %s1 ; CHECK-NEXT: divs.l %s0, 3, %s1
; CHECK-NEXT: muls.l %s0, %s0, %s1 ; CHECK-NEXT: muls.l %s0, %s0, %s1
; CHECK-NEXT: subs.l %s0, 3, %s0 ; CHECK-NEXT: subs.l %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i64 3, %b %r = srem i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @remi32li(i32 %a, i32 %b) { define signext i32 @remi32li(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: remi32li: ; CHECK-LABEL: remi32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divs.w.sx %s0, 3, %s1 ; CHECK-NEXT: divs.w.sx %s0, 3, %s1
; CHECK-NEXT: muls.w.sx %s0, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0 ; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i32 3, %b %r = srem i32 3, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remu128li(i128) {
; CHECK-LABEL: remu128li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __umodti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%2 = urem i128 3, %0
ret i128 %2
}
; Function Attrs: norecurse nounwind readnone
define i64 @remu64li(i64 %a, i64 %b) { define i64 @remu64li(i64 %a, i64 %b) {
; CHECK-LABEL: remu64li: ; CHECK-LABEL: remu64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.l %s0, 3, %s1 ; CHECK-NEXT: divu.l %s0, 3, %s1
; CHECK-NEXT: muls.l %s0, %s0, %s1 ; CHECK-NEXT: muls.l %s0, %s0, %s1
; CHECK-NEXT: subs.l %s0, 3, %s0 ; CHECK-NEXT: subs.l %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i64 3, %b %r = urem i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @remu32li(i32 %a, i32 %b) { define zeroext i32 @remu32li(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: remu32li: ; CHECK-LABEL: remu32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: divu.w %s0, 3, %s1 ; CHECK-NEXT: divu.w %s0, 3, %s1
; CHECK-NEXT: muls.w.sx %s0, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0 ; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i32 3, %b %r = urem i32 3, %b
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/VE/subtraction.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func1(i8 signext %0, i8 signext %1) { define signext i8 @func8s(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i8 %0, %1 %3 = sub i8 %0, %1
ret i8 %3 ret i8 %3
} }
define signext i16 @func2(i16 signext %0, i16 signext %1) { define signext i16 @func16s(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i16 %0, %1 %3 = sub i16 %0, %1
ret i16 %3 ret i16 %3
} }
define i32 @func3(i32 %0, i32 %1) { define signext i32 @func32s(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub nsw i32 %0, %1 %3 = sub nsw i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func4(i64 %0, i64 %1) { define i64 @func64s(i64 %0, i64 %1) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub nsw i64 %0, %1 %3 = sub nsw i64 %0, %1
ret i64 %3 ret i64 %3
} }
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) { define i128 @func128s(i128 %0, i128 %1) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: cmpu.l %s3, %s0, %s2
; CHECK-NEXT: or %s4, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s3
; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: subs.l %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub nsw i128 %0, %1
ret i128 %3
}
define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i8 %0, %1 %3 = sub i8 %0, %1
ret i8 %3 ret i8 %3
} }
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i16 %0, %1 %3 = sub i16 %0, %1
ret i16 %3 ret i16 %3
} }
define i32 @func8(i32 %0, i32 %1) { define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i32 %0, %1 %3 = sub i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func9(i64 %0, i64 %1) { define i64 @func64z(i64 %0, i64 %1) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i64 %0, %1 %3 = sub i64 %0, %1
ret i64 %3 ret i64 %3
} }
define signext i8 @func13(i8 signext %0, i8 signext %1) { define i128 @func128z(i128 %0, i128 %1) {
; CHECK-LABEL: func13: ; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: cmpu.l %s3, %s0, %s2
; CHECK-NEXT: or %s4, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s3
; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: subs.l %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i128 %0, %1
ret i128 %3
}
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i8 %0, -5 %ret = add i8 %a, -5
ret i8 %3 ret i8 %ret
} }
define signext i16 @func14(i16 signext %0, i16 signext %1) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: func14: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i16 %0, -5 %ret = add i16 %a, -5
ret i16 %3 ret i16 %ret
} }
define i32 @func15(i32 %0, i32 %1) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: func15: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i32 %0, -5 %ret = add i32 %a, -5
ret i32 %3 ret i32 %ret
} }
define i64 @func16(i64 %0, i64 %1) { define i64 @funci64s(i64 %a) {
; CHECK-LABEL: func16: ; CHECK-LABEL: funci64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, -5(, %s0) ; CHECK-NEXT: lea %s0, -5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i64 %0, -5 %ret = add nsw i64 %a, -5
ret i64 %3 ret i64 %ret
}
define i128 @funci128s(i128 %0) {
; CHECK-LABEL: funci128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, -5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i128 %0, -5
ret i128 %2
} }
define zeroext i8 @func18(i8 zeroext %0, i8 zeroext %1) { define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: func18: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i8 %0, -5 %ret = add i8 %a, -5
ret i8 %3 ret i8 %ret
} }
define zeroext i16 @func19(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: func19: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i16 %0, -5 %ret = add i16 %a, -5
ret i16 %3 ret i16 %ret
} }
define i32 @func20(i32 %0, i32 %1) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: func20: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i32 %0, -5 %ret = add i32 %a, -5
ret i32 %3 ret i32 %ret
} }
define i64 @func21(i64 %0, i64 %1) { define i64 @funci64z(i64 %a) {
; CHECK-LABEL: func21: ; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, -5(, %s0) ; CHECK-NEXT: lea %s0, -5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add i64 %0, -5 %ret = add i64 %a, -5
ret i64 %3 ret i64 %ret
}
define i128 @funci128z(i128 %0) {
; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, -5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%2 = add i128 %0, -5
ret i128 %2
} }
define i64 @func26(i64 %0, i64 %1) { define i64 @funci64_2(i64 %a) {
; CHECK-LABEL: func26: ; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, -2147483648(, %s0) ; CHECK-NEXT: lea %s0, -2147483648(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i64 %0, -2147483648 %ret = add nsw i64 %a, -2147483648
ret i64 %3 ret i64 %ret
} }
define i128 @funci128_2(i128 %0) {
; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, -2147483648(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i128 %0, -2147483648
ret i128 %2
}