[AVR] Implement disassembly of 32-bit instructions

[aykevl]

Summary

This needed two fixes:

• 32-bit instructions were read in the wrong order. The machine code swaps the two 16-bit instruction words, which wasn't undone when decoding instructions.
• Jump and call instructions don't encode the lowest address bit, which is always zero. Therefore, the address needed to be shifted by one to fix that.

---

Note: I didn't add all address decode tests to the call instruction as all of that should already be tested with the jmp instruction (which has the same format). I can of course add it if needed.

llvm/lib/Target/AVR/AVRInstrInfo.td

def brtarget_13 : Operand<OtherVT>
     let PrintMethod   = "printPCRelImm";
     let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
 }
 
 // The target of a 22 or 16-bit call/jmp instruction.
 def call_target : Operand<iPTR>
 {
     let EncoderMethod = "encodeCallTarget";
+    let DecoderMethod = "decodeCallTarget";
 }
 
 // A 16-bit address (which can lead to an R_AVR_16 relocation).
 def imm16 : Operand<i16>
 {
     let EncoderMethod = "encodeImm<AVR::fixup_16, 2>";
 }
 

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder);
 
 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder);
 
 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder);
 
+static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
+                                     uint64_t Address, const void *Decoder);
+
 #include "AVRGenDisassemblerTables.inc"
 
 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
   unsigned addr = 0;
   addr |= fieldFromInstruction(Insn, 0, 4);
   addr |= fieldFromInstruction(Insn, 9, 2) << 4;
   unsigned reg = fieldFromInstruction(Insn, 4, 5);
static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
   unsigned addr = fieldFromInstruction(Insn, 3, 5);
   unsigned b = fieldFromInstruction(Insn, 0, 3);
   Inst.addOperand(MCOperand::createImm(addr));
   Inst.addOperand(MCOperand::createImm(b));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
+                                     uint64_t Address, const void *Decoder) {
+  // Call targets need to be shifted left by one so this needs a custom
+  // decoder.
+  Inst.addOperand(MCOperand::createImm(Field << 1));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
                                       uint64_t &Size, uint32_t &Insn) {
   if (Bytes.size() < 2) {
     Size = 0;
     return MCDisassembler::Fail;
   }
 
   Size = 2;
   Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
                                       uint64_t &Size, uint32_t &Insn) {
 
   if (Bytes.size() < 4) {
     Size = 0;
     return MCDisassembler::Fail;
   }
 
   Size = 4;
-  Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
+  Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
 
   return MCDisassembler::Success;
 }
 
 static const uint8_t *getDecoderTable(uint64_t Size) {
 
   switch (Size) {
     case 2: return DecoderTable16;

llvm/test/MC/AVR/inst-call.s

 ; RUN: llvm-mc -triple avr -mattr=jmpcall -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=jmpcall < %s | llvm-objdump -dr --mattr=jmpcall - | FileCheck -check-prefix=CHECK-INST %s
 
 
 foo:
 
   call  4096
   call  -124
   call   -12
   call   0
 
 ; CHECK: call  4096                 ; encoding: [0x0e,0x94,0x00,0x08]
 ; CHECK: call -124                  ; encoding: [0xff,0x95,0xc2,0xff]
 ; CHECK: call -12                   ; encoding: [0xff,0x95,0xfa,0xff]
 ; CHECK: call  0                    ; encoding: [0x0e,0x94,0x00,0x00]
+
+
+; CHECK-INST: call 4096
+; CHECK-INST: call 8388484
+; CHECK-INST: call 8388596
+; CHECK-INST: call 0

llvm/test/MC/AVR/inst-jmp.s

 ; RUN: llvm-mc -triple avr -mattr=jmpcall -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=jmpcall < %s | llvm-objdump -dr --mattr=jmpcall - | FileCheck -check-prefix=CHECK-INST %s
 
 
 foo:
 
   jmp   200
   jmp  -12
   jmp   80
   jmp   0
 
   jmp foo+1
 
+  jmp   0x03fffe ; Inst{16-0}  or k{16-0}
+  jmp   0x7c0000 ; Inst{24-20} or k{21-17}
+  jmp   0x7ffffe ; all bits set
+
 ; CHECK: jmp  200                  ; encoding: [0x0c,0x94,0x64,0x00]
 ; CHECK: jmp -12                   ; encoding: [0xfd,0x95,0xfa,0xff]
 ; CHECK: jmp  80                   ; encoding: [0x0c,0x94,0x28,0x00]
 ; CHECK: jmp  0                    ; encoding: [0x0c,0x94,0x00,0x00]
 
 ; CHECK: jmp foo+1                 ; encoding: [0x0c'A',0x94'A',0b00AAAAAA,0x00]
 ; CHECK:                           ;   fixup A - offset: 0, value: foo+1, kind: fixup_call
+
+; CHECK: jmp 262142                ; encoding: [0x0d,0x94,0xff,0xff]
+; CHECK: jmp 8126464               ; encoding: [0xfc,0x95,0x00,0x00]
+; CHECK: jmp 8388606               ; encoding: [0xfd,0x95,0xff,0xff]
+
+
+; CHECK-INST: jmp 200
+; CHECK-INST: jmp 8388596
+; CHECK-INST: jmp 80
+; CHECK-INST: jmp 0
+; CHECK-INST: jmp 0
+; CHECK-INST:     R_AVR_CALL .text+0x1
+; CHECK-INST: jmp 262142
+; CHECK-INST: jmp 8126464
+; CHECK-INST: jmp 8388606

llvm/test/MC/AVR/inst-lds.s

 ; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -dr --mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
 
 
 foo:
   lds r16, 241
   lds r29, 190
   lds r22, 172
   lds r27, 92
   lds r4, SYMBOL+12
 
 ; CHECK: lds r16, 241                 ; encoding: [0x00,0x91,0xf1,0x00]
 ; CHECK: lds r29, 190                 ; encoding: [0xd0,0x91,0xbe,0x00]
 ; CHECK: lds r22, 172                 ; encoding: [0x60,0x91,0xac,0x00]
 ; CHECK: lds r27, 92                  ; encoding: [0xb0,0x91,0x5c,0x00]
 ; CHECK: lds r4, SYMBOL+12            ; encoding: [0x40,0x90,A,A]
 ; CHECK:                              ;   fixup A - offset: 2, value: SYMBOL+12, kind: fixup_16
+
+
+; CHECK-INST: lds r16, 241
+; CHECK-INST: lds r29, 190
+; CHECK-INST: lds r22, 172
+; CHECK-INST: lds r27, 92
+; CHECK-INST: lds r4,  0
+; CHECK-INST:     R_AVR_16 SYMBOL+0xc

llvm/test/MC/AVR/inst-sts.s

 ; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -dr --mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
 
 
 foo:
 
   sts 3,   r5
   sts 255, r7
   sts SYMBOL+1, r25
 
 ; CHECK:  sts 3,   r5                 ; encoding: [0x50,0x92,0x03,0x00]
 ; CHECK:  sts 255, r7                 ; encoding: [0x70,0x92,0xff,0x00]
 ; CHECK:  sts SYMBOL+1, r25           ; encoding: [0x90,0x93,A,A]
 ; CHECK:                              ;   fixup A - offset: 2, value: SYMBOL+1, kind: fixup_16
 
+
+; CHECK-INST: sts 3, r5
+; CHECK-INST: sts 255, r7
+; CHECK-INST: sts 0, r25
+; CHECK-INST:     R_AVR_16 SYMBOL+0x1