GlobalISel: Fix some artifact combiner worklist inconsistencies

[arsenm]

Summary

In one case, UpdateDefs was not getting set and a dead SmallVector
constructed In another, it was adding new vreg defs to the updated set
which should be unnecessary. This also wasn't considering the multiple
defs of G_UNMERGE_VALUES.

Also increase the small vector sizes for merge/unmerge operands to the
usual semi-arbitrary 8. While debugging these, I'm usually seeing
merges and unmerges with at least 4 uses/defs.

I haven't run into an actual problem from any of these though.

[aemerson]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

755

A G_MERGE should never have multiple defs?

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

755

This is handling G_UNMERGE_VALUES, not merge

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

755

Oh I can't read, the user is G_UNEMRGE

[arsenm]

Drop unnecessary part

[arsenm]

2ec1267ecec372e55aed0995917b601f7cf61c5e

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

if (SrcMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) {
 
         LLVM_DEBUG(
             dbgs() << "Combining G_TRUNC(G_MERGE_VALUES) to G_MERGE_VALUES: "
                    << MI);
 
         const unsigned NumSrcs = DstSize / MergeSrcSize;
         assert(NumSrcs < SrcMI->getNumOperands() - 1 &&
                "trunc(merge) should require less inputs than merge");
-        SmallVector<Register, 2> SrcRegs(NumSrcs);
+        SmallVector<Register, 8> SrcRegs(NumSrcs);
         for (unsigned i = 0; i < NumSrcs; ++i)
           SrcRegs[i] = SrcMI->getOperand(i + 1).getReg();
 
         Builder.buildMerge(DstReg, SrcRegs);
         UpdatedDefs.push_back(DstReg);
       } else {
         // Unable to combine
         return false;
if (CastOpc == TargetOpcode::G_TRUNC) {
 
         if (isInstUnsupported(
                 {TargetOpcode::G_UNMERGE_VALUES, {UnmergeTy, CastSrcTy}}))
           return false;
 
         Builder.setInstr(MI);
         auto NewUnmerge = Builder.buildUnmerge(UnmergeTy, CastSrcReg);
 
-        SmallVector<Register, 8> Regs(NumDefs);
-        for (unsigned I = 0; I != NumDefs; ++I)
-          Builder.buildTrunc(MI.getOperand(I), NewUnmerge.getReg(I));
+        for (unsigned I = 0; I != NumDefs; ++I) {
+          Register DefReg = MI.getOperand(I).getReg();
+          UpdatedDefs.push_back(DefReg);
+          Builder.buildTrunc(DefReg, NewUnmerge.getReg(I));
+        }
 
         markInstAndDefDead(MI, CastMI, DeadInsts);
         return true;
       }
 
       if (CastSrcTy.isScalar() && SrcTy.isScalar() && !DestTy.isVector()) {
         //  %1:_(s16) = G_TRUNC %0(s32)
         //  %2:_(s8), %3:_(s8) = G_UNMERGE_VALUES %1
         // =>
         //  %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %0
 
         // Unmerge(trunc) can be combined if the trunc source size is a multiple
         // of the unmerge destination size
         if (CastSrcSize % DestSize != 0)
           return false;
 
         // Check if the new unmerge is supported
         if (isInstUnsupported(
                 {TargetOpcode::G_UNMERGE_VALUES, {DestTy, CastSrcTy}}))
           return false;
 
         // Gather the original destination registers and create new ones for the
         // unused bits
         const unsigned NewNumDefs = CastSrcSize / DestSize;
-        SmallVector<Register, 2> DstRegs(NewNumDefs);
+        SmallVector<Register, 8> DstRegs(NewNumDefs);
         for (unsigned Idx = 0; Idx < NewNumDefs; ++Idx) {
           if (Idx < NumDefs)
             DstRegs[Idx] = MI.getOperand(Idx).getReg();
           else
             DstRegs[Idx] = MRI.createGenericVirtualRegister(DestTy);
         }
 
         // Build new unmerge
         Builder.setInstr(MI);
         Builder.buildUnmerge(DstRegs, CastSrcReg);
-        UpdatedDefs.append(DstRegs.begin(), DstRegs.begin() + NumDefs);
+        UpdatedDefs.append(DstRegs.begin(), DstRegs.begin() + NewNumDefs);
         markInstAndDefDead(MI, CastMI, DeadInsts);
         return true;
       }
     }
 
     // TODO: support combines with other casts as well
     return false;
   }
if (NumMergeRegs < NumDefs) {
       //   %1 = G_MERGE_VALUES %4, %5
       //   %9, %10, %11, %12 = G_UNMERGE_VALUES %1
       // to
       //   %9, %10 = G_UNMERGE_VALUES %4
       //   %11, %12 = G_UNMERGE_VALUES %5
 
       const unsigned NewNumDefs = NumDefs / NumMergeRegs;
       for (unsigned Idx = 0; Idx < NumMergeRegs; ++Idx) {
-        SmallVector<Register, 2> DstRegs;
+        SmallVector<Register, 8> DstRegs;
         for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs;
              ++j, ++DefIdx)
           DstRegs.push_back(MI.getOperand(DefIdx).getReg());
 
         if (ConvertOp) {
           LLT MergeSrcTy = MRI.getType(MergeI->getOperand(1).getReg());
 
           // This is a vector that is being split and casted. Extract to the
if (NumMergeRegs < NumDefs) {
       //   %6 = G_MERGE_VALUES %17, %18, %19, %20
       //   %7, %8 = G_UNMERGE_VALUES %6
       // to
       //   %7 = G_MERGE_VALUES %17, %18
       //   %8 = G_MERGE_VALUES %19, %20
 
       const unsigned NumRegs = NumMergeRegs / NumDefs;
       for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
-        SmallVector<Register, 2> Regs;
+        SmallVector<Register, 8> Regs;
         for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs;
              ++j, ++Idx)
           Regs.push_back(MergeI->getOperand(Idx).getReg());
 
         Register DefReg = MI.getOperand(DefIdx).getReg();
         Builder.buildMerge(DefReg, Regs);
         UpdatedDefs.push_back(DefReg);
       }
case TargetOpcode::G_UNMERGE_VALUES:
       break;
     case TargetOpcode::G_MERGE_VALUES:
       // If any of the users of this merge are an unmerge, then add them to the
       // artifact worklist in case there's folding that can be done looking up.
       for (MachineInstr &U : MRI.use_instructions(MI.getOperand(0).getReg())) {
         if (U.getOpcode() == TargetOpcode::G_UNMERGE_VALUES ||
             U.getOpcode() == TargetOpcode::G_TRUNC) {
           UpdatedDefs.push_back(MI.getOperand(0).getReg());
           break;
         }
       }
       break;
     case TargetOpcode::G_EXTRACT:
       Changed = tryCombineExtract(MI, DeadInsts, UpdatedDefs);
       break;
     case TargetOpcode::G_TRUNC:
       Changed = tryCombineTrunc(MI, DeadInsts, UpdatedDefs, WrapperObserver);