[VE] Support convert instructions in MC layer

[kaz7]

Summary

Add CVTSQ/CVTDQ/CVTQD/CVTQS instructions. Add regression tests for
them and other convert instructions of asmparser, mccodeemitter, and
disassembler. In order to add those instructions, support RD operands
in asmparser, mccodeemitter, and disassembler.

[simoll]

Few nits.

llvm/lib/Target/VE/VE.h

301

unreachable + return

322

unreachable + return

llvm/lib/Target/VE/VEInstrInfo.td

406

Is this commented out for future implementation?

[kaz7]

Thank you for reviewing. I'll update code soon.

llvm/lib/Target/VE/VEInstrInfo.td

406

Thank you. I was checking the behavior of EncoderMethod for other purpose. I forgot to change it back.

[kaz7]

Update following suggestions. Thank you.

[simoll]

Thanks!

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

#include "VEGenAsmMatcher.inc"
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   // Custom parse functions for VE specific operands.
   OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
   OperandMatchResultTy parseMEMAsOperand(OperandVector &Operands);
   OperandMatchResultTy parseCCOpOperand(OperandVector &Operands);
+  OperandMatchResultTy parseRDOpOperand(OperandVector &Operands);
   OperandMatchResultTy parseMImmOperand(OperandVector &Operands);
   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
   OperandMatchResultTy parseVEAsmOperand(std::unique_ptr<VEOperand> &Operand);
   // Split the mnemonic stripping conditional code and quantifiers
   StringRef splitMnemonic(StringRef Name, SMLoc NameLoc,
                           OperandVector *Operands);
 
 public:
enum KindTy {
     k_MemoryRegImmImm,  // base=reg, index=imm, disp=imm
     k_MemoryZeroRegImm, // base=0, index=reg, disp=imm
     k_MemoryZeroImmImm, // base=0, index=imm, disp=imm
     // SX-Aurora AS form is disp(base).
     k_MemoryRegImm,  // base=reg, disp=imm
     k_MemoryZeroImm, // base=0, disp=imm
     // Other special cases for Aurora VE
     k_CCOp,   // condition code
+    k_RDOp,   // rounding mode
     k_MImmOp, // Special immediate value of sequential bit stream of 0 or 1.
   } Kind;
 
   SMLoc StartLoc, EndLoc;
 
   struct Token {
     const char *Data;
     unsigned Length;
struct MemOp {
     const MCExpr *Index;
     const MCExpr *Offset;
   };
 
   struct CCOp {
     unsigned CCVal;
   };
 
+  struct RDOp {
+    unsigned RDVal;
+  };
+
   struct MImmOp {
     const MCExpr *Val;
     bool M0Flag;
   };
 
   union {
     struct Token Tok;
     struct RegOp Reg;
     struct ImmOp Imm;
     struct MemOp Mem;
     struct CCOp CC;
+    struct RDOp RD;
     struct MImmOp MImm;
   };
 
 public:
   VEOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 
   bool isToken() const override { return Kind == k_Token; }
   bool isReg() const override { return Kind == k_Register; }
   bool isImm() const override { return Kind == k_Immediate; }
   bool isMem() const override {
     return isMEMrri() || isMEMrii() || isMEMzri() || isMEMzii() || isMEMri() ||
            isMEMzi();
   }
   bool isMEMrri() const { return Kind == k_MemoryRegRegImm; }
   bool isMEMrii() const { return Kind == k_MemoryRegImmImm; }
   bool isMEMzri() const { return Kind == k_MemoryZeroRegImm; }
   bool isMEMzii() const { return Kind == k_MemoryZeroImmImm; }
   bool isMEMri() const { return Kind == k_MemoryRegImm; }
   bool isMEMzi() const { return Kind == k_MemoryZeroImm; }
   bool isCCOp() const { return Kind == k_CCOp; }
+  bool isRDOp() const { return Kind == k_RDOp; }
   bool isZero() {
     if (!isImm())
       return false;
 
     // Constant case
     if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
       int64_t Value = ConstExpr->getValue();
       return Value == 0;
void setMemOffset(const MCExpr *off) {
     Mem.Offset = off;
   }
 
   unsigned getCCVal() const {
     assert((Kind == k_CCOp) && "Invalid access!");
     return CC.CCVal;
   }
 
+  unsigned getRDVal() const {
+    assert((Kind == k_RDOp) && "Invalid access!");
+    return RD.RDVal;
+  }
+
   const MCExpr *getMImmVal() const {
     assert((Kind == k_MImmOp) && "Invalid access!");
     return MImm.Val;
   }
   bool getM0Flag() const {
     assert((Kind == k_MImmOp) && "Invalid access!");
     return MImm.M0Flag;
   }
case k_MemoryRegImm:
       break;
     case k_MemoryZeroImm:
       assert(getMemOffset() != nullptr);
       OS << "Mem: 0+" << *getMemOffset() << "\n";
       break;
     case k_CCOp:
       OS << "CCOp: " << getCCVal() << "\n";
       break;
+    case k_RDOp:
+      OS << "RDOp: " << getRDVal() << "\n";
+      break;
     case k_MImmOp:
       OS << "MImm: (" << getMImmVal() << (getM0Flag() ? ")0" : ")1") << "\n";
       break;
     }
   }
 
   void addRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
public:
 
   void addUImm6Operands(MCInst &Inst, unsigned N) const {
     addImmOperands(Inst, N);
   }
 
   void addUImm7Operands(MCInst &Inst, unsigned N) const {
     addImmOperands(Inst, N);
   }
+
   void addSImm7Operands(MCInst &Inst, unsigned N) const {
     addImmOperands(Inst, N);
   }
 
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     // Add as immediate when possible.  Null MCExpr = 0.
     if (!Expr)
       Inst.addOperand(MCOperand::createImm(0));
public:
   }
 
   void addCCOpOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     Inst.addOperand(MCOperand::createImm(getCCVal()));
   }
 
+  void addRDOpOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+
+    Inst.addOperand(MCOperand::createImm(getRDVal()));
+  }
+
   void addMImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const auto *ConstExpr = dyn_cast<MCConstantExpr>(getMImmVal());
     assert(ConstExpr && "Null operands!");
     int64_t Value = ConstExpr->getValue();
     if (getM0Flag())
       Value += 64;
     Inst.addOperand(MCOperand::createImm(Value));
static std::unique_ptr<VEOperand> CreateCCOp(unsigned CCVal, SMLoc S,
                                                SMLoc E) {
     auto Op = std::make_unique<VEOperand>(k_CCOp);
     Op->CC.CCVal = CCVal;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
+  static std::unique_ptr<VEOperand> CreateRDOp(unsigned RDVal, SMLoc S,
+                                               SMLoc E) {
+    auto Op = std::make_unique<VEOperand>(k_RDOp);
+    Op->RD.RDVal = RDVal;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
+  }
+
   static std::unique_ptr<VEOperand> CreateMImm(const MCExpr *Val, bool Flag,
                                                SMLoc S, SMLoc E) {
     auto Op = std::make_unique<VEOperand>(k_MImmOp);
     Op->MImm.Val = Val;
     Op->MImm.M0Flag = Flag;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
if (CondCode != VECC::UNKNOWN &&
     if (!SuffixStr.empty())
       Operands->push_back(VEOperand::CreateToken(SuffixStr, SuffixLoc));
   } else {
     Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
   }
   return Name;
 }
 
+static StringRef parseRD(StringRef Name, unsigned Prefix, SMLoc NameLoc,
+                         OperandVector *Operands) {
+  // Parse instructions with a conditional code. For example, 'cvt.w.d.sx.rz'
+  // is converted into two operands 'cvt.w.d.sx' and '.rz'.
+  StringRef RD = Name.substr(Prefix);
+  VERD::RoundingMode RoundingMode = stringToVERD(RD);
+
+  if (RoundingMode != VERD::UNKNOWN) {
+    Name = Name.slice(0, Prefix);
+    // push 1st like `cvt.w.d.sx`
+    Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
+    SMLoc SuffixLoc =
+        SMLoc::getFromPointer(NameLoc.getPointer() + (RD.data() - Name.data()));
+    SMLoc SuffixEnd =
+        SMLoc::getFromPointer(NameLoc.getPointer() + (RD.end() - Name.data()));
+    // push $round if it has rounding mode
+    Operands->push_back(
+        VEOperand::CreateRDOp(RoundingMode, SuffixLoc, SuffixEnd));
+  } else {
+    Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
+  }
+  return Name;
+}
+
 // Split the mnemonic into ASM operand, conditional code and instruction
 // qualifier (half-word, byte).
 StringRef VEAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,
                                      OperandVector *Operands) {
   // Create the leading tokens for the mnemonic
   StringRef Mnemonic = Name;
 
   if (Name[0] == 'b') {
     // Match b?? or br??.
     size_t Start = 1;
     size_t Next = Name.find('.');
     // Adjust position of CondCode.
     if (Name.size() > 1 && Name[1] == 'r')
       Start = 2;
     // Check suffix.
     bool ICC = true;
     if (Next + 1 < Name.size() &&
         (Name[Next + 1] == 'd' || Name[Next + 1] == 's'))
       ICC = false;
     Mnemonic = parseCC(Name, Start, Next, ICC, true, NameLoc, Operands);
   } else if (Name.startswith("cmov.l.") || Name.startswith("cmov.w.") ||
              Name.startswith("cmov.d.") || Name.startswith("cmov.s.")) {
     bool ICC = Name[5] == 'l' || Name[5] == 'w';
     Mnemonic = parseCC(Name, 7, Name.size(), ICC, false, NameLoc, Operands);
+  } else if (Name.startswith("cvt.w.d.sx") || Name.startswith("cvt.w.d.zx") ||
+             Name.startswith("cvt.w.s.sx") || Name.startswith("cvt.w.s.zx")) {
+    Mnemonic = parseRD(Name, 10, NameLoc, Operands);
+  } else if (Name.startswith("cvt.l.d")) {
+    Mnemonic = parseRD(Name, 7, NameLoc, Operands);
   } else {
     Operands->push_back(VEOperand::CreateToken(Mnemonic, NameLoc));
   }
 
   return Mnemonic;
 }
 
 static void applyMnemonicAliases(StringRef &Mnemonic,

llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp

 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address,
                                  const void *Decoder);
 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
                                const void *Decoder);
 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address,
                                 const void *Decoder);
 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn,
                                     uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn,
+                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn,
                                           uint64_t Address,
                                           const void *Decoder);
 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn,
                                                 uint64_t Address,
                                                 const void *Decoder);
 
 #include "VEGenDisassemblerTables.inc"

 
 // Decode CC Operand field.
 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address,
                                     const void *Decoder) {
   MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
   return MCDisassembler::Success;
 }
 
+// Decode RD Operand field.
+static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address,
+                                    const void *Decoder) {
+  MI.addOperand(MCOperand::createImm(VEValToRD(cf)));
+  return MCDisassembler::Success;
+}
+
 // Decode branch condition instruction and CCOperand field in it.
 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn,
                                           uint64_t Address,
                                           const void *Decoder) {
   unsigned cf = fieldFromInstruction(insn, 48, 4);
   bool cy = fieldFromInstruction(insn, 47, 1);
   unsigned sy = fieldFromInstruction(insn, 40, 7);
 

llvm/lib/Target/VE/MCTargetDesc/VEMCCodeEmitter.cpp

public:
   /// operand requires relocation, record the relocation and return zero.
   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
   uint64_t getCCOpValue(const MCInst &MI, unsigned OpNo,
                         SmallVectorImpl<MCFixup> &Fixups,
                         const MCSubtargetInfo &STI) const;
+  uint64_t getRDOpValue(const MCInst &MI, unsigned OpNo,
+                        SmallVectorImpl<MCFixup> &Fixups,
+                        const MCSubtargetInfo &STI) const;
 
 private:
   FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
   void
   verifyInstructionPredicates(const MCInst &MI,
                               const FeatureBitset &AvailableFeatures) const;
 };
 
uint64_t VEMCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned OpNo,
                                        const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isImm())
     return VECondCodeToVal(
         static_cast<VECC::CondCode>(getMachineOpValue(MI, MO, Fixups, STI)));
   return 0;
 }
 
+uint64_t VEMCCodeEmitter::getRDOpValue(const MCInst &MI, unsigned OpNo,
+                                       SmallVectorImpl<MCFixup> &Fixups,
+                                       const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isImm())
+    return VERDToVal(static_cast<VERD::RoundingMode>(
+        getMachineOpValue(MI, MO, Fixups, STI)));
+  return 0;
+}
+
 #define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "VEGenMCCodeEmitter.inc"
 
 MCCodeEmitter *llvm::createVEMCCodeEmitter(const MCInstrInfo &MCII,
                                            const MCRegisterInfo &MRI,
                                            MCContext &Ctx) {
   return new VEMCCodeEmitter(MCII, Ctx);
 }

llvm/lib/Target/VE/VE.h

case VERD::RD_RN:
     return ".rn";
   case VERD::RD_RA:
     return ".ra";
   default:
     llvm_unreachable("Invalid branch predicate");
   }
 }
 
+inline static VERD::RoundingMode stringToVERD(StringRef S) {
+  return StringSwitch<VERD::RoundingMode>(S)
+      .Case("", VERD::RD_NONE)
+      .Case(".rz", VERD::RD_RZ)
+      .Case(".rp", VERD::RD_RP)
+      .Case(".rm", VERD::RD_RM)
+      .Case(".rn", VERD::RD_RN)
+      .Case(".ra", VERD::RD_RA)
+      .Default(VERD::UNKNOWN);
+}
+
+inline static unsigned VERDToVal(VERD::RoundingMode R) {
+  switch (R) {
+  case VERD::RD_NONE:
+  case VERD::RD_RZ:
+  case VERD::RD_RP:
+  case VERD::RD_RM:
+  case VERD::RD_RN:
+  case VERD::RD_RA:
+    return static_cast<unsigned>(R);
+  default:
+    break;
+  }
+  llvm_unreachable("Invalid branch predicates");
+}
+
+inline static VERD::RoundingMode VEValToRD(unsigned Val) {
+  switch (Val) {
+  case static_cast<unsigned>(VERD::RD_NONE):
+    return VERD::RD_NONE;
+  case static_cast<unsigned>(VERD::RD_RZ):
+    return VERD::RD_RZ;
+  case static_cast<unsigned>(VERD::RD_RP):
+    return VERD::RD_RP;
+  case static_cast<unsigned>(VERD::RD_RM):
+    return VERD::RD_RM;
+  case static_cast<unsigned>(VERD::RD_RN):
+    return VERD::RD_RN;
+  case static_cast<unsigned>(VERD::RD_RA):
+    return VERD::RD_RA;
+  default:
+    break;
+  }
+  llvm_unreachable("Invalid branch predicates");
+}
+
 // MImm - Special immediate value of sequential bit stream of 0 or 1.
 //   See VEInstrInfo.td for details.
 inline static bool isMImmVal(uint64_t Val) {
   if (Val == 0) {
     // (0)1 is 0
     return true;
   }
   if (isMask_64(Val)) {

llvm/lib/Target/VE/VEInstrInfo.td

 def CCOp : Operand<i32>, ImmLeaf<i32, [{
     return Imm >= 0 && Imm < 22; }], CCOP> {
   let PrintMethod = "printCCOperand";
   let DecoderMethod = "DecodeCCOperand";
   let EncoderMethod = "getCCOpValue";
   let ParserMatchClass = CCOpAsmOperand;
 }
 
-// Operand for printing out a rounding mode code.
+// Operand for a rounding mode code.
+def RDOpAsmOperand : AsmOperandClass {
+  let Name = "RDOp";
+}
 def RDOp : Operand<i32> {
   let PrintMethod = "printRDOperand";
+  let DecoderMethod = "DecodeRDOperand";
+  let EncoderMethod = "getRDOpValue";
+  let ParserMatchClass = RDOpAsmOperand;
 }
 
 def VEhi    : SDNode<"VEISD::Hi", SDTIntUnaryOp>;
 def VElo    : SDNode<"VEISD::Lo", SDTIntUnaryOp>;
 
 //  These are target-independent nodes, but have target-specific formats.
 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64>,
                                           SDTCisVT<1, i64> ]>;

 let cx = 1 in
 defm CVTSW : CVTm<"cvt.s.w", 0x5E, F32, f32, I32, i32, sint_to_fp>;
 
 // Section 8.7.14 - FLTX (Convert to Floating Point)
 defm CVTDL : CVTm<"cvt.d.l", 0x5F, I64, f64, I64, i64, sint_to_fp>;
 
 // Section 8.7.15 - CVS (Convert to Single-format)
 defm CVTSD : CVTm<"cvt.s.d", 0x1F, F32, f32, I64, f64, fpround>;
+let cx = 1 in
+defm CVTSQ : CVTm<"cvt.s.q", 0x1F, F32, f32, F128, f128>;
 
 // Section 8.7.16 - CVD (Convert to Double-format)
 defm CVTDS : CVTm<"cvt.d.s", 0x0F, I64, f64, F32, f32, fpextend>;
+let cx = 1 in
+defm CVTDQ : CVTm<"cvt.d.q", 0x0F, I64, f64, F128, f128>;
 
 // Section 8.7.17 - CVQ (Convert to Single-format)
+defm CVTQD : CVTm<"cvt.q.d", 0x2D, F128, f128, I64, f64>;
+let cx = 1 in
+defm CVTQS : CVTm<"cvt.q.s", 0x2D, F128, f128, F32, f32>;
 
 //-----------------------------------------------------------------------------
 // Section 8.8 - Branch instructions
 //-----------------------------------------------------------------------------
 
 // Section 8.8.1 - BC (Branch on Codition)
 defm BCFL : BCm<"b${cond}.l", "b.l", "baf.l", 0x19, I64, simm7>;
 

llvm/test/MC/VE/CVTDL.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.d.l %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x5f]
+cvt.d.l %s11, %s12
+
+# CHECK-INST: cvt.d.l %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x0b,0x5f]
+cvt.d.l %s11, 63
+
+# CHECK-INST: cvt.d.l %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x0b,0x5f]
+cvt.d.l %s11, -64
+
+# CHECK-INST: cvt.d.l %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x0b,0x5f]
+cvt.d.l %s11, -1

llvm/test/MC/VE/CVTDQ.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.d.q %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x8b,0x0f]
+cvt.d.q %s11, %s12
+
+# CHECK-INST: cvt.d.q %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x8b,0x0f]
+cvt.d.q %s11, 63
+
+# CHECK-INST: cvt.d.q %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x8b,0x0f]
+cvt.d.q %s11, -64
+
+# CHECK-INST: cvt.d.q %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x8b,0x0f]
+cvt.d.q %s11, -1

llvm/test/MC/VE/CVTDS.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.d.s %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x0f]
+cvt.d.s %s11, %s12
+
+# CHECK-INST: cvt.d.s %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x0b,0x0f]
+cvt.d.s %s11, 63
+
+# CHECK-INST: cvt.d.s %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x0b,0x0f]
+cvt.d.s %s11, -64
+
+# CHECK-INST: cvt.d.s %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x0b,0x0f]
+cvt.d.s %s11, -1

llvm/test/MC/VE/CVTDW.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.d.w %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x5e]
+cvt.d.w %s11, %s12
+
+# CHECK-INST: cvt.d.w %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x0b,0x5e]
+cvt.d.w %s11, 63
+
+# CHECK-INST: cvt.d.w %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x0b,0x5e]
+cvt.d.w %s11, -64
+
+# CHECK-INST: cvt.d.w %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x0b,0x5e]
+cvt.d.w %s11, -1

llvm/test/MC/VE/CVTLD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.l.d %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x4f]
+cvt.l.d %s11, %s12
+
+# CHECK-INST: cvt.l.d.rz %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x08,0x3f,0x0b,0x4f]
+cvt.l.d.rz %s11, 63
+
+# CHECK-INST: cvt.l.d.rp %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x09,0x40,0x0b,0x4f]
+cvt.l.d.rp %s11, -64
+
+# CHECK-INST: cvt.l.d.rm %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0a,0x7f,0x0b,0x4f]
+cvt.l.d.rm %s11, -1
+
+# CHECK-INST: cvt.l.d.rn %s11, 7
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0b,0x07,0x0b,0x4f]
+cvt.l.d.rn %s11, 7
+
+# CHECK-INST: cvt.l.d.ra %s11, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0c,0xbf,0x0b,0x4f]
+cvt.l.d.ra %s11, %s63

llvm/test/MC/VE/CVTQD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.q.d %s18, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x12,0x2d]
+cvt.q.d %s18, %s12
+
+# CHECK-INST: cvt.q.d %s18, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x12,0x2d]
+cvt.q.d %s18, 63
+
+# CHECK-INST: cvt.q.d %s18, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x12,0x2d]
+cvt.q.d %s18, -64
+
+# CHECK-INST: cvt.q.d %s18, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x12,0x2d]
+cvt.q.d %s18, -1

llvm/test/MC/VE/CVTQS.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.q.s %s18, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x92,0x2d]
+cvt.q.s %s18, %s12
+
+# CHECK-INST: cvt.q.s %s18, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x92,0x2d]
+cvt.q.s %s18, 63
+
+# CHECK-INST: cvt.q.s %s18, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x92,0x2d]
+cvt.q.s %s18, -64
+
+# CHECK-INST: cvt.q.s %s18, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x92,0x2d]
+cvt.q.s %s18, -1

llvm/test/MC/VE/CVTSD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.s.d %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x1f]
+cvt.s.d %s11, %s12
+
+# CHECK-INST: cvt.s.d %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x0b,0x1f]
+cvt.s.d %s11, 63
+
+# CHECK-INST: cvt.s.d %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x0b,0x1f]
+cvt.s.d %s11, -64
+
+# CHECK-INST: cvt.s.d %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x0b,0x1f]
+cvt.s.d %s11, -1

llvm/test/MC/VE/CVTSQ.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.s.q %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x8b,0x1f]
+cvt.s.q %s11, %s12
+
+# CHECK-INST: cvt.s.q %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x8b,0x1f]
+cvt.s.q %s11, 63
+
+# CHECK-INST: cvt.s.q %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x8b,0x1f]
+cvt.s.q %s11, -64
+
+# CHECK-INST: cvt.s.q %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x8b,0x1f]
+cvt.s.q %s11, -1

llvm/test/MC/VE/CVTSW.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.s.w %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x8b,0x5e]
+cvt.s.w %s11, %s12
+
+# CHECK-INST: cvt.s.w %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x8b,0x5e]
+cvt.s.w %s11, 63
+
+# CHECK-INST: cvt.s.w %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x8b,0x5e]
+cvt.s.w %s11, -64
+
+# CHECK-INST: cvt.s.w %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x8b,0x5e]
+cvt.s.w %s11, -1

llvm/test/MC/VE/CVTWD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.w.d.sx %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x4e]
+cvt.w.d.sx %s11, %s12
+
+# CHECK-INST: cvt.w.d.sx.rz %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x08,0x3f,0x0b,0x4e]
+cvt.w.d.sx.rz %s11, 63
+
+# CHECK-INST: cvt.w.d.sx.rp %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x09,0x40,0x0b,0x4e]
+cvt.w.d.sx.rp %s11, -64
+
+# CHECK-INST: cvt.w.d.sx.rm %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0a,0x7f,0x0b,0x4e]
+cvt.w.d.sx.rm %s11, -1
+
+# CHECK-INST: cvt.w.d.sx.rn %s11, 7
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0b,0x07,0x0b,0x4e]
+cvt.w.d.sx.rn %s11, 7
+
+# CHECK-INST: cvt.w.d.sx.ra %s11, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0c,0xbf,0x0b,0x4e]
+cvt.w.d.sx.ra %s11, %s63
+
+# CHECK-INST: cvt.w.d.zx %s11, %s12
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x00,0x8c,0x0b,0x4e]
+cvt.w.d.zx %s11, %s12
+
+# CHECK-INST: cvt.w.d.zx.rz %s11, 63
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x08,0x3f,0x0b,0x4e]
+cvt.w.d.zx.rz %s11, 63
+
+# CHECK-INST: cvt.w.d.zx.rp %s11, -64
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x09,0x40,0x0b,0x4e]
+cvt.w.d.zx.rp %s11, -64
+
+# CHECK-INST: cvt.w.d.zx.rm %s11, -1
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x0a,0x7f,0x0b,0x4e]
+cvt.w.d.zx.rm %s11, -1
+
+# CHECK-INST: cvt.w.d.zx.rn %s11, 7
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x0b,0x07,0x0b,0x4e]
+cvt.w.d.zx.rn %s11, 7
+
+# CHECK-INST: cvt.w.d.zx.ra %s11, %s63
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x0c,0xbf,0x0b,0x4e]
+cvt.w.d.zx.ra %s11, %s63

llvm/test/MC/VE/CVTWS.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cvt.w.s.sx %s11, %s12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x8b,0x4e]
+cvt.w.s.sx %s11, %s12
+
+# CHECK-INST: cvt.w.s.sx.rz %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x08,0x3f,0x8b,0x4e]
+cvt.w.s.sx.rz %s11, 63
+
+# CHECK-INST: cvt.w.s.sx.rp %s11, -64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x09,0x40,0x8b,0x4e]
+cvt.w.s.sx.rp %s11, -64
+
+# CHECK-INST: cvt.w.s.sx.rm %s11, -1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0a,0x7f,0x8b,0x4e]
+cvt.w.s.sx.rm %s11, -1
+
+# CHECK-INST: cvt.w.s.sx.rn %s11, 7
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0b,0x07,0x8b,0x4e]
+cvt.w.s.sx.rn %s11, 7
+
+# CHECK-INST: cvt.w.s.sx.ra %s11, %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0c,0xbf,0x8b,0x4e]
+cvt.w.s.sx.ra %s11, %s63
+
+# CHECK-INST: cvt.w.s.zx %s11, %s12
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x00,0x8c,0x8b,0x4e]
+cvt.w.s.zx %s11, %s12
+
+# CHECK-INST: cvt.w.s.zx.rz %s11, 63
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x08,0x3f,0x8b,0x4e]
+cvt.w.s.zx.rz %s11, 63
+
+# CHECK-INST: cvt.w.s.zx.rp %s11, -64
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x09,0x40,0x8b,0x4e]
+cvt.w.s.zx.rp %s11, -64
+
+# CHECK-INST: cvt.w.s.zx.rm %s11, -1
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x0a,0x7f,0x8b,0x4e]
+cvt.w.s.zx.rm %s11, -1
+
+# CHECK-INST: cvt.w.s.zx.rn %s11, 7
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x0b,0x07,0x8b,0x4e]
+cvt.w.s.zx.rn %s11, 7
+
+# CHECK-INST: cvt.w.s.zx.ra %s11, %s63
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x0c,0xbf,0x8b,0x4e]
+cvt.w.s.zx.ra %s11, %s63