[VE] Support shift operation instructions in MC layer

[kaz7]

Summary

Add regression tests of asmparser, mccodeemitter, and disassembler for
shift operation instructions. Also change asmparser to support UImm7
operand. And, add new SLD/SRD/SLA isntructions also.

[kaz7]

Change the order of predicates to make it identical to the inner develop
branch..

[simoll]

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

199

Consider using const auto* next time.

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

public:
   }
   bool isMEMrri() const { return Kind == k_MemoryRegRegImm; }
   bool isMEMrii() const { return Kind == k_MemoryRegImmImm; }
   bool isMEMzri() const { return Kind == k_MemoryZeroRegImm; }
   bool isMEMzii() const { return Kind == k_MemoryZeroImmImm; }
   bool isMEMri() const { return Kind == k_MemoryRegImm; }
   bool isMEMzi() const { return Kind == k_MemoryZeroImm; }
   bool isCCOp() const { return Kind == k_CCOp; }
+  bool isUImm7() {
+    if (!isImm())
+      return false;
+
+    // Constant case
+    if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+      int64_t Value = ConstExpr->getValue();
+      return isUInt<7>(Value);
+    }
+    return false;
+  }
   bool isSImm7() {
     if (!isImm())
       return false;
 
     // Constant case
     if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
       int64_t Value = ConstExpr->getValue();
       return isInt<7>(Value);
public:
   }
 
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCExpr *Expr = getImm();
     addExpr(Inst, Expr);
   }
 
+  void addUImm7Operands(MCInst &Inst, unsigned N) const {
+    addImmOperands(Inst, N);
+  }
+
   void addSImm7Operands(MCInst &Inst, unsigned N) const {
     addImmOperands(Inst, N);
   }
 
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     // Add as immediate when possible.  Null MCExpr = 0.
     if (!Expr)
       Inst.addOperand(MCOperand::createImm(0));

llvm/lib/Target/VE/VEInstrInfo.td

 //     bit 5-0: Represents the m (0-63).
 // Use `!add(m, 64)` to generates an immediate value in pattern matchings.
 //
 // The floating point immediate value is not something like compacted value.
 // It is simple integer representation, so it works rarely.
 //     e.g. 0.0 (0x00000000) or -2.0 (0xC0000000=(2)1).
 //===----------------------------------------------------------------------===//
 
+def ULO7 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getZExtValue() & 0x7f,
+                                   SDLoc(N), MVT::i32);
+}]>;
 def LO7 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
                                    SDLoc(N), MVT::i32);
 }]>;
 def MIMM : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(convMImmVal(getImmVal(N)),
                                    SDLoc(N), MVT::i32);
 }]>;

 def uimm1 : Operand<i32>, PatLeaf<(imm), [{
     return isUInt<1>(N->getZExtValue()); }]>;
 
 // uimm6 - Generic immediate value.
 def uimm6 : Operand<i32>, PatLeaf<(imm), [{
     return isUInt<6>(N->getZExtValue()); }]>;
 
 // uimm7 - Generic immediate value.
+def UImm7AsmOperand : AsmOperandClass {
+  let Name = "UImm7";
+}
 def uimm7 : Operand<i32>, PatLeaf<(imm), [{
-    return isUInt<7>(N->getZExtValue()); }]>;
+    return isUInt<7>(N->getZExtValue()); }], ULO7> {
+  let ParserMatchClass = UImm7AsmOperand;
+}
 
 // simm7 - Generic immediate value.
 def SImm7AsmOperand : AsmOperandClass {
   let Name = "SImm7";
 }
 def simm7 : Operand<i32>, PatLeaf<(imm), [{
     return isInt<7>(N->getSExtValue()); }], LO7> {
   let ParserMatchClass = SImm7AsmOperand;
def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm7:$sy),
               !strconcat(opcStr, " $sx, $sz, $sy"),
               [(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm7:$sy)))]>;
   let cy = 0, cz = 0 in
   def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm7:$sy),
               !strconcat(opcStr, " $sx, $sz, $sy"),
               [(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>;
 }
 
+// Special RR multiclass for 128 bits shift left instruction.
+//   e.g. SLD
+let Constraints = "$hi = $sx", DisableEncoding = "$hi", hasSideEffects = 0 in
+multiclass RRILDm<string opcStr, bits<8>opc,
+                  RegisterClass RC, ValueType Ty,
+                  SDPatternOperator OpNode = null_frag> {
+  def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+  let cz = 0 in
+  def rmr : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, I32:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+  let cy = 0 in
+  def rri : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, uimm7:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+  let cy = 0, cz = 0 in
+  def rmi : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, uimm7:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+}
+
+// Special RR multiclass for 128 bits shift right instruction.
+//   e.g. SRD
+let Constraints = "$low = $sx", DisableEncoding = "$low", hasSideEffects = 0 in
+multiclass RRIRDm<string opcStr, bits<8>opc,
+                  RegisterClass RC, ValueType Ty,
+                  SDPatternOperator OpNode = null_frag> {
+  def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+  let cz = 0 in
+  def mrr : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, I32:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+  let cy = 0 in
+  def rri : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, uimm7:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+  let cy = 0, cz = 0 in
+  def mri : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, uimm7:$sy),
+              !strconcat(opcStr, " $sx, $sz, $sy")>;
+}
+
 // Generic RR multiclass with an argument.
 //   e.g. LDZ, PCNT, and  BRV
 let cy = 0, sy = 0, hasSideEffects = 0 in
 multiclass RRI1m<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
                  SDPatternOperator OpNode = null_frag> {
   def r : RR<opc, (outs RC:$sx), (ins RC:$sz), !strconcat(opcStr, " $sx, $sz"),
              [(set Ty:$sx, (OpNode Ty:$sz))]>;
   let cz = 0 in

 //-----------------------------------------------------------------------------
 // Section 8.6 - Shift Operation Instructions
 //-----------------------------------------------------------------------------
 
 // Section 8.6.1 - SLL (Shift Left Logical)
 defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
 
 // Section 8.6.2 - SLD (Shift Left Double)
+defm SLD : RRILDm<"sld", 0x64, I64, i64>;
 
 // Section 8.6.3 - SRL (Shift Right Logical)
 defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
 
 // Section 8.6.4 - SRD (Shift Right Double)
+defm SRD : RRIRDm<"srd", 0x74, I64, i64>;
 
 // Section 8.6.5 - SLA (Shift Left Arithmetic)
 defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
 let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
 
 // Section 8.6.6 - SLAX (Shift Left Arithmetic)
+defm SLAL : RRIm<"sla.l", 0x57, I64, i64>;
 
 // Section 8.6.7 - SRA (Shift Right Arithmetic)
 defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;
 let cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>;
 
 // Section 8.6.8 - SRAX (Shift Right Arithmetic)
 defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>;
 

llvm/test/MC/VE/SLA.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sla.w.sx %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x66]
+sla.w.sx %s11, %s11, %s11
+
+# CHECK-INST: sla.w.zx %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x8b,0x66]
+sla.w.zx %s11, %s11, 63
+
+# CHECK-INST: sla.l %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x57]
+sla.l %s11, %s11, 127
+
+# CHECK-INST: sla.w.sx %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x66]
+sla.w.sx %s11, %s11, 64
+
+# CHECK-INST: sla.w.zx %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x8b,0x66]
+sla.w.zx %s11, (32)1, 64
+
+# CHECK-INST: sla.l %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x57]
+sla.l %s11, (32)0, 63

llvm/test/MC/VE/SLD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sld %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x64]
+sld %s11, %s11, %s11
+
+# CHECK-INST: sld %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x64]
+sld %s11, %s11, 63
+
+# CHECK-INST: sld %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x64]
+sld %s11, %s11, 127
+
+# CHECK-INST: sld %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x64]
+sld %s11, %s11, 64
+
+# CHECK-INST: sld %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x64]
+sld %s11, (32)1, 64
+
+# CHECK-INST: sld %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x64]
+sld %s11, (32)0, 63

llvm/test/MC/VE/SLL.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sll %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x65]
+sll %s11, %s11, %s11
+
+# CHECK-INST: sll %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x65]
+sll %s11, %s11, 63
+
+# CHECK-INST: sll %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x65]
+sll %s11, %s11, 127
+
+# CHECK-INST: sll %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x65]
+sll %s11, %s11, 64
+
+# CHECK-INST: sll %s11, (32)1, 35
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x23,0x0b,0x65]
+sll %s11, (32)1, 35
+
+# CHECK-INST: sll %s11, (32)0, 23
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x17,0x0b,0x65]
+sll %s11, (32)0, 23

llvm/test/MC/VE/SRA.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sra.w.sx %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x76]
+sra.w.sx %s11, %s11, %s11
+
+# CHECK-INST: sra.w.zx %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x8b,0x76]
+sra.w.zx %s11, %s11, 63
+
+# CHECK-INST: sra.l %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x77]
+sra.l %s11, %s11, 127
+
+# CHECK-INST: sra.w.sx %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x76]
+sra.w.sx %s11, %s11, 64
+
+# CHECK-INST: sra.w.zx %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x8b,0x76]
+sra.w.zx %s11, (32)1, 64
+
+# CHECK-INST: sra.l %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x77]
+sra.l %s11, (32)0, 63

llvm/test/MC/VE/SRD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: srd %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x74]
+srd %s11, %s11, %s11
+
+# CHECK-INST: srd %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x74]
+srd %s11, %s11, 63
+
+# CHECK-INST: srd %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x74]
+srd %s11, %s11, 127
+
+# CHECK-INST: srd %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x74]
+srd %s11, %s11, 64
+
+# CHECK-INST: srd %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x74]
+srd %s11, (32)1, 64
+
+# CHECK-INST: srd %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x74]
+srd %s11, (32)0, 63

llvm/test/MC/VE/SRL.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: srl %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x75]
+srl %s11, %s11, %s11
+
+# CHECK-INST: srl %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x75]
+srl %s11, %s11, 63
+
+# CHECK-INST: srl %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x75]
+srl %s11, %s11, 127
+
+# CHECK-INST: srl %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x75]
+srl %s11, %s11, 64
+
+# CHECK-INST: srl %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x75]
+srl %s11, (32)1, 64
+
+# CHECK-INST: srl %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x75]
+srl %s11, (32)0, 63