[X86] Fold undef elts to 0 in getTargetVShiftByConstNode.

[craig.topper]

Summary

Similar to D81212.

[RKSimon]

LGTM

llvm/lib/Target/X86/X86ISelLowering.cpp

if (ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
     unsigned NumElts = SrcOp->getNumOperands();
 
     switch (Opc) {
     default: llvm_unreachable("Unknown opcode!");
     case X86ISD::VSHLI:
       for (unsigned i = 0; i != NumElts; ++i) {
         SDValue CurrentOp = SrcOp->getOperand(i);
         if (CurrentOp->isUndef()) {
-          Elts.push_back(CurrentOp);
+          // Must produce 0s in the correct bits.
+          Elts.push_back(DAG.getConstant(0, dl, ElementType));
           continue;
         }
         auto *ND = cast<ConstantSDNode>(CurrentOp);
         const APInt &C = ND->getAPIntValue();
         Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
       }
       break;
     case X86ISD::VSRLI:
       for (unsigned i = 0; i != NumElts; ++i) {
         SDValue CurrentOp = SrcOp->getOperand(i);
         if (CurrentOp->isUndef()) {
-          Elts.push_back(CurrentOp);
+          // Must produce 0s in the correct bits.
+          Elts.push_back(DAG.getConstant(0, dl, ElementType));
           continue;
         }
         auto *ND = cast<ConstantSDNode>(CurrentOp);
         const APInt &C = ND->getAPIntValue();
         Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
       }
       break;
     case X86ISD::VSRAI:
       for (unsigned i = 0; i != NumElts; ++i) {
         SDValue CurrentOp = SrcOp->getOperand(i);
         if (CurrentOp->isUndef()) {
-          Elts.push_back(CurrentOp);
+          // All shifted in bits must be the same so use 0.
+          Elts.push_back(DAG.getConstant(0, dl, ElementType));
           continue;
         }
         auto *ND = cast<ConstantSDNode>(CurrentOp);
         const APInt &C = ND->getAPIntValue();
         Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
       }
       break;
     }

llvm/test/CodeGen/X86/vec_shift5.ll

 ; X64-NEXT:    retq
   %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 8, i64 16>, i32 3)
   ret <2 x i64> %1
 }
 
 define <8 x i16> @test9() {
 ; X32-LABEL: test9:
 ; X32:       # %bb.0:
-; X32-NEXT:    movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
+; X32-NEXT:    movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test9:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
 ; X64-NEXT:    retq
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
   ret <8 x i16> %1
 }
 
 define <4 x i32> @test10() {
 ; X32-LABEL: test10:
 ; X32:       # %bb.0:
-; X32-NEXT:    movaps {{.*#+}} xmm0 = <u,1,u,4>
+; X32-NEXT:    movaps {{.*#+}} xmm0 = [0,1,0,4]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test10:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <u,1,u,4>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [0,1,0,4]
 ; X64-NEXT:    retq
   %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
   ret <4 x i32> %1
 }
 
 define <2 x i64> @test11() {
 ; X32-LABEL: test11:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movaps {{.*#+}} xmm0 = [0,0,3,0]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test11:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <u,3>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0]
 ; X64-NEXT:    retq
   %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
   ret <2 x i64> %1
 }
 
 define <8 x i16> @test12() {
 ; X32-LABEL: test12:
 ; X32:       # %bb.0:
-; X32-NEXT:    movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
+; X32-NEXT:    movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test12:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
 ; X64-NEXT:    retq
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
   ret <8 x i16> %1
 }
 
 define <4 x i32> @test13() {
 ; X32-LABEL: test13:
 ; X32:       # %bb.0:
-; X32-NEXT:    movaps {{.*#+}} xmm0 = <u,1,u,4>
+; X32-NEXT:    movaps {{.*#+}} xmm0 = [0,1,0,4]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test13:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <u,1,u,4>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [0,1,0,4]
 ; X64-NEXT:    retq
   %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
   ret <4 x i32> %1
 }
 
 define <8 x i16> @test14() {
 ; X32-LABEL: test14:
 ; X32:       # %bb.0:
-; X32-NEXT:    movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
+; X32-NEXT:    movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test14:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
 ; X64-NEXT:    retq
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
   ret <8 x i16> %1
 }
 
 define <4 x i32> @test15() {
 ; X32-LABEL: test15:
 ; X32:       # %bb.0:
-; X32-NEXT:    movaps {{.*#+}} xmm0 = <u,64,u,256>
+; X32-NEXT:    movaps {{.*#+}} xmm0 = [0,64,0,256]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test15:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <u,64,u,256>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [0,64,0,256]
 ; X64-NEXT:    retq
   %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
   ret <4 x i32> %1
 }
 
 define <2 x i64> @test16() {
 ; X32-LABEL: test16:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movaps {{.*#+}} xmm0 = [0,0,248,0]
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test16:
 ; X64:       # %bb.0:
-; X64-NEXT:    movaps {{.*#+}} xmm0 = <u,248>
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,248,0,0,0,0,0,0,0]
 ; X64-NEXT:    retq
   %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
   ret <2 x i64> %1
 }
 
 declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
 declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
 declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
 declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32)
 declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32)
 declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32)