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Differential D80539

[X86] Report error for invalid register number.
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Authored by LuoYuanke on May 26 2020, 1:11 AM.
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Change-Id: I2587106ada854a95098698f0d3b1c7d8e5f665f8

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LuoYuanke created this revision.May 26 2020, 1:11 AM
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Harbormaster completed remote builds in B57845: Diff 266116.May 26 2020, 3:44 AM

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
MCTargetDesc/
15 lines

Diff 266116

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 1,004 Lines • ▼ Show 20 Lines if (HasVEX_4V) {
unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
VEX_4V = ~VRegEnc & 0xf; VEX_4V = ~VRegEnc & 0xf;
EVEX_V2 = ~(VRegEnc >> 4) & 1; EVEX_V2 = ~(VRegEnc >> 4) & 1;
} }
RegEnc = getX86RegEncoding(MI, CurOp++); RegEnc = getX86RegEncoding(MI, CurOp++);
VEX_B = ~(RegEnc >> 3) & 1; VEX_B = ~(RegEnc >> 3) & 1;
VEX_X = ~(RegEnc >> 4) & 1; VEX_X = ~(RegEnc >> 4) & 1;
if (Encoding == X86II::VEX && !VEX_X)
report_fatal_error("R/M register number exceed 16 in VEX encoding!");
if (EVEX_b) { if (EVEX_b) {
if (HasEVEX_RC) { if (HasEVEX_RC) {
unsigned RcOperand = NumOps - 1; unsigned RcOperand = NumOps - 1;
assert(RcOperand >= CurOp); assert(RcOperand >= CurOp);
EVEX_rc = MI.getOperand(RcOperand).getImm(); EVEX_rc = MI.getOperand(RcOperand).getImm();
assert(EVEX_rc <= 3 && "Invalid rounding control!"); assert(EVEX_rc <= 3 && "Invalid rounding control!");
} }
Show All 22 Lines case X86II::MRMSrcRegOp4: {
VEX_4V = ~VRegEnc & 0xf; VEX_4V = ~VRegEnc & 0xf;
// Skip second register source (encoded in Imm[7:4]) // Skip second register source (encoded in Imm[7:4])
++CurOp; ++CurOp;
RegEnc = getX86RegEncoding(MI, CurOp++); RegEnc = getX86RegEncoding(MI, CurOp++);
VEX_B = ~(RegEnc >> 3) & 1; VEX_B = ~(RegEnc >> 3) & 1;
VEX_X = ~(RegEnc >> 4) & 1; VEX_X = ~(RegEnc >> 4) & 1;
if (Encoding == X86II::VEX && !VEX_X)
report_fatal_error("R/M register number exceed 16 in VEX encoding!");
break; break;
} }
case X86II::MRMDestReg: { case X86II::MRMDestReg: {
// MRMDestReg instructions forms: // MRMDestReg instructions forms:
// dst(ModR/M), src(ModR/M) // dst(ModR/M), src(ModR/M)
// dst(ModR/M), src(ModR/M), imm8 // dst(ModR/M), src(ModR/M), imm8
// dst(ModR/M), src1(VEX_4V), src2(ModR/M) // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
unsigned RegEnc = getX86RegEncoding(MI, CurOp++); unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
VEX_B = ~(RegEnc >> 3) & 1; VEX_B = ~(RegEnc >> 3) & 1;
VEX_X = ~(RegEnc >> 4) & 1; VEX_X = ~(RegEnc >> 4) & 1;
if (Encoding == X86II::VEX && !VEX_X)
report_fatal_error("R/M register number exceed 16 in VEX encoding!");
if (HasEVEX_K) if (HasEVEX_K)
EVEX_aaa = getX86RegEncoding(MI, CurOp++); EVEX_aaa = getX86RegEncoding(MI, CurOp++);
if (HasVEX_4V) { if (HasVEX_4V) {
unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
VEX_4V = ~VRegEnc & 0xf; VEX_4V = ~VRegEnc & 0xf;
EVEX_V2 = ~(VRegEnc >> 4) & 1; EVEX_V2 = ~(VRegEnc >> 4) & 1;
Show All 22 Lines if (HasVEX_4V) {
EVEX_V2 = ~(VRegEnc >> 4) & 1; EVEX_V2 = ~(VRegEnc >> 4) & 1;
} }
if (HasEVEX_K) if (HasEVEX_K)
EVEX_aaa = getX86RegEncoding(MI, CurOp++); EVEX_aaa = getX86RegEncoding(MI, CurOp++);
unsigned RegEnc = getX86RegEncoding(MI, CurOp++); unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
VEX_B = ~(RegEnc >> 3) & 1; VEX_B = ~(RegEnc >> 3) & 1;
VEX_X = ~(RegEnc >> 4) & 1; VEX_X = ~(RegEnc >> 4) & 1;
if (Encoding == X86II::VEX && !VEX_X)
report_fatal_error("R/M register number exceed 16 in VEX encoding!");
break; break;
} }
} }
if (Encoding == X86II::VEX) {
if (!EVEX_R2)
report_fatal_error("R/M.reg register number exceed 16 in VEX encoding!");
if (!EVEX_V2)
report_fatal_error("V register number exceed 16 in VEX encoding!");
}
if (Encoding == X86II::VEX || Encoding == X86II::XOP) { if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
// VEX opcode prefix can have 2 or 3 bytes // VEX opcode prefix can have 2 or 3 bytes
// //
// 3 bytes: // 3 bytes:
// +-----+ +--------------+ +-------------------+ // +-----+ +--------------+ +-------------------+
// | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
// +-----+ +--------------+ +-------------------+ // +-----+ +--------------+ +-------------------+
// 2 bytes: // 2 bytes:
▲ Show 20 Lines • Show All 650 Lines • Show Last 20 Lines