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AMDGPU: Implement isConstantPhysReg
ClosedPublic

Authored by arsenm on May 22 2020, 5:34 AM.

Reviewers

rampitec

Summary

I don't think any of these registers are used in contexts where this
would do anything yet.

LGTM

This revision is now accepted and ready to land.May 22 2020, 10:22 AM

Path

Size

llvm/

lib/

Target/

AMDGPU/

2 lines

13 lines

Show First 20 Lines • Show All 204 Lines • ▼ Show 20 Lines	public:
const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,		const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
Register Reg) const;		Register Reg) const;
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;		bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;		bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const {		bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const {
return isVGPR(MRI, Reg) \|\| isAGPR(MRI, Reg);		return isVGPR(MRI, Reg) \|\| isAGPR(MRI, Reg);
}		}

		bool isConstantPhysReg(MCRegister PhysReg) const override;

bool isDivergentRegClass(const TargetRegisterClass *RC) const override {		bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
return !isSGPRClass(RC);		return !isSGPRClass(RC);
}		}

ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,		ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
unsigned EltSize) const;		unsigned EltSize) const;

bool shouldCoalesce(MachineInstr *MI,		bool shouldCoalesce(MachineInstr *MI,
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

Show First 20 Lines • Show All 1,843 Lines • ▼ Show 20 Lines	MCPhysReg SIRegisterInfo::get32BitRegister(MCPhysReg Reg) const {
}		}
if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16,		if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16,
&AMDGPU::VGPR_32RegClass)) {		&AMDGPU::VGPR_32RegClass)) {
return Super;		return Super;
}		}

return AMDGPU::NoRegister;		return AMDGPU::NoRegister;
}		}

		bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
		switch (PhysReg) {
		case AMDGPU::SGPR_NULL:
		case AMDGPU::SRC_SHARED_BASE:
		case AMDGPU::SRC_PRIVATE_BASE:
		case AMDGPU::SRC_SHARED_LIMIT:
		case AMDGPU::SRC_PRIVATE_LIMIT:
		return true;
		default:
		return false;
		}
		}