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Differential D80256

[AMDGPU] Process V_MOV_B32_indirect in SET_GPR_IDX optimization
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Authored by rampitec on May 19 2020, 3:59 PM.

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arsenm
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rG677929e35218: [AMDGPU] Process V_MOV_B32_indirect in SET_GPR_IDX optimization

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rampitec created this revision.May 19 2020, 3:59 PM
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arsenm accepted this revision.May 19 2020, 6:50 PM
This revision is now accepted and ready to land.May 19 2020, 6:50 PM
Closed by commit rG677929e35218: [AMDGPU] Process V_MOV_B32_indirect in SET_GPR_IDX optimization (authored by rampitec). · Explain WhyMay 19 2020, 9:58 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
8 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
10 lines
20 lines

Diff 265134

llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp

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return false; return false;
if (IdxReg && I->modifiesRegister(IdxReg, TRI)) if (IdxReg && I->modifiesRegister(IdxReg, TRI))
return false; return false;
if (llvm::any_of(I->operands(), if (llvm::any_of(I->operands(),
[&MRI, this](const MachineOperand &MO) { [&MRI, this](const MachineOperand &MO) {
return MO.isReg() && return MO.isReg() &&
TRI->isVectorRegister(MRI, MO.getReg()); TRI->isVectorRegister(MRI, MO.getReg());
})) { })) {
// The only exception allowed here is another indirect V_MOV_B32_e32 // The only exception allowed here is another indirect vector move
// with the same mode. // with the same mode.
if (!IdxOn || I->getOpcode() != AMDGPU::V_MOV_B32_e32 || if (!IdxOn ||
!I->hasRegisterImplicitUseOperand(AMDGPU::M0)) !((I->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
I->hasRegisterImplicitUseOperand(AMDGPU::M0)) ||
I->getOpcode() == AMDGPU::V_MOV_B32_indirect))
return false; return false;
} }
} }
} }
MI.eraseFromParent(); MI.eraseFromParent();
for (MachineInstr *RI : ToRemove) for (MachineInstr *RI : ToRemove)
RI->eraseFromParent(); RI->eraseFromParent();
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llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

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; GPRIDX-NEXT: v_mov_b32_e32 v6, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s4
; GPRIDX-NEXT: v_mov_b32_e32 v5, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s3
; GPRIDX-NEXT: v_mov_b32_e32 v4, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s0
; GPRIDX-NEXT: s_lshl_b32 s0, s18, 1 ; GPRIDX-NEXT: s_lshl_b32 s0, s18, 1
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v2, v0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, v0
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v3, v1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, v1
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[6:9], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[6:9], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[10:13], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[10:13], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[14:17], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[14:17], off
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
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} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_s_s: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_lshl_b32 s0, s4, 1 ; GPRIDX-NEXT: s_lshl_b32 s0, s4, 1
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v0, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s2
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v1, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s3
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
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} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double %val, i32 inreg %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1 ; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v16 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v16
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v1, v17 ; GPRIDX-NEXT: v_mov_b32_e32 v1, v17
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
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; GPRIDX-NEXT: v_mov_b32_e32 v7, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v7, s5
; GPRIDX-NEXT: v_mov_b32_e32 v6, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s4
; GPRIDX-NEXT: v_mov_b32_e32 v5, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s3
; GPRIDX-NEXT: v_mov_b32_e32 v4, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s0
; GPRIDX-NEXT: s_set_gpr_idx_on s33, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s33, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v2, v0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, v0
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_set_gpr_idx_on s33, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v3, v1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, v1
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v4 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v4
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v5 ; GPRIDX-NEXT: v_readfirstlane_b32 s3, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v6 ; GPRIDX-NEXT: v_readfirstlane_b32 s4, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s5, v7
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; GPRIDX-NEXT: v_mov_b32_e32 v7, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v7, s5
; GPRIDX-NEXT: v_mov_b32_e32 v6, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s4
; GPRIDX-NEXT: v_mov_b32_e32 v5, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s3
; GPRIDX-NEXT: v_mov_b32_e32 v4, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s0
; GPRIDX-NEXT: s_set_gpr_idx_on s33, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s33, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v2, v0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, v0
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_set_gpr_idx_on s33, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v3, v1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, v1
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v4 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v4
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v5 ; GPRIDX-NEXT: v_readfirstlane_b32 s3, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v6 ; GPRIDX-NEXT: v_readfirstlane_b32 s4, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s5, v7
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llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir

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S_SET_GPR_IDX_OFF S_SET_GPR_IDX_OFF
S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit undef $m0 S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit undef $m0
$vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
S_SET_GPR_IDX_OFF S_SET_GPR_IDX_OFF
S_SET_GPR_IDX_ON killed $sgpr1, 1, implicit-def $m0, implicit undef $m0 S_SET_GPR_IDX_ON killed $sgpr1, 1, implicit-def $m0, implicit undef $m0
$vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
S_SET_GPR_IDX_OFF S_SET_GPR_IDX_OFF
... ...
---
name: indirect_mov
body: |
bb.0:
; GCN-LABEL: name: indirect_mov
; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit undef $m0
; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
; GCN: V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3)
; GCN: V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3)
; GCN: S_SET_GPR_IDX_OFF
S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit undef $m0
$vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3)
S_SET_GPR_IDX_OFF
S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit undef $m0
V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3)
S_SET_GPR_IDX_OFF
...