[ARM] Fix MIR tests with invalid live-ins.

[efriedma]

Summary

A register can't be live if it isn't defined; fix issues in various testcases.

(I'm working on a MachineVerifier patch to verify this.)

[samparker]

Thanks.

llvm/test/CodeGen/ARM/constant-islands-split-IT.mir

body:             |
   ; CHECK:   $sp = tMOVr $r0, 0 /* CC::eq */, $cpsr, implicit $itstate
   ; CHECK:   $sp = t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate
   ; CHECK:   tBL 14 /* CC::al */, $noreg, &__stack_chk_fail, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
   ; CHECK: bb.8 (align 8):
   ; CHECK:   successors:
   ; CHECK:   CONSTPOOL_ENTRY 6, %const.0, 8
   ; CHECK: bb.9 (align 2):
   ; CHECK:   successors: %bb.9(0x80000000)
-  ; CHECK:   liveins: $r0
   ; CHECK:   dead renamable $r0 = SPACE 4000, undef renamable $r0
   ; CHECK:   t2B %bb.9, 14 /* CC::al */, $noreg
   ; CHECK: bb.10:
   bb.0:
     successors: %bb.1(0x80000000)
 
     renamable $d0 = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool)
     dead renamable $r0 = SPACE 40, undef renamable $r0
bb.2:
     $r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate
     t2IT 0, 4, implicit-def $itstate
     $sp = tMOVr $r0, 0, $cpsr, implicit $itstate
     $sp = t2LDMIA_RET $sp, 0, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate
     tBL 14, $noreg, &__stack_chk_fail, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
 
   bb.3:
     successors: %bb.3(0x80000000)
-    liveins: $r0
 
     dead renamable $r0 = SPACE 4000, undef renamable $r0
     t2B %bb.3, 14, $noreg
 

llvm/test/CodeGen/ARM/ifcvt-size.mir

bb.0.entry:
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
     liveins: $r0, $r1, $r2, $r3
 
     t2CMPri killed renamable $r2, 4, 14, $noreg, implicit-def $cpsr
     t2Bcc %bb.2, 1, killed $cpsr
 
   bb.1.if.then:
     successors: %bb.3(0x30000000), %bb.4(0x50000000)
-    liveins: $r0, $r3
+    liveins: $r0, $r1, $r3
 
     renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
     renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
     renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
     t2CMPri renamable $r0, 0, 14, $noreg, implicit-def $cpsr
     t2Bcc %bb.3.if2.then, 1, killed $cpsr
     t2B %bb.4.if2.else, 14, $noreg
 

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir

bb.0.entry:
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
     renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
     tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
     t2IT 11, 8, implicit-def $itstate
-    $r1 = t2ADDri killed renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate
+    $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate
     $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
     $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
     renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
     renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
     renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
     renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
     renamable $r2 = tLEApcrel %const.0, 14, $noreg
     renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)

llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir

bb.4.bb12:
     renamable $r8 = t2MOVi 0, 14, $noreg, $noreg
     renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg
     t2DoLoopStart renamable $r3
     $lr = tMOVr killed $r3, 14, $noreg
     renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
 
   bb.5.bb28:
     successors: %bb.5(0x7c000000), %bb.6(0x04000000)
-    liveins: $r0, $r1, $r2, $r3, $r8, $r12, $lr
+    liveins: $r0, $r1, $r2, $r3, $r8, $lr
 
     renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617)
     renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
     renamable $r6 = tLDRr renamable $r2, $r3, 14, $noreg :: (load 4 from %ir.scevgep418)
     $r12 = tMOVr $lr, 14, $noreg
     renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14, $noreg, $noreg
     renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14, $noreg
     renamable $r6 = tLDRr renamable $r0, $r3, 14, $noreg :: (load 4 from %ir.scevgep219)

llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir

 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: predicated_livout
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
   ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
-  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4
   ; CHECK: bb.1.for.body.preheader:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   liveins: $lr, $r0, $r1
   ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
   ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
   ; CHECK: bb.2.for.body:
   ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
   ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r3
   ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
   ; CHECK:   renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.input_2_cast, align 1)
   ; CHECK:   renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.input_1_cast, align 1)
   ; CHECK:   renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
   ; CHECK:   renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, undef renamable $q0
   ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
   ; CHECK: bb.3.middle.block:
   ; CHECK:   liveins: $q0
   ; CHECK:   renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg
   ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
   ; CHECK: bb.4.for.cond.cleanup:
-  ; CHECK:   liveins: $lr, $r7
+  ; CHECK:   liveins: $lr
   ; CHECK:   $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
   ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
   bb.0.entry:
     successors: %bb.1(0x40000000), %bb.4(0x40000000)
     liveins: $r0, $r1, $r2, $lr, $r7
 
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg
     renamable $lr = t2LSRri killed renamable $r3, 3, 14, $noreg, $noreg
-    t2WhileLoopStart killed renamable $lr, %bb.4, implicit-def dead $cpsr
+    t2WhileLoopStart renamable $lr, %bb.4, implicit-def dead $cpsr
     tB %bb.1, 14, $noreg
 
   bb.1.for.body.preheader:
     successors: %bb.2(0x80000000)
     liveins: $r0, $r1, $r2, $lr
 
     renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
     renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
 
   bb.2.for.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
     liveins: $q0, $r0, $r1, $r2, $r3, $lr
 
     renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg
     renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14, $noreg
     renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg
     renamable $lr = t2LoopDec killed renamable $lr, 1
     MVE_VPST 1, implicit $vpr
     renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.input_2_cast, align 1)
     renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.input_1_cast, align 1)
     renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 1, renamable $vpr, undef renamable $q1
     renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 1, killed renamable $vpr, undef renamable $q0
-    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
+    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14, $noreg
 
   bb.3.middle.block:
     liveins: $q0
 
     renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg
     tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
 
   bb.4.for.cond.cleanup:
-    liveins: $lr, $r7
+    liveins: $lr
 
     $r0, dead $cpsr = tMOVi8 0, 14, $noreg
     tBX_RET 14, $noreg, implicit killed $r0
 
 ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir

bb.0.entry:
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     t2DoLoopStart $r0
     renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
     renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
 
   bb.1.preheader:
     successors: %bb.2(0x80000000)
-    liveins: $r0
+    liveins: $r0, $r1
     $lr = tMOVr $r0, 14, $noreg
 
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
     liveins: $lr, $r0, $r1
 
     renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
     early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir

bb.0.entry:
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
     renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
     t2DoLoopStart renamable $r0
     renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg
-    $lr = tMOVr killed $r0, 14, $noreg
+    $lr = tMOVr $r0, 14, $noreg
 
   bb.1.while.body:
     successors: %bb.1(0x7c000000), %bb.2(0x04000000)
     liveins: $lr, $r0, $r1, $r2
 
     renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
     tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2IT 2, 8, implicit-def $itstate
     renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
     early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
     renamable $lr = tMOVr $lr, 14, $noreg
-    t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr
+    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
     tB %bb.2, 14, $noreg
 
   bb.2.while.end:
     $r0, dead $cpsr = tMOVi8 0, 14, $noreg
     tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
 
 ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir

bb.0.entry:
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     t2DoLoopStart $r0
     renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
     renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
 
   bb.1.preheader:
     successors: %bb.2(0x80000000)
-    liveins: $r0, $lr
+    liveins: $r0, $r1, $lr
     $lr = tMOVr $r0, 14, $noreg
   
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
     liveins: $lr, $r0, $r1
   
     renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
     early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir

bb.0.entry:
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     t2DoLoopStart $r0
     renamable $r0 = t2SUBri killed renamable $lr, 4, 14, $noreg, def $cpsr
     renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
 
   bb.1.preheader:
     successors: %bb.2(0x80000000)
-    liveins: $r0
+    liveins: $r0, $r1
     $lr = tMOVr $r0, 14, $noreg
 
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
     liveins: $lr, $r0, $r1
 
     renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
     early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir

 constants:       []
 body:             |
   ; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $q0, $q1, $q2, $r0
   ; CHECK:   $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
   ; CHECK:   $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
-  ; CHECK:   BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
+  ; CHECK:   BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
   ; CHECK:     MVE_VPST 4, implicit $vpr
   ; CHECK:     renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
-  ; CHECK:     renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1
+  ; CHECK:     renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1
   ; CHECK:   }
   ; CHECK: bb.1.bb2:
   ; CHECK:   liveins: $q0, $q1, $q2, $q3, $vpr
   ; CHECK:   BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
   ; CHECK:     MVE_VPST 4, implicit $vpr
   ; CHECK:     renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
   ; CHECK:     renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
   ; CHECK:   }
   ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $q0
   bb.0.entry:
     liveins: $q0, $q1, $q2, $r0
 
     $vpr = VMSR_P0 killed $r0, 14, $noreg
     $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
     renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
-    renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
+    renamable $q1 = nnan ninf nsz MVE_VMINNMf32 renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
 
   bb.1.bb2:
     liveins: $q0, $q1, $q2, $q3, $vpr
 
     renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
     renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
     tBX_RET 14, $noreg, implicit $q0
 
 ...