Implementation of PLT: handling of IFUNC calls (gnu_indirect_function).

[lenykholodov]

Summary

This diff includes implementation of linking calls to ifunc functions. It provides ifunc entries in PLT and corresponding relocations (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G1_NC, R_ARM_LDR_PC_G2 for link-time and R_ARM_IRELATIVE for run-time).

[shankarke]

Can you add testcases for the other relocations that you have in the code ?

[Bigcheese]

Looks good, but needs tests for the other relocations too.

[lenykholodov]

Tests for relocations R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G1_NC, R_ARM_LDR_PC_G2 have been added. All of them were created in manual mode by editing YAML files. Unfortunately, I couldn't find the way how I could generate these relocations with gcc/clang compilation.

[• shankar.easwaran]

Lgtm

[Bigcheese]

lgtm

[denis-protivensky]

The idea of group relocations is that they allow splitting an address up among couple of instructions without making access to the memory with load instruction. It's the optimization, that won't work for offsets more than 2^28 bits in the way it's used (maybe we should add comments into TODO section about that?)

So the three separated tests for group relocations don't really test anything. They should be tested as a group in one test case:

• you point all three relocs at the same function address
• you then show offsets in comments to the content of .rel.plt section as it's done for other tests. Example:

# CHECK: Contents of section .text:                                                                                                                                         
# CHECK: 400084 80b500af fff7f4bf 03461846 80bd00bf                                                                                                                         
#                           ^^ offset = -0x18

• you then show that summing up these offsets gives the address of the function you're pointing at (again in comments):

#               call site  offset  PC(thm) _Z1fv addr                                                                                                                       
#               0x400088 + (-0x18) + 0x4 = 0x400074

I think in this case it's at least understandable what's happening. And the current edition of these three tests just shows that something is generated by lld, but there's no way to check it.

lib/ReaderWriter/ELF/ARM/ARMLinkingContext.h

35

We don't handle dynamic linking yet. Moreover, we don't use any of the relocations in the switch block, so I doubt if this code is needed. You shouldn't add the code that you cannot state is working. Please, remove this function.

66

The same as for isDynamicRelocation - may be removed.

lib/ReaderWriter/ELF/ARM/ARMRelocationHandler.cpp

324

This is better to be implemented as a template function taking count of bits in lshift as a template parameter.
Also, I'd rework this function to:

• calculate shifted result value
• do what current function does
• write the reloc with applyArmReloc

So the prototype would be:

template <uint32_t lshift>
static void reloc_R_ARM_ALU_PC_GN_NC(uint8_t *location, uint32_t result);

The calling function should calculate the result by the formula, dump values in the log, and call this function in the end.

360

There's no T bit in the documentation, so please, update the comment here.

363

For all these three group relocations:
the offset you receive when making calculations, it may be negative.
The reference ("Group relocations", p.32) says how you should handle this case.
Since you don't handle it, you need to put a check and fire llvm_unreachable in that case, so we may later implement proper handling if needed.

437

For these, you don't handle initial addend calculation as for other relocation types, so it's inconsistent.

lib/ReaderWriter/ELF/ARM/ARMRelocationPass.cpp

171

There are more reloc types that can target IFUNC entries. Imagine that someone takes the address of memcpy, so it goes through the ldr instruction (using R_ARM_ABS32 reloc, for example). Other platforms handle most types of relocations with this function just not to miss anything.

252

You shouldn't pollute the symbol table with this sort of needless symbols. Just put

#ifndef NDEBUG
#endif

guard around.

test/elf/ARM/rel-ifunc.test

8

I'd really want to see the explanation of where these three instructions in .plt section point at. I think they should point at the same .got entry where value from .rel.plt section points.

11

You should add .rel.plt section output, and it should point at the .got.plt symbol you specified below.

13

You'd better show where this address ad004000 is pointing at. This should be somewhere in the .text section defining a function to be substituted (you may add it to the symbol table output for simplicity).

[lenykholodov]

• unused methods ARMLinkingContext::isDynamicRelocation and ARMLinkingContext::isRelativeReloc have been removed;
• imlementations of relocations R_ARM_ALU_PC_G0_NC & R_ARM_ALU_PC_G1_NC have been generalized (see relocR_ARM_ALU_PC_GN_NC function);
• initial addends have been ignored because they are read during the relocation applying, for group relocation reference.addend() have been used;
• for negative offsets in group relocations llvm_unreachable has been inserted (full implementation will be done in further patch);
• additional relocs have been processed with ifunc;
• global vars scope was changed to static;
• separate tests for relocations were removed (because of useless);
• test for ifunc has been changed according to the Denis's comment;
• comments were fixed.

[denis-protivensky]

You removed tests for separate group relocations, but didn't add one which tests all the three at a time. Can you please do that?

lib/ReaderWriter/ELF/ARM/ARMRelocationHandler.cpp

326

That's better to be made static_assert

328

static doesn't make sense. Statics use locks in C++11, so why introduce unneeded internal complexity? If you want to have compile-time variable here, use enum { rshift = 32 - lshift }; but I think that regular variable is enough.

329

Remove this empty line.

338

The cast type is wrong. Should be int32_t result = (int32_t)((S + A) - P);

356

The cast is wrong as above.

374

The cast is wrong as above.

380

The result is converted to unsigned while making & operation (because mask is unsigned) then back to signed when assigned. You're also modifying the result value before logging. So I'd propose to move this operation into applyArmReloc:
applyArmReloc(location, (uint32_t)result & mask, mask);

lib/ReaderWriter/ELF/ARM/ARMRelocationPass.cpp

52

I think this code is already in. You should rebase to the actual sources.

124

This code is also in the trunk already.

167

Why don't you handle these two relocs on a subject of IFUNC?

279

We came to using dyn_cast and assuming that ref.target() cannot be null.

[lenykholodov]

• small fixes for group relocations (static_assert, using of static specifier, formatting, types conversion);
• ifunc handling for all available relocations;
• rebasing with master;
• new complex test has been added for three group relocs (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G1_NC, R_ARM_LDR_PC_G2).

[denis-protivensky]

LGTM

[lenykholodov]

I have no commit permission. I would really appreciate if someone could send this patch on my behalf.

[lenykholodov]

• generation of veneers for non jump instructions has been disabled;
• tests have been fixes;
• missing break has been added to the relocations processing switch.

lib/ReaderWriter/ELF/ARM/ARMLinkingContext.h

 namespace lld {
 namespace elf {
 
 class ARMLinkingContext final : public ELFLinkingContext {
 public:
   static std::unique_ptr<ELFLinkingContext> create(llvm::Triple);
   ARMLinkingContext(llvm::Triple);
 
+  bool isRelaOutputFormat() const override { return false; }
+
   void addPasses(PassManager &) override;
 
   uint64_t getBaseAddress() const override {
     if (_baseAddress == 0)
       return 0x400000;
     return _baseAddress;
   }
+
+  bool isDynamicRelocation(const Reference &r) const override {
+    if (r.kindNamespace() != Reference::KindNamespace::ELF)
+      return false;
+    assert(r.kindArch() == Reference::KindArch::ARM);
+    switch (r.kindValue()) {
+    case llvm::ELF::R_ARM_TLS_DTPMOD32:
+    case llvm::ELF::R_ARM_TLS_DTPOFF32:
+    case llvm::ELF::R_ARM_TLS_TPOFF32:
+    case llvm::ELF::R_ARM_COPY:
+    case llvm::ELF::R_ARM_GLOB_DAT:
+    case llvm::ELF::R_ARM_JUMP_SLOT:
+    case llvm::ELF::R_ARM_RELATIVE:
+      return true;
+    default:
+      return false;
+    }
+  }
+
+  bool isPLTRelocation(const Reference &r) const override {
+    if (r.kindNamespace() != Reference::KindNamespace::ELF)
+      return false;
+    assert(r.kindArch() == Reference::KindArch::ARM);
+    switch (r.kindValue()) {
+    case llvm::ELF::R_ARM_JUMP_SLOT:
+    case llvm::ELF::R_ARM_IRELATIVE:
+      return true;
+    default:
+      return false;
+    }
+  }
+
+  bool isRelativeReloc(const Reference &r) const override {
+    if (r.kindNamespace() != Reference::KindNamespace::ELF)
+      return false;
+    assert(r.kindArch() == Reference::KindArch::ARM);
+    switch (r.kindValue()) {
+    case llvm::ELF::R_ARM_RELATIVE:
+      return true;
+    default:
+      return false;
+    }
+  }
 };
 } // end namespace elf
 } // end namespace lld
 
 #endif

lib/ReaderWriter/ELF/ARM/ARMRelocationHandler.cpp

DEBUG_WITH_TYPE(
       "ARM", llvm::dbgs() << "\t\tHandle " << LLVM_FUNCTION_NAME << " -";
       llvm::dbgs() << " S: 0x" << Twine::utohexstr(S);
       llvm::dbgs() << " A: 0x" << Twine::utohexstr(A);
       llvm::dbgs() << " P: 0x" << Twine::utohexstr(P);
       llvm::dbgs() << " result: 0x" << Twine::utohexstr(result) << "\n");
   return relocR_ARM_THM_MOV(location, arg);
 }
 
+static uint32_t formALU_PC_GN(uint32_t val, uint32_t lshift) {
+  assert(lshift < 32 && lshift % 2 == 0);
+  const uint32_t rshift = 32 - lshift;
+  return (val & 0xFF) | ((rshift / 2) << 8);
+}
+
+/// \brief R_ARM_ALU_PC_G0_NC - ((S + A) | T) - P => S + A - P
+static void relocR_ARM_ALU_PC_G0_NC(uint8_t *location, uint64_t P, uint64_t S,
+                                    int64_t A) {
+  uint32_t result = (uint32_t)((S + A) - P);
+  result = result >> 20;
+  result = formALU_PC_GN(result, 20);
+  DEBUG_WITH_TYPE(
+      "ARM", llvm::dbgs() << "\t\tHandle " << LLVM_FUNCTION_NAME << " -";
+      llvm::dbgs() << " S: 0x" << Twine::utohexstr(S);
+      llvm::dbgs() << " A: 0x" << Twine::utohexstr(A);
+      llvm::dbgs() << " P: 0x" << Twine::utohexstr(P);
+      llvm::dbgs() << " result: 0x" << Twine::utohexstr(result) << "\n");
+  applyArmReloc(location, result, 0xFFF);
+}
+
+/// \brief R_ARM_ALU_PC_G1_NC - ((S + A) | T) - P => S + A - P
+static void relocR_ARM_ALU_PC_G1_NC(uint8_t *location, uint64_t P, uint64_t S,
+                                    int64_t A) {
+  uint32_t result = (uint32_t)((S + A) - P);
+  result = result >> 12;
+  result = formALU_PC_GN(result, 12);
+  DEBUG_WITH_TYPE(
+      "ARM", llvm::dbgs() << "\t\tHandle " << LLVM_FUNCTION_NAME << " -";
+      llvm::dbgs() << " S: 0x" << Twine::utohexstr(S);
+      llvm::dbgs() << " A: 0x" << Twine::utohexstr(A);
+      llvm::dbgs() << " P: 0x" << Twine::utohexstr(P);
+      llvm::dbgs() << " result: 0x" << Twine::utohexstr(result) << "\n");
+  applyArmReloc(location, result, 0xFFF);
+}
+
+/// \brief R_ARM_LDR_PC_G2 - ((S + A) | T) - P => S + A - P
+static void relocR_ARM_LDR_PC_G2(uint8_t *location, uint64_t P, uint64_t S,
+                                 int64_t A) {
+  uint32_t result = (uint32_t)((S + A) - P);
+  const uint32_t mask = 0xFFF;
+  result = result & mask;
+  DEBUG_WITH_TYPE(
+      "ARM", llvm::dbgs() << "\t\tHandle " << LLVM_FUNCTION_NAME << " -";
+      llvm::dbgs() << " S: 0x" << Twine::utohexstr(S);
+      llvm::dbgs() << " A: 0x" << Twine::utohexstr(A);
+      llvm::dbgs() << " P: 0x" << Twine::utohexstr(P);
+      llvm::dbgs() << " result: 0x" << Twine::utohexstr(result) << "\n");
+  applyArmReloc(location, result, mask);
+}
+
 std::error_code ARMTargetRelocationHandler::applyRelocation(
     ELFWriter &writer, llvm::FileOutputBuffer &buf, const lld::AtomLayout &atom,
     const Reference &ref) const {
   uint8_t *atomContent = buf.getBufferStart() + atom._fileOffset;
   uint8_t *location = atomContent + ref.offsetInAtom();
   uint64_t targetVAddress = writer.addressOfAtom(ref.target());
   uint64_t relocVAddress = atom._virtualAddr + ref.offsetInAtom();
 
   if (ref.kindNamespace() != Reference::KindNamespace::ELF)
     return std::error_code();
   assert(ref.kindArch() == Reference::KindArch::ARM);
 
   // Calculate proper initial addend for the relocation
   const Reference::Addend addend =
case R_ARM_MOVT_ABS:
     break;
   case R_ARM_THM_MOVW_ABS_NC:
     relocR_ARM_THM_MOVW_ABS_NC(location, relocVAddress, targetVAddress, addend,
                                addressesThumb);
     break;
   case R_ARM_THM_MOVT_ABS:
     relocR_ARM_THM_MOVT_ABS(location, relocVAddress, targetVAddress, addend);
     break;
+  case R_ARM_ALU_PC_G0_NC:
+    relocR_ARM_ALU_PC_G0_NC(location, relocVAddress, targetVAddress, addend);
+    break;
+  case R_ARM_ALU_PC_G1_NC:
+    relocR_ARM_ALU_PC_G1_NC(location, relocVAddress, targetVAddress, addend);
+    break;
+  case R_ARM_LDR_PC_G2:
+    relocR_ARM_LDR_PC_G2(location, relocVAddress, targetVAddress, addend);
+    break;
+  case R_ARM_IRELATIVE:
+    // Runtime only relocations. Ignore here.
+    break;
   default:
     return make_unhandled_reloc_error();
   }
 
   return std::error_code();
 }

lib/ReaderWriter/ELF/ARM/ARMRelocationPass.cpp

 // TODO: consider different instruction set for archs above ARMv5
 // (one as for ARM may be used since it's more optimal).
 const uint8_t Veneer_THM_B_BL_StaticAtomContent[8] = {
     0x78, 0x47,              // bx pc
     0x00, 0x00,              // nop
     0xfe, 0xff, 0xff, 0xea   // b <target_symbol_address>
 };
 
+// .got values
+const uint8_t ARMGotAtomContent[4] = {0, 0, 0, 0};
+
+// .plt values (other entries)
+const uint8_t ARMPltAtomContent[12] = {
+    0x00, 0xc0, 0x8f,
+    0xe2, // add    ip, pc, #offset[G0]
+    0x00, 0xc0, 0x8c,
+    0xe2, // add    ip, ip, #offset[G1]
+
+    0x00, 0xf0, 0xbc,
+    0xe5, // ldr    pc, [ip, #offset[G2]]!
+};
+
 /// \brief Atoms that hold veneer code.
 class VeneerAtom : public SimpleELFDefinedAtom {
   StringRef _section;
 
 public:
   VeneerAtom(const File &f, StringRef secName)
       : SimpleELFDefinedAtom(f), _section(secName) {}
 
DefinedAtom::CodeModel codeModel() const override {
     return DefinedAtom::codeARMThumb;
   }
 
   ArrayRef<uint8_t> rawContent() const override {
     return llvm::makeArrayRef(Veneer_THM_B_BL_StaticAtomContent);
   }
 };
 
+/// \brief Atoms that are used by ARM dynamic linking
+class ARMGOTAtom : public GOTAtom {
+public:
+  ARMGOTAtom(const File &f, StringRef secName) : GOTAtom(f, secName) {}
+
+  ArrayRef<uint8_t> rawContent() const override {
+    return llvm::makeArrayRef(ARMGotAtomContent);
+  }
+
+  Alignment alignment() const override { return Alignment(2); }
+};
+
+class ARMPLTAtom : public PLTAtom {
+public:
+  ARMPLTAtom(const File &f, StringRef secName) : PLTAtom(f, secName) {}
+
+
+  ArrayRef<uint8_t> rawContent() const override {
+    return llvm::makeArrayRef(ARMPltAtomContent);
+  }
+};
+
 class ELFPassFile : public SimpleFile {
 public:
   ELFPassFile(const ELFLinkingContext &eti) : SimpleFile("ELFPassFile") {
     setOrdinal(eti.getNextOrdinalAndIncrement());
   }
 
   llvm::BumpPtrAllocator _alloc;
 };
 
 /// \brief CRTP base for handling relocations.
 template <class Derived> class ARMRelocationPass : public Pass {
   /// \brief Handle a specific reference.
   void handleReference(const DefinedAtom &atom, const Reference &ref) {
     DEBUG_WITH_TYPE(
         "ARM", llvm::dbgs() << "\t" << LLVM_FUNCTION_NAME << "()"
             << ":   Name of Defined Atom: " << atom.name().str();
         llvm::dbgs() << "   kindValue: " << ref.kindValue() << "\n");
     if (ref.kindNamespace() != Reference::KindNamespace::ELF)
       return;
     assert(ref.kindArch() == Reference::KindArch::ARM);
     switch (ref.kindValue()) {
     case R_ARM_JUMP24:
     case R_ARM_THM_JUMP24:
       static_cast<Derived *>(this)->handleVeneer(atom, ref);
       break;
+    case R_ARM_CALL:
+    case R_ARM_THM_CALL:
+      static_cast<Derived *>(this)->handleIFUNC(ref);
+      break;
     }
   }
 
 protected:
   std::error_code handleVeneer(const DefinedAtom &atom, const Reference &ref) {
     // Target symbol and relocated place should have different
     // instruction sets in order a veneer to be generated in between.
     const auto *target = dyn_cast_or_null<DefinedAtom>(ref.target());
default:
       llvm_unreachable("Unhandled reference type for veneer generation");
     }
 
     assert(veneer && "The veneer is not set");
     const_cast<Reference &>(ref).setTarget(veneer);
     return std::error_code();
   }
 
+  /// \brief Create a PLT entry referencing PLTGOT entry.
+  ///
+  /// The function creates the PLT entry object and passes ownership
+  /// over it to the caller.
+  PLTAtom *createPLTforGOT(const GOTAtom *ga) {
+    auto pa = new (_file._alloc) ARMPLTAtom(_file, ".plt");
+    pa->addReferenceELF_ARM(R_ARM_ALU_PC_G0_NC, 0, ga, -8);
+    pa->addReferenceELF_ARM(R_ARM_ALU_PC_G1_NC, 4, ga, -4);
+    pa->addReferenceELF_ARM(R_ARM_LDR_PC_G2, 8, ga, 0);
+    return pa;
+  }
+
+  /// \brief get the PLT entry for a given IFUNC Atom.
+  ///
+  /// If the entry does not exist. Both the GOT and PLT entry is created.
+  const PLTAtom *getIFUNCPLTEntry(const DefinedAtom *da) {
+    auto plt = _pltMap.find(da);
+    if (plt != _pltMap.end())
+      return plt->second;
+    auto ga = new (_file._alloc) ARMGOTAtom(_file, ".got.plt");
+    ga->addReferenceELF_ARM(R_ARM_ABS32, 0, da, 0);
+    ga->addReferenceELF_ARM(R_ARM_IRELATIVE, 0, da, 0);
+    auto pa = createPLTforGOT(ga);
+
+    ga->_name = "__got_ifunc_";
+    ga->_name += da->name();
+    pa->_name = "__plt_ifunc_";
+    pa->_name += da->name();
+
+    _gotMap[da] = ga;
+    _pltMap[da] = pa;
+    _gotVector.push_back(ga);
+    _pltVector.push_back(pa);
+    return pa;
+  }
+
+  /// \brief Handle adding of PLT entry by marking the reference
+  /// as requiring veneer generation.
+  std::error_code handlePLTEntry(Reference &ref, const PLTAtom *pa) {
+    ref.setTarget(pa);
+
+    return std::error_code();
+  }
+
+  /// \brief Redirect the call to the PLT stub for the target IFUNC.
+  ///
+  /// This create a PLT and GOT entry for the IFUNC if one does not exist. The
+  /// GOT entry and a IRELATIVE relocation to the original target resolver.
+  std::error_code handleIFUNC(const Reference &ref) {
+    auto target = dyn_cast_or_null<const DefinedAtom>(ref.target());
+    if (target && target->contentType() == DefinedAtom::typeResolver) {
+      return handlePLTEntry(const_cast<Reference &>(ref),
+                            getIFUNCPLTEntry(target));
+    }
+    return std::error_code();
+  }
 public:
   ARMRelocationPass(const ELFLinkingContext &ctx) : _file(ctx), _ctx(ctx) {}
 
   /// \brief Do the pass.
   ///
   /// The goal here is to first process each reference individually. Each call
   /// to handleReference may modify the reference itself and/or create new
   /// atoms which must be stored in one of the maps below.
void perform(std::unique_ptr<MutableFile> &mf) override {
     }
 
     // Add all created atoms to the link.
     uint64_t ordinal = 0;
     for (auto &veneer : _veneerVector) {
       veneer->setOrdinal(ordinal++);
       mf->addAtom(*veneer);
     }
+    for (auto &plt : _pltVector) {
+      plt->setOrdinal(ordinal++);
+      mf->addAtom(*plt);
+    }
+    for (auto &got : _gotVector) {
+      got->setOrdinal(ordinal++);
+      mf->addAtom(*got);
+    }
   }
 
 protected:
   /// \brief Owner of all the Atoms created by this pass.
   ELFPassFile _file;
   const ELFLinkingContext &_ctx;
 
   /// \brief Map Atoms to their veneers.
   llvm::DenseMap<const Atom *, VeneerAtom *> _veneerMap;
 
   /// \brief the list of veneer atoms.
   std::vector<VeneerAtom *> _veneerVector;
+
+  /// \brief Map Atoms to their GOT entries.
+  llvm::DenseMap<const Atom *, GOTAtom *> _gotMap;
+
+  /// \brief Map Atoms to their PLT entries.
+  llvm::DenseMap<const Atom *, PLTAtom *> _pltMap;
+  /// \brief the list of GOT/PLT atoms
+  std::vector<GOTAtom *> _gotVector;
+  std::vector<PLTAtom *> _pltVector;
 };
 
 /// This implements the static relocation model. Meaning GOT and PLT entries are
 /// not created for references that can be directly resolved. These are
 /// converted to a direct relocation. For entries that do require a GOT or PLT
 /// entry, that entry is statically bound.
 ///
 /// TLS always assumes module 1 and attempts to remove indirection.

test/elf/ARM/rel-ifunc.test

+# Check handling of IFUNC (gnu_indirect_function).
+# RUN: yaml2obj -format=elf %s > %t-o.o
+# RUN: lld -flavor gnu -target arm -m armelf_linux_eabi -Bstatic \
+# RUN: %t-o.o -o %t
+# RUN: llvm-objdump -s -t %t | FileCheck %s
+
+# CHECK: Contents of section .plt:
+# CHECK: 400080 00c68fe2 00ca8ce2 78ffbce5
+# CHECK-NEXT: Contents of section .text:
+# CHECK: 40013c 80b500af fff7ccff fff79cef 00231846
+# CHECK: Contents of section .got.plt:
+# CHECK: 401000 ad004000
+# CHECK: SYMBOL TABLE:
+# CHECK: 00400074 g       *ABS* 00000000 __rel_iplt_start
+# CHECK: 0040007c g       *ABS* 00000000 __rel_iplt_end
+
+---
+FileHeader:      
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_ARM
+  Flags:           [ EF_ARM_EABI_VER5 ]
+Sections:        
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000004
+    Content:         80B400AF01231846BD465DF8047B704780B400AF02231846BD465DF8047B704780B400AF40F20003C0F200031846BD465DF8047B704700BF80B582B000AF78607B689847034618460837BD4680BD00BF80B584B000AF40F20003C0F20003FB601BE0FB68BB60BB681B687B60BB685B68DBB23B603B68A02B0CBF01230023DBB2002B07D07B681B681846FFF7D5FF02467B681A60FB680833FB60FA6840F20003C0F200039A42DCD31037BD4680BD00BF80B500AFFFF7CCFFFFF7FEFF0023184680BD00BF
+  - Name:            .rel.text
+    Type:            SHT_REL
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .text
+    Relocations:     
+      - Offset:          0x0000000000000024
+        Symbol:          myfunc1
+        Type:            R_ARM_THM_MOVW_ABS_NC
+      - Offset:          0x0000000000000028
+        Symbol:          myfunc1
+        Type:            R_ARM_THM_MOVT_ABS
+      - Offset:          0x0000000000000056
+        Symbol:          __rel_iplt_start
+        Type:            R_ARM_THM_MOVW_ABS_NC
+      - Offset:          0x000000000000005A
+        Symbol:          __rel_iplt_start
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