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Differential D77185

[WebAssembly] Rename SIMD min/max/avgr intrinsics for consistency
ClosedPublic

Authored by tlively on Mar 31 2020, 5:11 PM.

Details

Reviewers
aheejin
Commits
rG95fac2e46b73: [WebAssembly] Rename SIMD min/max/avgr intrinsics for consistency
Summary

The convention for the wasm_simd128.h intrinsics is to have the
integer sign in the lane interpretation rather than as a suffix. This
PR changes the names of the integer min, max, and avgr intrinsics to
match this convention.

Diff Detail

Event Timeline

tlively created this revision.Mar 31 2020, 5:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 31 2020, 5:12 PM
Herald added subscribers: cfe-commits, sunfish, jgravelle-google and 2 others. · View Herald Transcript
Harbormaster failed remote builds in B51221: Diff 254047!Mar 31 2020, 6:45 PM
aheejin accepted this revision.Apr 1 2020, 9:32 AM
This revision is now accepted and ready to land.Apr 1 2020, 9:32 AM
Closed by commit rG95fac2e46b73: [WebAssembly] Rename SIMD min/max/avgr intrinsics for consistency (authored by tlively). · Explain WhyApr 1 2020, 9:54 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
clang/
lib/
Headers/
56 lines

Diff 254233

clang/lib/Headers/wasm_simd128.h

Show First 20 Lines • Show All 644 Lines • ▼ Show 20 Lines return (v128_t)__builtin_wasm_sub_saturate_u_i8x16((__i8x16)__a,
(__i8x16)__b); (__i8x16)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_mul(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_mul(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)((__u8x16)__a * (__u8x16)__b); return (v128_t)((__u8x16)__a * (__u8x16)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_min_s(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_min(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_min_s_i8x16((__i8x16)__a, (__i8x16)__b); return (v128_t)__builtin_wasm_min_s_i8x16((__i8x16)__a, (__i8x16)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_min_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_min(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_min_u_i8x16((__i8x16)__a, (__i8x16)__b); return (v128_t)__builtin_wasm_min_u_i8x16((__i8x16)__a, (__i8x16)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_max_s(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_max(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_max_s_i8x16((__i8x16)__a, (__i8x16)__b); return (v128_t)__builtin_wasm_max_s_i8x16((__i8x16)__a, (__i8x16)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_max_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_max(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_max_u_i8x16((__i8x16)__a, (__i8x16)__b); return (v128_t)__builtin_wasm_max_u_i8x16((__i8x16)__a, (__i8x16)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_avgr_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_avgr(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_avgr_u_i8x16((__i8x16)__a, (__i8x16)__b); return (v128_t)__builtin_wasm_avgr_u_i8x16((__i8x16)__a, (__i8x16)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_abs(v128_t __a) { static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_abs(v128_t __a) {
return (v128_t)__builtin_wasm_abs_i16x8((__i16x8)__a); return (v128_t)__builtin_wasm_abs_i16x8((__i16x8)__a);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_neg(v128_t __a) { static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_neg(v128_t __a) {
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines return (v128_t)__builtin_wasm_sub_saturate_u_i16x8((__i16x8)__a,
(__i16x8)__b); (__i16x8)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_mul(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_mul(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)((__u16x8)__a * (__u16x8)__b); return (v128_t)((__u16x8)__a * (__u16x8)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_min_s(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_min(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_min_s_i16x8((__i16x8)__a, (__i16x8)__b); return (v128_t)__builtin_wasm_min_s_i16x8((__i16x8)__a, (__i16x8)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_min_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u16x8_min(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_min_u_i16x8((__i16x8)__a, (__i16x8)__b); return (v128_t)__builtin_wasm_min_u_i16x8((__i16x8)__a, (__i16x8)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_max_s(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_max(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_max_s_i16x8((__i16x8)__a, (__i16x8)__b); return (v128_t)__builtin_wasm_max_s_i16x8((__i16x8)__a, (__i16x8)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_max_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u16x8_max(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_max_u_i16x8((__i16x8)__a, (__i16x8)__b); return (v128_t)__builtin_wasm_max_u_i16x8((__i16x8)__a, (__i16x8)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_avgr_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u16x8_avgr(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_avgr_u_i16x8((__i16x8)__a, (__i16x8)__b); return (v128_t)__builtin_wasm_avgr_u_i16x8((__i16x8)__a, (__i16x8)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_abs(v128_t __a) { static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_abs(v128_t __a) {
return (v128_t)__builtin_wasm_abs_i32x4((__i32x4)__a); return (v128_t)__builtin_wasm_abs_i32x4((__i32x4)__a);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_neg(v128_t __a) { static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_neg(v128_t __a) {
Show All 33 Linesstatic __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_sub(v128_t __a,
return (v128_t)((__u32x4)__a - (__u32x4)__b); return (v128_t)((__u32x4)__a - (__u32x4)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_mul(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_mul(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)((__u32x4)__a * (__u32x4)__b); return (v128_t)((__u32x4)__a * (__u32x4)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_min_s(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_min(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_min_s_i32x4((__i32x4)__a, (__i32x4)__b); return (v128_t)__builtin_wasm_min_s_i32x4((__i32x4)__a, (__i32x4)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_min_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u32x4_min(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_min_u_i32x4((__i32x4)__a, (__i32x4)__b); return (v128_t)__builtin_wasm_min_u_i32x4((__i32x4)__a, (__i32x4)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_max_s(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_max(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_max_s_i32x4((__i32x4)__a, (__i32x4)__b); return (v128_t)__builtin_wasm_max_s_i32x4((__i32x4)__a, (__i32x4)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i32x4_max_u(v128_t __a, static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u32x4_max(v128_t __a,
v128_t __b) { v128_t __b) {
return (v128_t)__builtin_wasm_max_u_i32x4((__i32x4)__a, (__i32x4)__b); return (v128_t)__builtin_wasm_max_u_i32x4((__i32x4)__a, (__i32x4)__b);
} }
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i64x2_neg(v128_t __a) { static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i64x2_neg(v128_t __a) {
return (v128_t)(-(__u64x2)__a); return (v128_t)(-(__u64x2)__a);
} }
#ifdef __wasm_unimplemented_simd128__ #ifdef __wasm_unimplemented_simd128__
▲ Show 20 Lines • Show All 302 Lines • Show Last 20 Lines