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[X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory form
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Authored by craig.topper on Mar 3 2020, 11:13 AM.

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Summary

uops.info says these should be 15 cycle instructions. Uops.info also shows the 512-bit form uses port 0 and 5 for both register and memory. We had memory using 0 and 1.

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Event Timeline

craig.topper created this revision.Mar 3 2020, 11:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 3 2020, 11:13 AM
RKSimon accepted this revision.Mar 3 2020, 11:27 AM

LGTM - Agner mostly agrees (but misses the port05 for the Z512 case)

This revision is now accepted and ready to land.Mar 3 2020, 11:27 AM
This revision was automatically updated to reflect the committed changes.