uops.info says these should be 15 cycle instructions. Uops.info also shows the 512-bit form uses port 0 and 5 for both register and memory. We had memory using 0 and 1.
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[X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory form ClosedPublic Authored by craig.topper on Mar 3 2020, 11:13 AM.
Details Summary uops.info says these should be 15 cycle instructions. Uops.info also shows the 512-bit form uses port 0 and 5 for both register and memory. We had memory using 0 and 1.
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Event TimelineThis revision is now accepted and ready to land.Mar 3 2020, 11:27 AM Closed by commit rG02f03a6fd4cd: [X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory… (authored by craig.topper). · Explain WhyMar 3 2020, 12:37 PM This revision was automatically updated to reflect the committed changes.
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Diff 247990 llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dq.s
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dqvl.s
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