[ARM] Add armv6s[-]m as an alias to armv6[-]m

[bsmith]

Summary

Patch to add armv6s[-]m as an alias to armv6[-]m.

LLVM currently does not model the M-class OS extension, but instead enables its features by default for armv6-m targets. Technically the correct name for this architecture would be armv6s-m, although in order to avoid breaking current use cases this patch adds armv6s-m as an alias to armv6-m instead of properly modelling the OS extension (which is probably not necessary).

(Testcases for this will be under a separate clang review).

[bsmith]

Testcases under D7505.

[jroelofs]

Please add a tests in:

llvm/test/CodeGen/ARM/build-attributes.ll
llvm/test/MC/ARM/arm-thumb-cpus.s

[jroelofs]

Specifically, you should also add a note on the test for .eabi_attribute 6, 12 saying that we're emitting the wrong one when -march=armv6-m is specified on the command line, and the correct one when -march=armv6s-m is specified.

[bsmith]

Add extra tests for armv6s[-]m target.

[jroelofs]

Thanks! LGTM.

[bsmith]

Thanks, committed as r228696.

lib/Support/Triple.cpp

if (ArchName.startswith("armv")) {
     offset = 7;
     arch = Triple::thumbeb;
   }
   return StringSwitch<Triple::ArchType>(ArchName.substr(offset))
     .Cases("v2", "v2a", isThumb ? Triple::UnknownArch : arch)
     .Cases("v3", "v3m", isThumb ? Triple::UnknownArch : arch)
     .Cases("v4", "v4t", arch)
     .Cases("v5", "v5e", "v5t", "v5te", "v5tej", arch)
-    .Cases("v6", "v6j", "v6k", "v6m", arch)
+    .Cases("v6", "v6j", "v6k", "v6m", "v6sm", arch)
     .Cases("v6t2", "v6z", "v6zk", arch)
     .Cases("v7", "v7a", "v7em", "v7l", arch)
     .Cases("v7m", "v7r", "v7s", arch)
     .Cases("v8", "v8a", arch)
     .Default(Triple::UnknownArch);
 }
 
 static Triple::ArchType parseArch(StringRef ArchName) {
return StringSwitch<Triple::SubArchType>(SubArchName)
     .EndsWith("v7a", Triple::ARMSubArch_v7)
     .EndsWith("v7em", Triple::ARMSubArch_v7em)
     .EndsWith("v7l", Triple::ARMSubArch_v7)
     .EndsWith("v7m", Triple::ARMSubArch_v7m)
     .EndsWith("v7r", Triple::ARMSubArch_v7)
     .EndsWith("v7s", Triple::ARMSubArch_v7s)
     .EndsWith("v6", Triple::ARMSubArch_v6)
     .EndsWith("v6m", Triple::ARMSubArch_v6m)
+    .EndsWith("v6sm", Triple::ARMSubArch_v6m)
     .EndsWith("v6t2", Triple::ARMSubArch_v6t2)
     .EndsWith("v5", Triple::ARMSubArch_v5)
     .EndsWith("v5e", Triple::ARMSubArch_v5)
     .EndsWith("v5t", Triple::ARMSubArch_v5)
     .EndsWith("v5te", Triple::ARMSubArch_v5te)
     .EndsWith("v4t", Triple::ARMSubArch_v4t)
     .EndsWith("kalimba3", Triple::KalimbaSubArch_v3)
     .EndsWith("kalimba4", Triple::KalimbaSubArch_v4)
result = llvm::StringSwitch<const char *>(MArch.substr(offset))
       .Case("v4t", "arm7tdmi")
       .Cases("v5", "v5t", "arm10tdmi")
       .Cases("v5e", "v5te", "arm1022e")
       .Case("v5tej", "arm926ej-s")
       .Cases("v6", "v6k", "arm1136jf-s")
       .Case("v6j", "arm1136j-s")
       .Cases("v6z", "v6zk", "arm1176jzf-s")
       .Case("v6t2", "arm1156t2-s")
-      .Cases("v6m", "v6-m", "cortex-m0")
+      .Cases("v6m", "v6-m", "v6sm", "v6s-m", "cortex-m0")
       .Cases("v7", "v7a", "v7-a", "v7l", "v7-l", "cortex-a8")
       .Cases("v7s", "v7-s", "swift")
       .Cases("v7r", "v7-r", "cortex-r4")
       .Cases("v7m", "v7-m", "cortex-m3")
       .Cases("v7em", "v7e-m", "cortex-m4")
       .Cases("v8", "v8a", "v8-a", "cortex-a53")
       .Default(nullptr);
   else

test/CodeGen/ARM/build-attributes.ll

 ; This tests that MC/asm header conversion is smooth and that the
 ; build attributes are correct
 
 ; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale | FileCheck %s --check-prefix=XSCALE
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s --check-prefix=V6
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
+; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi | FileCheck %s --check-prefix=V6M
+; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast  | FileCheck %s --check-prefix=ARM1156T2F-S-FAST
 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7M-FAST
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING

 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
 ;; positive zero here. There's no hardware support doing this, but the
 ;; fast maths software library might.
 ; V6-FAST-NOT:   .eabi_attribute 20
 ; V6-FAST-NOT:   .eabi_attribute 21
 ; V6-FAST-NOT:   .eabi_attribute 22
 ; V6-FAST:   .eabi_attribute 23, 1
 
+;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
+;; V6-M, however we don't model the OS extension so this is fine.
 ; V6M:  .eabi_attribute 6, 12
 ; V6M-NOT:  .eabi_attribute 7
 ; V6M:  .eabi_attribute 8, 0
 ; V6M:  .eabi_attribute 9, 1
 ; V6M-NOT:   .eabi_attribute 19
 ;; The default choice made by llc is for a V6M CPU without an FPU.
 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
 ;; software floating-point support. The choice is not important for targets without

test/MC/ARM/arm-thumb-cpus.s

 @ RUN:  | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
 
 @ RUN: not llvm-mc -show-encoding -triple=armv7m-eabi < %s 2>&1 \
 @ RUN:  | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
 
 @ RUN: not llvm-mc -show-encoding -triple=armv6m-eabi < %s 2>&1 \
 @ RUN:  | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
 
+@ RUN: not llvm-mc -show-encoding -triple=armv6sm-eabi < %s 2>&1 \
+@ RUN:  | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+
         @ Make sure correct diagnostics are given for CPUs without support for
         @ one or other of the execution states.
         .thumb
         .arm
         .code 16
         .code 32
 @ CHECK-ARM-THUMB-NOT: target does not support
 
 @ CHECK-ARM-ONLY: target does not support Thumb mode
 @ CHECK-ARM-ONLY: target does not support Thumb mode
 
 @ CHECK-THUMB-ONLY: target does not support ARM mode
 @ CHECK-THUMB-ONLY: target does not support ARM mode