AMDGPU: Use undef_tied_input on VOP3P instructions

[arsenm]

Summary

In a future commit this will help simplify patterns.

[arsenm]

This needs additional work in tablegen to avoid some ugly codegen hacks, since the operand ends up not getting a register class

llvm/lib/Target/AMDGPU/SIInstrInfo.td

def SRCMODS {
 
   int NEG_HI = ABS;
   int OP_SEL_0 = 4;
   int OP_SEL_1 = 8;
   int DST_OP_SEL = 8;
 }
 
 def DSTCLAMP {
-  int NONE = 0;
-  int ENABLE = 1;
+  bit NONE = 0;
+  bit ENABLE = 1;
 }
 
 def DSTOMOD {
   int NONE = 0;
 }
 
 def TRAPID{
   int LLVM_TRAP = 2;

llvm/lib/Target/AMDGPU/VOP3PInstructions.td

 //===-- VOP3PInstructions.td - Vector Instruction Defintions --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // VOP3P Classes
 //===----------------------------------------------------------------------===//
 
+class vdst_in_op32<ValueType vt> :
+  OperandWithDefaultOps<vt, (VGPR_32 undef_tied_input)>;
+
 class VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
   VOP3P_Pseudo<OpName, P,
     !if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret)
 >;
 
 // Non-packed instructions that use the VOP3P encoding.
 // VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.
 class VOP3_VOP3PInst<string OpName, VOPProfile P, bit UseTiedOutput = 0,
                      SDPatternOperator node = null_frag> :
   VOP3P_Pseudo<OpName, P> {
   // These operands are only sort of f16 operands. Depending on
   // op_sel_hi, these may be interpreted as f32. The inline immediate
   // values are really f16 converted to f32, so we treat these as f16
   // operands.
   let InOperandList =
     !con(
       !con(
         (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
              FP16InputMods:$src1_modifiers, VCSrc_f16:$src1,
              FP16InputMods:$src2_modifiers, VCSrc_f16:$src2,
              clampmod:$clamp),
-         !if(UseTiedOutput, (ins VGPR_32:$vdst_in), (ins))),
+         !if(UseTiedOutput, (ins vdst_in_op32<P.DstVT>:$vdst_in), (ins))),
          (ins op_sel:$op_sel, op_sel_hi:$op_sel_hi));
 
   let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", "");
   let DisableEncoding = !if(UseTiedOutput, "$vdst_in", "");
   let AsmOperands =
     " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
 }
 
multiclass MadFmaMixPats<SDPatternOperator fma_like,
   def : GCNPat <
     (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
                             (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)),
                             (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))),
     (mixlo_inst $src0_modifiers, $src0,
                 $src1_modifiers, $src1,
                 $src2_modifiers, $src2,
                 DSTCLAMP.NONE,
-                (i32 (IMPLICIT_DEF)))
+                (IMPLICIT_DEF))
   >;
 
   // FIXME: Special case handling for maxhi (especially for clamp)
   // because dealing with the write to high half of the register is
   // difficult.
   def : GCNPat <
     (build_vector f16:$elt0, (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
                                                 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)),
def : GCNPat <
     (v2f16 (mixhi_inst $hi_src0_modifiers, $hi_src0,
                        $hi_src1_modifiers, $hi_src1,
                        $hi_src2_modifiers, $hi_src2,
                        DSTCLAMP.ENABLE,
                        (mixlo_inst $lo_src0_modifiers, $lo_src0,
                                    $lo_src1_modifiers, $lo_src1,
                                    $lo_src2_modifiers, $lo_src2,
                                    DSTCLAMP.ENABLE,
-                                   (i32 (IMPLICIT_DEF)))))
+                                   (IMPLICIT_DEF))))
   >;
 }
 
 let SubtargetPredicate = HasMadMixInsts in {
 // These are VOP3a-like opcodes which accept no omod.
 // Size of src arguments (16/32) is controlled by op_sel.
 // For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
 let isCommutable = 1 in {