[llvm][MIR-Canon] Adding support for avoiding collisions across constant pool indices.

[plotfi]

Summary

When hashing on MachineOperand::MO_ConstantPoolIndex, now MIR-Canon and MIRVRegNamer will no longer result in a hash collision.

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

case MachineOperand::MO_Register:
       if (Register::isVirtualRegister(MO.getReg()))
         return MRI.getVRegDef(MO.getReg())->getOpcode();
       return MO.getReg();
     case MachineOperand::MO_Immediate:
       return MO.getImm();
     case MachineOperand::MO_TargetIndex:
       return MO.getOffset() | (MO.getTargetFlags() << 16);
     case MachineOperand::MO_FrameIndex:
+    case MachineOperand::MO_ConstantPoolIndex:
       return llvm::hash_value(MO);
 
     // We could explicitly handle all the types of the MachineOperand,
     // here but we can just return a common number until we find a
     // compelling test case where this is bad. The only side effect here
     // is contributing to a hash collision but there's enough information
     // (Opcodes,other registers etc) that this will likely not be a problem.
 
     // TODO: Handle the following Index/ID/Predicate cases. They can
     // be hashed on in a stable manner.
-    case MachineOperand::MO_ConstantPoolIndex:
     case MachineOperand::MO_JumpTableIndex:
     case MachineOperand::MO_CFIIndex:
     case MachineOperand::MO_IntrinsicID:
     case MachineOperand::MO_Predicate:
 
     // In the cases below we havn't found a way to produce an artifact that will
     // result in a stable hash, in most cases because they are pointers. We want
     // stable hashes because we want the hash to be the same run to run.

llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir

+# RUN: llc -o - -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
+--- |
+  target triple = "aarch64-unknown-unknown"
+  define void @f() { unreachable }
+...
+---
+name: f
+constants:
+  - id:              0
+    value:           '<1 x i8> <i8 0>'
+  - id:              1
+    value:           '<1 x i8> <i8 1>'
+body: |
+  bb.0:
+    ; Test that we no longer have hash collisions between two different consts:
+    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
+    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
+    %vreg0:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    %vreg1:gpr64common = ADRP target-flags(aarch64-page) %const.1
+...